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JPH01205590A - Circuit board - Google Patents

Circuit board

Info

Publication number
JPH01205590A
JPH01205590A JP63028976A JP2897688A JPH01205590A JP H01205590 A JPH01205590 A JP H01205590A JP 63028976 A JP63028976 A JP 63028976A JP 2897688 A JP2897688 A JP 2897688A JP H01205590 A JPH01205590 A JP H01205590A
Authority
JP
Japan
Prior art keywords
substrate
circuit board
stepped portion
cracks
aluminum nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63028976A
Other languages
Japanese (ja)
Other versions
JP2637136B2 (en
Inventor
Hideki Sato
英樹 佐藤
Masakazu Hajima
羽島 雅一
Nobuyuki Mizunoya
水野谷 信幸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP63028976A priority Critical patent/JP2637136B2/en
Priority to US07/250,635 priority patent/US4906511A/en
Priority to EP88309137A priority patent/EP0310437B1/en
Priority to DE3854293T priority patent/DE3854293T2/en
Priority to KR1019880012887A priority patent/KR910007470B1/en
Publication of JPH01205590A publication Critical patent/JPH01205590A/en
Application granted granted Critical
Publication of JP2637136B2 publication Critical patent/JP2637136B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Structure Of Printed Boards (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PURPOSE:To prevent chipping or cracks on a periphery of an aluminum nitride substrate surface for applying metallizing past, by forming a gently curved step thereon. CONSTITUTION:A lower stepped section 13 is formed on a periphery of a surface 11a of an AlN substrate 11. The two projecting corner edges of the step 13, that is, a crossing edge section 14 of a rising surface 13b of the step 13 and a surface 11a of the substrate 11, and a crossing stepped section 15 of a bottom 13b of the step 13 and an outer circumference 11b of the substrate 11 are formed in a gently curved surface. Even if impact or load works on the stepped section while handling, stress concentration to the projecting and recessed corner edge sections can be thereby prevented. In this way, chipping of the projecting edge section or cracks on the recessed corner edge section can be prevented.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明はレラミックベースの回路基板に係り、特に窒化
アルミニウム基板を用いた回路基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a circuit board based on a reramic base, and particularly to a circuit board using an aluminum nitride substrate.

(従来の技術) 従来、半導体回路基板どじで化較的安価なアルミナ(A
j!203)基板を用いたものが多用されている。しか
し、近年、半導体装置の大出力化に伴って素子の発熱量
か増大し、これまでのAl2O3基板の放熱性では熱対
策が不十分となってさている。そこで最近では放熱性に
優れた窒化アルミニウム(Aj!N)基板を用いた回路
基板が利用され始めている。
(Prior art) Conventionally, relatively inexpensive alumina (A
j! 203) Those using a substrate are often used. However, in recent years, as the output of semiconductor devices has increased, the amount of heat generated by elements has increased, and the heat dissipation properties of conventional Al2O3 substrates have become insufficient as a heat countermeasure. Therefore, recently, circuit boards using aluminum nitride (Aj!N) substrates, which have excellent heat dissipation properties, have begun to be used.

ところで、このような回路基板では△IN基板の表面に
タングステン(W)またはモリブデン(Mo)等のメタ
ライズ層を形成し、このメタライズ層の表面にニッケル
(N : >等のメツキにより導体層を形成している。
By the way, in such a circuit board, a metallized layer such as tungsten (W) or molybdenum (Mo) is formed on the surface of the △IN board, and a conductor layer is formed on the surface of this metallized layer by plating with nickel (N: >, etc.). are doing.

この導体層に半導体素子および電極を兼ねるリードフレ
ーム等を接合している。
A semiconductor element and a lead frame that also serves as an electrode are bonded to this conductor layer.

A矛N基板へのメタライス層の形成は、△1N基板の表
面にメタライズペース1−を塗tfi シ、これを焼成
してメタライズ部を硬化させることによって行なってい
る。この場合、第3図に示すように、△ff1N基板1
の周縁面1aを表面部1bに直角な裁断形状にしておく
と、表面に塗布したメタライズペースト2が周縁部1a
に垂れ下り、これにより耐電圧が低下したり、メタライ
ズペースト2の垂下部分2aにひび割れが生じてメタラ
イズ不良を起こり−ことがある。
Formation of the metallized layer on the Δ1N substrate is carried out by applying metallizing paste 1- to the surface of the Δ1N substrate and baking it to harden the metallized portion. In this case, as shown in FIG.
If the peripheral edge surface 1a is cut into a shape perpendicular to the surface portion 1b, the metallization paste 2 applied to the surface will be cut into the peripheral edge portion 1a.
As a result, the withstand voltage may decrease, or cracks may occur in the hanging portion 2a of the metallizing paste 2, resulting in poor metallization.

そこで第4図に示すように、AIN基板1の周縁部1a
と表面部1bとの間に段部3を形成し、この段部3でメ
タライズペースト2の垂下部分2aを止め、AjN基板
1の周縁部1aにメタライズペースト2の垂れが及ばな
いようにすることが考えられる。
Therefore, as shown in FIG.
A step portion 3 is formed between the surface portion 1b and the step portion 3, and the hanging portion 2a of the metallizing paste 2 is stopped by the step portion 3, so that the hanging portion 2a of the metallizing paste 2 does not reach the peripheral portion 1a of the AJN substrate 1. is possible.

(発明が解決しようとする課題) ところが、第4図に示ず回路基板では、AjN基板1の
段部3の突出隅角縁部3a、3bが欠損したりζ窪み隅
角縁部3Cにクラックか生じる場合がある。
(Problem to be Solved by the Invention) However, in the circuit board not shown in FIG. 4, the protruding corner edges 3a and 3b of the stepped portion 3 of the AjN board 1 are damaged, and the ζ recessed corner edge 3C is cracked. may occur.

本発明はこのような事情に鑑みてなされたもので、メタ
ライズ不良による耐電圧低下を防止でさることは勿論、
A、&N基板の段部での欠損やクラックの発生も防1]
二できる回路基板を提供覆ることを1」的とする。
The present invention was made in view of these circumstances, and it not only prevents a drop in withstand voltage due to poor metallization, but also
Prevents damage and cracks from occurring at stepped parts of A, &N boards 1]
2) Provide a circuit board that can be used to cover the 1' target.

〔発明の構成〕[Structure of the invention]

(課題を解決覆るだめの手段) 本発明は窒化アルミニウム基板の表面にメタライズペー
ス1へを塗布し、これを焼成してメタライズ層を形成し
てなる回路基板において、前記窒化アルミニウム基板の
メタライズペースト塗布用表面の周縁部分に一段低い段
部を形成し、その段部の突出隅角縁部と窪み隅角縁部と
を緩かな曲面どしだことを特徴どづる。
(Means for Solving the Problems) The present invention provides a circuit board in which a metallization paste 1 is applied to the surface of an aluminum nitride substrate and then fired to form a metallization layer. The present invention is characterized in that a lower step is formed at the peripheral edge of the surface, and the protruding corner edge and the recessed corner edge of the step are gently curved.

(作用) 本発明によれば、窒化アルミニウム基板のメタライズペ
ースト塗布用表面の周縁部分に形成した一段低い段部の
突出隅角縁部と窪み隅角縁部とを緩かな曲面としたこと
により、取扱い中に段部に衝撃や荷重が作用しても、そ
の段部の突出隅角縁部や窪み隅角縁部への応力集中を防
止できる。
(Function) According to the present invention, the protruding corner edge and the recessed corner edge of the lower step formed on the peripheral edge of the metallizing paste application surface of the aluminum nitride substrate are made into gently curved surfaces. Even if an impact or load is applied to the stepped portion during handling, stress concentration on the protruding corner edges or recessed corner edges of the stepped portion can be prevented.

したかっ−C1突出隅角縁部か衝撃にJ:り欠損したり
、窪み隅角縁部に荷重によるクラックが生じ−J   
 − たりすることを防止でき、窒化アルミニウム基板の健全
性維持が図れるようになる。
- The protruding corner edge of C1 was damaged due to impact, and the concave corner edge cracked due to the load - J
- It is possible to prevent damage to the aluminum nitride substrate and maintain the integrity of the aluminum nitride substrate.

なお、前記曲面の応力集中回避のための望ましい曲率半
径の範囲は0.01〜0.5mmである。
Note that the desirable range of the radius of curvature for avoiding stress concentration on the curved surface is 0.01 to 0.5 mm.

(実施例) 以下、本発明の一実施例を第1図および第2図を参照し
て説明する。
(Example) An example of the present invention will be described below with reference to FIGS. 1 and 2.

第1図はこの実施例の回路基板を示し、熱伝導率が50
W/m−に以上の窒化アルミニウム(AIN>基板11
の表面にタングステン(W>またはモリブデン(MO)
を成分としたメタライズ層12を形成し、さらにその表
面に図示しないがニッケル(N i >合金その他の金
属からなる導電層を介してシリコンチップ等の半導体素
子を装着した構成とされる。
Figure 1 shows the circuit board of this example, with a thermal conductivity of 50
Aluminum nitride (AIN>substrate 11
Tungsten (W> or molybdenum (MO)) on the surface of
A metallized layer 12 is formed, and a semiconductor element such as a silicon chip is mounted on the surface of the metallized layer 12 through a conductive layer (not shown) made of nickel (N i >alloy or other metal).

A ffl N 1%板11の表面11aの周縁部分に
は一段低い段部13が形成されており、その段部13の
底面13aは基板表面11aと略平行であるが立上り面
13bば基板表面11aに対して例えば60°の傾斜を
なす斜面とされている。なお、A−−/−1,− fflN基板11の外周面11bから中心側への段部1
3の底面13aの幅S【よ0.2mm、また、段差りは
0.3mmとされている。
A lower step 13 is formed at the peripheral edge of the surface 11a of the AfflN 1% board 11, and the bottom surface 13a of the step 13 is approximately parallel to the substrate surface 11a, but the rising surface 13b is parallel to the substrate surface 11a. For example, the slope is inclined at 60° with respect to the slope. Note that the stepped portion 1 from the outer circumferential surface 11b of the A--/-1,-fflN substrate 11 to the center side
The width S of the bottom surface 13a of No. 3 is 0.2 mm, and the step is 0.3 mm.

このものにおいて、AIN基板11の段部13の2つの
突出隅角縁部、即ぢ段部13の立上り面13bとAIN
基板110表面11aとの交差縁部14 、a5よび段
部13の底面13bとAJN基板11の外周面11bと
の交差段部15は、それぞれ半径が約0.2mmの緩か
な曲面とされている。
In this thing, two protruding corner edges of the stepped portion 13 of the AIN board 11, namely the rising surface 13b of the stepped portion 13 and the AIN
The intersecting edge 14 with the surface 11a of the substrate 110, a5, and the intersecting stepped portion 15 between the bottom surface 13b of the stepped portion 13 and the outer peripheral surface 11b of the AJN substrate 11 are each formed into a gently curved surface with a radius of about 0.2 mm. .

また、段部13の窪み隅角縁部、即ち底面13aと立」
二り面13bとの交差窪み部16も、半径0.2mmの
緩かな曲面とされている。
In addition, the corner edge of the recess of the stepped portion 13, that is, the bottom surface 13a and the
The concave portion 16 intersecting with the two surfaces 13b is also a gently curved surface with a radius of 0.2 mm.

そして、前記のメタライズ層12の形成は、メタライズ
ペーストをAfN基板11の表面11aに外周縁部まで
印刷法に」:って所定の厚さをもって塗布し、その後こ
れを焼成して硬化させることにより行なわれる。この場
合、メタライズペーストはAiN基板11の周縁部から
垂下する可能性があるが、段部13を設(プたことによ
って、その立」ニリ面13bおよび底面13aで停滞し
、AJ2N基板11の外周面11には垂下しない。した
がって、耐電圧特性か低下することはない。
The metallized layer 12 is formed by applying a metallized paste to the surface 11a of the AfN substrate 11 up to the outer periphery using a printing method to a predetermined thickness, and then baking and hardening it. It is done. In this case, there is a possibility that the metallization paste hangs down from the periphery of the AiN substrate 11, but due to the provision of the stepped portion 13, it stagnates on the vertical angular surface 13b and bottom surface 13a, and the metallization paste hangs down from the outer periphery of the AJ2N substrate 11. It does not hang down to the surface 11. Therefore, the withstand voltage characteristics do not deteriorate.

また、前記の段部13の突出隅角縁部14,15を緩か
な曲面としたので、この部分に衝撃力が加わっても欠損
が生じにくい。しかも段部13の窪み隅角縁部16も緩
かな曲面としたので、例えば段部13の底面13aに図
の下向きに荷重が作用したような場合でも、応力集中か
起こらず、クラックが発生しにくい。
Furthermore, since the protruding corner edges 14 and 15 of the stepped portion 13 are formed into gently curved surfaces, breakage is unlikely to occur even if an impact force is applied to these portions. Moreover, since the concave corner edge 16 of the stepped portion 13 is also made into a gently curved surface, even if, for example, a load is applied downward in the figure to the bottom surface 13a of the stepped portion 13, stress concentration will not occur and cracks will not occur. Hateful.

さらに、このような構成にJ:れば、回路基板のコンバ
ク1〜化J3よび経済性向−Lを図りつつ基板の健全性
を維持するという点でもきわめて効果的なものとなる。
Further, such a configuration is extremely effective in maintaining the integrity of the circuit board while achieving economic efficiency and economical efficiency of the circuit board.

即ち、AJN基板11の表面の周縁部を除いた一定範囲
にメタライズペース1へを塗布すれば、メタライズペー
ストの垂下が起らないので前記の段部13を設(プる必
要はない。しかし、それではメタライズ層以上の余分な
面積がAJN基板11に必要となり、それだ(プ回路基
板が人形化、高コス1−化することになる。このことに
対処するために、前記の段部13を形成した訳であるか
、このままでは段部13に欠損やクラックが生じ、健全
性を損う可能性がある。これに対して段部13を曲面と
したことにより、欠損やクラックの防止が図れ、コンバ
ク(〜化および低コスト化とともに健全性も維持できる
ようになるものである。
That is, if the metallizing paste 1 is applied to a certain area of the surface of the AJN substrate 11 excluding the peripheral edge, the metallizing paste will not sag, so there is no need to provide the stepped portion 13. However, In this case, an extra area larger than the metallized layer will be required for the AJN board 11, which will make the printed circuit board into a doll and a high cost. Perhaps because of the formation, if left as is, chips or cracks may occur in the stepped portion 13, which may impair its integrity.On the other hand, by making the stepped portion 13 a curved surface, chips or cracks can be prevented. , it will be possible to maintain soundness as well as to reduce costs and reduce costs.

特に半導体回路基板の大容量化に対して、放熱性に優れ
たAfN基根11の利用がより有効に図れるという利点
は大きい。
Particularly for increasing the capacity of semiconductor circuit boards, there is a great advantage in that the AfN base 11, which has excellent heat dissipation properties, can be used more effectively.

41お、第2図に示すように、前記実施例のものと略同
−形状、寸法のAJN基板11′について段部13′の
突出隅角縁部14’、15’および窪み隅角縁部16′
を曲面どしないものを試作し、前記実施例のものと比較
したところ、前記実施例のものに対するよりも小ざい衝
撃や荷重によって、突出隅角縁部14’、15’ の欠
損あるいは窪み隅角縁部16′へのクラック発生が生じ
ることが認められた。
41, as shown in FIG. 2, for an AJN board 11' having substantially the same shape and dimensions as those of the previous embodiment, the protruding corner edges 14' and 15' of the stepped portion 13' and the recessed corner edges 16'
When we made a prototype with a curved surface and compared it with the one in the previous example, we found that the protruding corner edges 14', 15' were damaged or the corner was depressed due to a smaller impact or load than the one in the previous example. It was observed that cracks occurred at the edge 16'.

なa3、本発明では前記実施例で示した寸法、具体的形
状等に必ずしもとられれず、段部の欠損、クラック発生
を防止することができる範囲での種−/− 々の変形、応用等が可能なことは勿論である。
A3: In the present invention, the dimensions and specific shapes etc. shown in the above embodiments are not necessarily adopted, and various modifications, applications, etc. can be made within the range that can prevent chipping of the stepped portion and generation of cracks. Of course, this is possible.

〔発明の効果] 以上のように、本発明ににれば、窒化アルミニウム基板
のメタライズペースト塗布用表面の周縁部分に形成した
段部を緩かな曲面としたことにより、その部分の欠損や
クラック発生防止が図れ、メタライズ不良による耐電圧
低下防止は勿論、健全性を大幅に向上することができる
という優れた効果が奏される。
[Effects of the Invention] As described above, according to the present invention, by forming the stepped portion formed at the peripheral portion of the metallizing paste application surface of the aluminum nitride substrate into a gently curved surface, it is possible to prevent defects and cracks from occurring in that portion. This has the excellent effect of not only preventing a drop in withstand voltage due to poor metallization but also significantly improving soundness.

【図面の簡単な説明】 第1図は本発明に係る回路基板の一実施例を示す部分拡
大断面図、第2図は比較例を示す部分拡大断面図、第3
図および第4図は互いに異なる従来例を示す部分拡大断
面図である。 11・・・AIN基板、11a・・・表面、11b・・
・外周面(側面)、12・・・メタライズ層、13・・
・段部、1/1..15・・・突出隅角縁部、16・・
・窪み隅角縁部。 第3 図 第4 図
[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a partially enlarged cross-sectional view showing an embodiment of a circuit board according to the present invention, FIG. 2 is a partially enlarged cross-sectional view showing a comparative example, and FIG.
This figure and FIG. 4 are partially enlarged sectional views showing conventional examples different from each other. 11...AIN board, 11a...surface, 11b...
・Outer peripheral surface (side surface), 12...Metallized layer, 13...
・Double section, 1/1. .. 15...Protruding corner edge, 16...
- Concave corner edge. Figure 3 Figure 4

Claims (1)

【特許請求の範囲】[Claims] 窒化アルミニウム基板の表面にメタライズペーストを塗
布し、これを焼成してメタライズ層を形成してなる回路
基板において、前記窒化アルミニウム基板のメタライズ
ペースト塗布用表面の周縁部分に一段低い段部を形成し
、その段部の突出隅角縁部と窪み隅角縁部とを緩かな曲
面としたことを特徴とする回路基板。
In a circuit board formed by applying a metallization paste to the surface of an aluminum nitride substrate and firing it to form a metallization layer, a lower step is formed at a peripheral portion of the surface for applying the metallization paste of the aluminum nitride substrate, A circuit board characterized in that a protruding corner edge and a recessed corner edge of the stepped portion are formed into gently curved surfaces.
JP63028976A 1987-02-12 1988-02-12 Circuit board Expired - Lifetime JP2637136B2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP63028976A JP2637136B2 (en) 1988-02-12 1988-02-12 Circuit board
US07/250,635 US4906511A (en) 1987-02-12 1988-09-29 Aluminum nitride circuit board
EP88309137A EP0310437B1 (en) 1987-09-30 1988-09-30 Method of manufacturing a metallised aluminium nitride circuit board
DE3854293T DE3854293T2 (en) 1987-09-30 1988-09-30 Process for manufacturing a metallized aluminum nitride circuit substrate.
KR1019880012887A KR910007470B1 (en) 1987-09-30 1988-09-30 Aluminium nitride circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63028976A JP2637136B2 (en) 1988-02-12 1988-02-12 Circuit board

Publications (2)

Publication Number Publication Date
JPH01205590A true JPH01205590A (en) 1989-08-17
JP2637136B2 JP2637136B2 (en) 1997-08-06

Family

ID=12263452

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63028976A Expired - Lifetime JP2637136B2 (en) 1987-02-12 1988-02-12 Circuit board

Country Status (1)

Country Link
JP (1) JP2637136B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011155172A (en) * 2010-01-28 2011-08-11 Seiko Epson Corp Electronic apparatus, and method of manufacturing the same
CN102185580A (en) * 2010-01-18 2011-09-14 精工爱普生株式会社 Electronic apparatus, method of manufacturing substrate, and method of manufacturing electronic apparatus

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513866U (en) * 1974-06-26 1976-01-12

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS513866U (en) * 1974-06-26 1976-01-12

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102185580A (en) * 2010-01-18 2011-09-14 精工爱普生株式会社 Electronic apparatus, method of manufacturing substrate, and method of manufacturing electronic apparatus
US8941017B2 (en) 2010-01-18 2015-01-27 Seiko Epson Corporation Electronic apparatus, method of manufacturing substrate, and method of manufacturing electronic apparatus
JP2011155172A (en) * 2010-01-28 2011-08-11 Seiko Epson Corp Electronic apparatus, and method of manufacturing the same

Also Published As

Publication number Publication date
JP2637136B2 (en) 1997-08-06

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