JPH01205461A - Manufacture of amorphous silicon thin film transistor array substrate - Google Patents

Abstract

PURPOSE:To avoid the roughness of a glass surface, and prevent undercut at a wiring terminal part, by making an amorphous silicon layer deposited in such a manner as to cover the connection terminal part of a gate wiring, and eliminating the amorphous silicon layer covering the connection terminal part of the gate wiring, at the time of patterning. CONSTITUTION:On a glass substrate 1 on which a gate wiring 2 is arranged, silicon nitride or silicon oxide turning to a gate insulating layer 3 is deposited by applying a connection terminal part to a mask by using a metal mask. Successively an intrinsic a-Si layer 4 is deposited on the whole substrate surface without a metal mask. Further silicon nitride or silicon oxide turning to a protective insulating layer 5 is deposited on the whole substrate surface without using a metal mask. Next, the protective insulating layer 5 is selectively etched by using buffer hydrofluoric acid solution. Since, at this time, the whole substrate is covered with the intrinsic a-Si layer 4, a connection terminal part 6 of the gate wiring and the glass substrate 1 are not etched. When etching is performed by using organic alkali system solution, the intrinsic a-Si layer 4 covering the connection terminal part of the gate wiring is simultaneously eliminated, so that the connection terminal 6 of the gate wiring is exposed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to amorphous silicon (amorphous silicon) used in active matrix type liquid crystal displays, etc.
us-S 11icon (hereinafter referred to as a-3i) thin film transistor (Thin Pi 1 mTra
nsistor (hereinafter referred to as T PT ) relates to a method of manufacturing an array substrate.

[Prior art] In recent years, LCD trix displays,
In particular, so-called active matrix type liquid crystal displays, in which a switching element is provided for each pixel, are being researched and developed in various places. For this switching element, an old S type TPT using a-3i is mainly used.

FIG. 2 schematically shows a configuration example of an active matrix type liquid crystal display using T F i'.

When, for example, Xl is selected among the scanning lines 11, the gates of the TPTs 13-a connected to it are turned on all at once, and through the sources of these turned-on TPTs, signals corresponding to image information are transmitted from each signal line ]2. Signal voltage <Each 'I'P'T'
13-a train.

A pixel electrode (not shown) is connected to the train, and the light transmittance of the liquid crystal layer 14 is determined by the voltage difference between this pixel electrode and a counter electrode 15 formed on the other substrate across the liquid crystal layer 4. The image is displayed by changing the .

xl or unlucky'' (when the state is reached, each 1'' that follows this)
F T13-a's gate is turned off and Xi
+] is selected, the gate of each TPT 13-L+ connected to this is turned on, and the same operation as above is performed. Even after the case is turned off, the voltage difference between the pixel electrode and the counter electrode 15 is stored in the liquid crystal layer I4 until the same scanning line is selected next, so the liquid crystal corresponding to each pixel is The a-Si TFT used for TFT 13 is statically driven and has high contrast.
Then, TP'r, which is manufactured by sequentially depositing a gate insulating layer, an a-Si layer, and a protective insulating layer, is considered to be a promising manufacturing method from the viewpoint of reliability, reproducibility of the manufacturing process, etc. It has become.

Figure 3 shows Actitsuma manufactured using the above manufacturing method!・a-Si'rF used in RIX-type liquid crystal displays
'I' This is a schematic representation of an example of f7 in manufacturing, and will be explained below using this figure.

(a) A metal layer such as Cr is selectively deposited on a glass substrate 21, a gate electrode 22 and a gate electrode 1/wiring (not shown) are formed, followed by a gate insulating layer made of silicon nitride or silicon oxide. 23. Intrinsie a-Si (intrinsic a-Si), which does not contain any impurities, becomes the active layer.
Si. Hereinafter, a (ia-Si) layer 24 and a protective insulating layer 25 made of silicon nitride or silicon oxide are deposited, for example, by plasma CVD.

(I) Selectively etching the protective insulating layer 25 with a buffered hydrofluoric acid solution so that it partially overlaps the gate electrode 22.
The ia-Si layer 24 is exposed.

(C) An n-type a-Si (hereinafter na-Si) layer 26 containing an appropriate amount of phosphorus as an impurity and a metal layer 27 such as Ti are sequentially deposited, the metal layer 27 is selectively etched, and this is used as a source. and patterned into the shape of the drain electrode,
Using the patterns of the metal layer 27 and the protective insulating layer 25 as masks, the na-34 layer 26 and the 1-a-Si layer 24 are etched using an organic alkaline solution to form an island structure.

(d) A transparent conductive layer 28 such as ITO is deposited and selectively removed to form source wiring and pixel electrodes.

Through the above-described steps, a-S as shown in Fig. 3(d) is obtained.
i Complete TPT.

By the way, the above description mainly refers to the manufacturing lens frame of the TPT main body, and manufacturing was carried out with the following points in mind in the peripheral area of the substrate, particularly at the terminal end of the gate wiring. Since the gate wiring needs to be connected to the external circuit via the gate wiring connection terminal, it must be exposed in the end.In order to simplify the process,
For example, as shown in FIG. 4, each layer was deposited by placing a metal mask 31 on a glass substrate 21 to prevent each layer from being deposited on the connection terminal portion of the gate wiring.

"Invention or problem to be solved" By the way, when each layer is deposited using a metal mask,
Each layer is not deposited not only on the connection terminal of the gate I/wiring but also on the surrounding glass substrate. Therefore, in the above-mentioned TPT manufacturing process, when the protective insulating layer made of silicon nitride or silicon oxide is etched with a buffered hydrofluoric acid solution, the surface of the glass substrate is also etched at the same time.

FIG. 5 schematically shows the state of the connection terminal portion of the gate wiring at this time. In the conventional method, the surface of the glass substrate is etched, resulting in problems such as roughening of the glass surface 29 or undercuts 30 at the ends of the cable 1 and wiring. In particular, the undercut 30 causes the gate wiring terminal to peel off, etc., and is a contributing factor to a decrease in manufacturing yield.

The present invention has been made in view of the above-mentioned conventional drawbacks, and aims to eliminate roughness on the glass surface and undercutting at the gate wiring terminal portion.

[Means for Solving the Problems] According to the present invention, a gate wiring having a predetermined shape and a glass substrate -1- on which the gate wiring is installed are provided with - 〇 - Case 1 - Insulating layer, amorphous silicon. The process includes sequentially depositing a layer and a protective insulating layer, and after the process, at least 11% amorphous silicon thin layer is formed through a predetermined manufacturing process.
l-Amorphous thin film l-ransistor array, case 1, wiring and source wiring manufactured by l/
In the method of manufacturing a substrate, the Ga-1 and insulating layers are
・The amorphous silicon layer is deposited to cover the connection terminal part of the cable wiring without covering the connection terminal part of the cable wiring, and when patterning the amorphous silicon layer, the amorphous silicon layer is deposited to cover the connection terminal part of the cable wiring. By manufacturing the device with a step of removing the existing amorphous silicon layer, the objective is achieved.

[Example] An embodiment of the present invention will now be described with reference to FIG.

1 is a horn substrate, 2 is a gate 1/wiring, 3 is a gate 1/silicon nitride or silicon oxide which will be an insulating layer, 4 is a 1
-a-3i layer, 5 is silicon nitride or silicon oxide serving as a protective insulating layer, and 6 is a connection terminal.

In addition, since there is no difference in the +111 configuration of the TPT main body or the manufacturing method from the conventional one, in the following explanation, it is preferable to refer to FIG.

(a) Gate electrode (not shown) and gate 1/wiring 2
Silicon nitride or silicon oxide, which will become the case 1 and the insulating layer 3, is deposited on the glass film (plate 1) using a metal mask to mask the connection terminals of the case 1 and the wiring 2, and then 1-a-3i layer 4 is deposited on the entire surface of the substrate without using a metal mask, and silicon nitride or silicon oxide, which will become the protective insulating layer 5, is further deposited on the entire surface of the substrate without using a metal mask. The plasma CVI) method is suitable for the deposition of Further, the protective insulating layer 5 may be deposited using a metal mask.

(1)) The protective insulating layer 5 is selectively etched using a buffered hydrofluoric acid solution. At this time, since the i-a-3i layer 4 covers the entire board, the connection terminal portion 6 of the cable wiring and the glass plate 1 are not attacked at all by the buffered hydrofluoric acid solution.

(C) n-a-3i layer (Fig. 3 26), metal layer (third
27) were sequentially deposited, and the metal layers were patterned in the shape of source and train electrodes, and using the patterns of the metal layer and protective insulating layer as masks, the na-a-9i layer, the 1-a-8i layer, and the 1-a-8i layer were formed.
is etched using an organic alkaline solution. At this time, the connection terminal part of the gate wiring was covered 1-a-3
Since the i-layer 4 is also removed at the same time, the connection terminal 6 of the gate wiring is exposed. Finally, deposit a transparent conductive layer such as ITO,
This is selectively removed to form source wiring and pixel electrodes.

By going through step 1 above, a connection terminal portion of the gate wiring 2 without roughness due to etching on the surface of the glass substrate as shown in FIG. 1(C) can be obtained.

[Effects of the Invention] As mentioned above, according to the present invention, when etching the protective insulating layer with buffered hydrofluoric acid solution ltM, since the entire substrate is covered with the amorphous silicon layer, the gate The connection terminals of the wiring will not be damaged in any way. Therefore, the film of the cable 1 and the wiring does not suffer from any flaking caused by etching the glass substrate, contributing to an improvement in manufacturing yield. Furthermore, since the amorphous silicon layer is deposited using a metal mask, the film thickness distribution becomes more uniform compared to when a metal mask is used, and the stability and reproducibility of transistor characteristics are improved. Note that the above effect can be achieved only by the presence or absence of a metal mask when depositing the gate insulating layer and the amorphous silicon layer, so there is no particular increase in the number of manufacturing steps.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of an embodiment of the present invention;
Figure 2 is an electrical circuit diagram showing the principle of an active matrix liquid crystal display, and Figure 3 is an amorphous silicon thin film! - A cross-sectional view showing an example of a transistor manufacturing process, FIG. 4 is a perspective view showing the relationship between a glass substrate and a metal mask, and FIG. 5 is a cross-sectional view showing an end of a substrate manufactured by a conventional method. 1... Glass substrate, 2. Kate wiring, 3. Gate insulating layer, 4. Amorphous silicon layer, 5. Protective insulating layer, 6. Connection terminal.

Claims (1)

[Claims] It includes a step of sequentially depositing a gate insulating layer, an amorphous silicon layer, and a protective insulating layer on a glass substrate on which a gate electrode and gate wiring having a predetermined shape are installed. In a manufacturing method of an amorphous silicon thin film transistor array substrate manufactured through a manufacturing process to include at least an amorphous silicon thin film transistor array, a gate wiring, and a source wiring, the gate insulating layer connects a connecting terminal portion of the gate wiring. The amorphous silicon layer is deposited so as not to cover the connecting terminal portion of the gate wiring, and the amorphous silicon layer is deposited so as to cover the connecting terminal portion of the gate wiring, and when patterning the amorphous silicon layer, covers the connecting terminal portion of the gate wiring. 1. A method of manufacturing an amorphous silicon thin film transistor array substrate, the method comprising the step of removing an amorphous silicon layer.