JPH01204461A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent a semiconductor integrated circuit from erroneously operating due to a parasitic transistor by connecting a first diffused region of P-type to a semiconductor substrate. CONSTITUTION:A P-type resistor 2 and crossover wirings 5 formed with an N-type second diffused region 52 in a P-type first diffused region 51 are provided in an insular region isolated from an N-type epitaxial layer 1 formed on a P-type semiconductor substrate 8, and a third diffused region of P-type and the P-type region 51 of the wirings 5 are connected to the substrate 8. Accordingly, even if the potential of the layer 1 becomes lower than that of the resistor 2 so that parasitic P-N-P transistors 10, 12 are operated to cause currents to flow, the currents flow to the substrate 8. thus, the current does not flow to the base of a parasitic N-P-N transistor 11 thereby to prevent a current from flowing to the wiring 5. In this manner, it can prevent it from erroneously operating due to the parasitic transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit, and particularly to a structure for preventing malfunctions caused by parasitic transistors when a resistor is formed near a crossover wiring body.

2. Description of the Related Art FIG. 4 shows a plan view of an example of a conventional semiconductor integrated circuit, FIG. 5 shows a cross-sectional view taken along the line B-B' in FIG. This will be explained with reference to an equivalent circuit diagram of the structure.

In a semiconductor integrated circuit, as shown in the figure, when wiring layers intersect, a crossover wiring body may be formed near a resistor. In Figures 4 and 6, 1 is N
2 is a P-type resistor, 3 is a wiring layer connecting the P-type resistor 2 and the external connection terminal 4, and 5 is an N-type diffusion region 52 provided in a P-type diffusion region 51. 6 is a wiring layer connected to the crossover wiring body 5, and 8 is a P-type semiconductor substrate.

In the above configuration, a parasitic PNP transistor 10 is configured by the P-type resistor 2, the N-type epitaxial layer 1, and the P-type diffusion region 51, and the parasitic PNP transistor 10 is N-type diffusion region 52
A parasitic NPN (NPN) transistor 11 is configured by the crossover wiring body 5 provided with a parasitic NPN transistor. An equivalent circuit diagram formed by these parasitic transistors is shown in FIG. By the way, it is common to use the N-type epitaxial layer 1 with a potential higher than the potential of the P-type resistor 2 and the crossover wiring body 5. For this reason, a parasitic PNP transistor or a parasitic NPN transistor is configured. However, there is no problem because those parasitic transistors do not operate.

Problems to be Solved by the Invention In such a conventional semiconductor integrated circuit, if the potential of the N-type epitaxial layer 1 becomes lower than that of the P-type resistor 2 for some reason in the circuit, the P-type A parasitic PNP transistor and a parasitic NPN transistor, which are composed of a resistor 2, an N-type epitaxial layer 1, and a crossover wiring body 5 in which an N-type diffusion region 52 is provided in a P-type diffusion region 51, operate, A current flows from the P-type resistor 2 through the N-type epitaxial layer 1 toward the P-type diffusion region 51 . When the current generated by this parasitic PNP transistor flows into the P-type diffusion region 51 forming the base of the parasitic NPN transistor, the current flows from the N-type epitaxial layer 1 to the crossover wiring body 5, and the crossover wiring The liquid flows out to the wiring layer 6 connected to the body 5. Therefore, there was a problem that the potential of the wiring layer 6 fluctuated. The present invention solves such conventional problems, and
Even if the potential of the epitaxial layer 1 decreases, the parasitic PNP
The object of the present invention is to provide a semiconductor integrated circuit that is completely unaffected by transistors and parasitic NPN transistors.

Means for Solving the Problems In order to solve the above problems, the semiconductor integrated circuit of the present invention has a P-type semiconductor integrated circuit in which a P-type epitaxial layer is separated from an N-type epitaxial layer formed on a P-type semiconductor substrate. It includes a resistor and a crossover wiring body in which an N-type second diffusion region is provided in a P-type first diffusion region, and sometimes a P-type second diffusion region is provided between the resistor and the crossover wiring body. 3 diffusion regions are provided, and the P-type third diffusion region and the P-type first diffusion region of the crossover wiring body are connected to the semiconductor substrate.

Effect: With this configuration, the potential of the N-type epitaxial layer becomes P
Even if the parasitic PNP transistor operates and current flows, the current flows to the semiconductor substrate, so no current is supplied to the base of the parasitic NPN transistor, and no current flows to the crossover wiring body. can be prevented from flowing.

Embodiments As described above, the embodiments of the semiconductor integrated circuit of the present invention are shown in the plan view shown in FIG. 1, the cross-sectional view taken along the line A-A' in FIG. This will be explained with reference to equivalent circuit diagrams of these structures.

In this semiconductor integrated circuit, an epitaxial layer 1 formed on a P-type semiconductor substrate 8 is separated by a separation region 9 to form an island region, and a P-type resistor 2 is provided in this island region.
A crossover wiring body 5 composed of a P-type diffusion region 51 rolled to a P-type isolation region 9 and an N-type diffusion region 52 formed within this diffusion region, and a P-type resistor 2. A P-type diffusion region 7 rolled to a P-type separation region 9 is formed between the crossover wiring body 5 and a wiring layer 3 on the resistor 2 and a wiring layer 6 on the crossover wiring body 5. This is a connected configuration. Note that 4 is an external connection terminal. Furthermore, the wiring layer that crosses over the crossover wiring body 5 is omitted to make the drawing easier to understand.

A part of the P-type diffusion region 7 is rolled to the P-type isolation region 9 to connect it to the P-type semiconductor substrate 8 . When the potential of the N-type epitaxial layer 1 falls below the potential of the P-type resistor 2, a first By causing the current flowing from the P-type resistor 2 to the N-type epitaxial layer 1 to flow into the semiconductor substrate 8 through the P-type diffusion region 7 by the parasitic PNP transistor 10, the current supply to other elements is stopped. Similar to the P-type diffusion region 7, the P-type diffusion region 51 formed in the N-type epitaxial layer 1 is also connected to the semiconductor substrate 8 by rolling a portion thereof into the isolation region 9. Here, P-type diffusion region 7
, the N-type epitaxial layer 1 and the P-type diffusion region 51 form a second parasitic PNP transistor 12, and the N-type epitaxial layer 1, the P-type diffusion region 51, and the N-type diffusion formed therein form a second parasitic PNP transistor 12. A parasitic NPN transistor 11 is constituted by the cross-over wiring body 5 constituted by the region 52. However, although most of the current flows to the semiconductor substrate 8 through the P-type diffusion region 7 due to the effect of the first parasitic PNP transistor 10, even if some of the current flows to the second parasitic PNP transistor 12, the P-type Since current flows to the semiconductor substrate 8 through the diffusion region 51, no current flows to the parasitic NPN transistor, and the potential of the wiring layer 6 connected to the crossover wiring body 5 is N-type, whereas the potential of the epitaxial layer 1 is P-type. Even if the potential is lower than that of the resistor 2, it is not affected by the parasitic PNP transistor or parasitic NPN transistor at all.

In the embodiment, a structure in which the P-type diffusion region 7 is provided has been described, but the P-type diffusion region 7 may be omitted as long as the P-type diffusion region 51 is connected to the semiconductor substrate 8. In this case, even if the potential of the N-type epitaxial layer 1 is lower than that of the resistor 2 and a current flows from the resistor 2 to the P-type diffusion region 51 due to the parasitic PNP transistor 10, the current flows to the semiconductor substrate 8. No current flows through the parasitic NPN transistor 11, and a similar effect is achieved.

Furthermore, in the embodiment, the case where the potential of the N-type epitaxial layer 1 is lower than that of the P-type resistor 2 has been explained.
A similar effect can be obtained when the potential of the N-type resistor 2 is higher than that of the N-type epitaxial layer 1.

In addition, in the embodiment, a P-type resistor 2 and a P-type diffusion region 51
In order to connect the semiconductor substrate 8 to the semiconductor substrate 8, each was rolled to the isolation region 9, but a contact window may be formed and the wiring layer connected to the ground wiring layer.

Effects of the Invention As described above, according to the semiconductor integrated circuit of the present invention, the potential of the N-type epitaxial layer 1 is reduced by the effects of the P-type resistor connected to the semiconductor substrate and the P-type diffusion region of the crossover wiring body. Even if the voltage drops below the potential of the resistor near the crossover wiring body, parasitic PNP transistors and parasitic NPN
It is possible to configure a semiconductor integrated circuit that is not affected by transistors, eliminate malfunctions, and improve reliability.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a sectional view taken along line A-A' in FIG. 1, and FIG. 3 is an equivalent circuit diagram of FIG. 1. FIG. 4 is a plan view of a conventional semiconductor integrated circuit, FIG. 5 is a sectional view taken along line BB' in FIG. 4, and FIG. 6 is an equivalent circuit diagram of FIG. 4. 1... N-type epitaxial layer, 2...
・P-type resistor, 3, 6... wiring layer, 4...
... External connection terminal, 5 ... Crossover wiring body, 51 ... P-type diffusion region, 52 ...
・N-type diffusion region, 7...P-type diffusion region, 8
... Semiconductor substrate, 9 ... Separation region, 1
0...First parasitic PNP transistor, 11
...parasitic NPN transistor, 12...
- Second parasitic PNP transistor. Name of agent: Patent attorney Toshio Nakao and one other person
School! ? law

Claims (2)

[Claims] (1) A resistor of one conductivity type, a first diffusion region of one conductivity type, and a first diffusion region of one conductivity type are placed in an island region separated from an epitaxial layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type. and a second diffusion region of an opposite conductivity type formed in the first diffusion region, and the first diffusion region
A semiconductor integrated circuit characterized in that a diffusion region of is connected to the semiconductor substrate. (2) A resistor of one conductivity type, a first diffusion region of one conductivity type, and a first diffusion region of one conductivity type are placed in an island region separated from an epitaxial layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type. a cross-over wiring body constituted by a second diffusion region of an opposite conductivity type formed in the first diffusion region; and a third diffusion region of one conductivity type formed between the resistor and the crossover wiring body. What is claimed is: 1. A semiconductor integrated circuit comprising: a diffusion region; and the first diffusion region and the third diffusion region are connected to the semiconductor substrate.