JPH01202853A - Molding type package for high frequency - Google Patents
Molding type package for high frequencyInfo
- Publication number
- JPH01202853A JPH01202853A JP63026905A JP2690588A JPH01202853A JP H01202853 A JPH01202853 A JP H01202853A JP 63026905 A JP63026905 A JP 63026905A JP 2690588 A JP2690588 A JP 2690588A JP H01202853 A JPH01202853 A JP H01202853A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- exposed
- leads
- characteristic impedance
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、信号用リードの両側に接地用リードを備えた
リードフレームと、前記信号用リードと接地用リードそ
れぞれの先端部（露出リード部）を除く前記リードフレ
ームの部分（非露出リード部）をパッケージングする樹
脂モールド部とを有する高周波用モールド型パッケージ
に関する。Detailed Description of the Invention (Field of Industrial Application) The present invention provides a lead frame having grounding leads on both sides of a signal lead, and a tip portion (exposed lead portion) of each of the signal lead and the grounding lead. The present invention relates to a high-frequency molded package having a resin mold part for packaging the portion of the lead frame (non-exposed lead part) except for ).
（従来の技術）
第２図は従来例の高周波用モールド型パッケージの平面
から見た断面図である。第２図において、符号２は複数
の信号用リード４とその信号用り−ド４の両側に配置さ
れた複数の接地用リード６とを備えたリードフレームで
ある。８は半導体チップであり、この半導体チップ８は
樹脂モールド部１０で樹脂モールドされている。また、
リードフレーム２の信号用リード４それぞれの各先端部
（露出リード部４ａ）を除く部分（非露出リード部４ｂ
）と接地用リード６の各先端部（Ｎ出す−ド部６ａ）を
除く部分（非露出リード部６ｂ）とはそれぞれ樹脂モー
ルド部１０でそれぞれ樹脂モールドされている。なお、
信号用リード４と接地用リード６それぞれの非露出リー
ド部４ｂ 、６ｂは、ワイヤ１２でそれぞれ半導体チッ
プ８の所要箇所上記の構成を有する従来例の高周波用モ
ールド型パッケージにあっては、信号用リード４とそれ
に対向している接地用リード６それぞれの幅と相互間隔
とがその露出リード部４ａ 、６ａにおいても、非露出
リード部４ｂ、６ｂにおいても一様に等しく構成されて
いることから、マイクロ波帯等の高周波信号が信号用リ
ード４に与えられると、両リード４．６が分布定数線路
として作用するために、次に述べるような問題点が指摘
されていた。(Prior Art) FIG. 2 is a cross-sectional view of a conventional high frequency molded package as seen from a plane. In FIG. 2, reference numeral 2 denotes a lead frame having a plurality of signal leads 4 and a plurality of grounding leads 6 arranged on both sides of the signal leads 4. Reference numeral 8 denotes a semiconductor chip, and this semiconductor chip 8 is resin-molded in a resin molding section 10 . Also,
The portions (non-exposed lead portions 4b) of each signal lead 4 of the lead frame 2 excluding the tip portions (exposed lead portions 4a)
) and the portions (non-exposed lead portions 6b) of the grounding lead 6 other than the tip portions (the N-output portions 6a) are molded with resin in resin mold portions 10, respectively. In addition,
The non-exposed lead portions 4b and 6b of the signal lead 4 and the ground lead 6 are wires 12, respectively, at the required locations on the semiconductor chip 8. Since the width and mutual spacing of the lead 4 and the grounding lead 6 facing it are uniformly equal in both the exposed lead portions 4a and 6a and the non-exposed lead portions 4b and 6b, When a high frequency signal such as a microwave band signal is applied to the signal lead 4, both leads 4 and 6 act as a distributed constant line, which causes the following problems.
すなわち、信号用リード４の幅寸法をａ１信号用リード
４と接地用リード６との相互間隔をＷ１露出リード部４
ａ 、６ａの周囲の比誘電率をε「、非露出リード部４
ｂ、６ｂの周囲の比誘電率をεｒ′とそれぞれ定めた場
合、露出リード部４ａ。That is, the width dimension of the signal lead 4 is a1, the mutual distance between the signal lead 4 and the grounding lead 6 is W1, and the exposed lead portion 4 is
a, the relative dielectric constant around 6a is ε'', non-exposed lead part 4
When the relative dielectric constant around b and 6b is defined as εr', the exposed lead portion 4a.
６ａで構成される分布定数線路の特性インピーダンスＺ
ｏは幅ａ、相互間隔Ｗおよび比誘電率εｒの関数となり
、また、非露出リード部４ｂ 、６ｂで構成される分布
定数線路の特性インピーダンスＺｏ’ も幅ａ１相互間
隔Ｗ１比誘電率εｒ′の関数となる。Characteristic impedance Z of the distributed constant line composed of 6a
o is a function of the width a, the mutual distance W, and the relative dielectric constant εr, and the characteristic impedance Zo' of the distributed constant line composed of the non-exposed lead parts 4b and 6b is also a function of the width a1, the mutual distance W1, and the relative permittivity εr'. Becomes a function.
しかるに、露出リード部４ａ 、６ａの周囲が空気であ
るのに対して露出リード部４ａ 、６ａの周囲が樹脂モ
ールド部ｌＯであるために、それぞれの比誘電率εｒと
εｒ′とが異なることになる結果、上記の両特性インピ
ーダンスＺｏ 、Ｚｏ ’が一致しないことになる。However, since the exposed lead parts 4a and 6a are surrounded by air, and the exposed lead parts 4a and 6a are surrounded by a resin molded part lO, their relative dielectric constants εr and εr' are different. As a result, the characteristic impedances Zo and Zo' do not match.
ところが、露出リード部４ａ 、６ａと非露出リード部
４ｂ 、６ｂとの境界部分でこのような特性インピーダ
ンスＺｏ 、Ｚｏ ’の不一致があると、その境界部分
で高周波信号の反射が起こるため、半導体チップ８に対
する所望の動作特性を得ることができなくなるという問
題があった。However, if there is a mismatch in the characteristic impedances Zo and Zo' at the boundary between the exposed lead portions 4a and 6a and the non-exposed lead portions 4b and 6b, reflection of high-frequency signals will occur at the boundary, resulting in damage to the semiconductor chip. There was a problem in that the desired operating characteristics for No. 8 could not be obtained.
本発明は、上記問題点に鑑みてなされたものであって、
露出リード部間で構成された分布定数線路の特性インピ
ーダンスと非露出リード部間で構成された分布定数線路
の特性インピーダンスとを一致させることで両リード部
の境界部分での高周波信号の不要な反射が起こらないよ
うにして半導体チップに対する所望の動作特性が得られ
るようにすることを目的としている。The present invention has been made in view of the above problems, and includes:
By matching the characteristic impedance of the distributed constant line formed between the exposed lead parts and the characteristic impedance of the distributed constant line formed between the non-exposed lead parts, unnecessary reflection of high frequency signals at the boundary between both lead parts is avoided. The purpose is to prevent this from occurring and to obtain desired operating characteristics for the semiconductor chip.
門
（？を解決するための手段）
このような目的を達成するために、本発明は信号用リー
ドの両側に接地用リードを備えたリードフレームと、前
記信号用リードと接地用リードそれぞれの先端部（露出
リード部）を除く前記リードフレームの部分（非露出リ
ード部）をパッケージングする樹脂モールド部とを有す
る高周波用モールド型パッケージにおいて、
前記信号用リードと接地用リードそれぞれの露出リード
部で構成される分布定数線路の特性インピーダンスと、
前記信号用リードと接地用リードそれぞれの非露出リー
ド部で構成される分布定数線路の特性インピーダンスと
が一致するように、前記信号用リードの幅と、その信号
用リードと接地用リードとの相互間隔との少なくとも一
方が設定されていることを特徴としている。(Means for solving the problem) In order to achieve such an object, the present invention provides a lead frame having grounding leads on both sides of a signal lead, and a lead frame having grounding leads on both sides of the signal lead and the ends of the signal lead and the grounding lead. In the high frequency molded package, the high frequency molded package has a resin molded part that packages a part (non-exposed lead part) of the lead frame except for the exposed lead part (exposed lead part), and the exposed lead part of each of the signal lead and the ground lead The characteristic impedance of the distributed constant line configured,
The width of the signal lead and the width of the signal lead and the ground lead are adjusted so that the characteristic impedance of the distributed constant line made up of the non-exposed lead portions of the signal lead and the ground lead match. The feature is that at least one of the interval and the interval is set.
（作用）
この構成によれば、信号用リードと接地用リードそれぞ
れの露出リード部周囲を囲む媒体の比誘電率と、非露出
リード部周囲を囲む媒体の比誘電率とが同じでなくても
、信号用リードの幅と、その信号用リードと接地用リー
ドとの相互間隔との少なくとも一方が両露出リード部で
構成される分布定数線路の特性インピーダンスと、両非
露出リード部で構成される分布定数線路の特性インピー
ダンスとが一致するように設定されていることから、露
出リード部と非露出リード部との境界部分での高周波信
号の不要な反射が起こらなくなり、その結果、樹脂モー
ルド部内にパブケージングされている半導体チップは、
その高周波信号に対して所望の高周波特性を得ることが
できる。(Function) According to this configuration, even if the relative dielectric constant of the medium surrounding the exposed lead portion of each of the signal lead and the grounding lead is not the same as the relative permittivity of the medium surrounding the non-exposed lead portion, , at least one of the width of the signal lead and the mutual spacing between the signal lead and the grounding lead is the characteristic impedance of the distributed constant line, which is composed of both exposed lead parts, and both non-exposed lead parts. Since the characteristic impedance of the distributed constant line is set to match the characteristic impedance of the distributed constant line, unnecessary reflection of high-frequency signals at the boundary between exposed and non-exposed leads is prevented, and as a result, the Semiconductor chips that are pubcaged are
Desired high frequency characteristics can be obtained for the high frequency signal.
（実施例）
以下、本発明の実施例を図面を参照して詳細に説明する
。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.
第１図は本発明の実施例に係る高周波用モールド型パッ
ケージの平面から見た断面図である。第１図において、
従来例に係る第２図に示した符号と同一の符号は、その
符号が示す部品、部分等と同様のものを示す。すなわち
、第１図において、符号２は信号用リード４（露出リー
ド部４ａと非露出リード部４ｂとからなる。）と接地用
リード６（露出リード部６ａと非露出リード部６ｂとか
らなる。）とを有するリードフレーム、８は半導体チッ
プ、ｌＯは樹脂モールド部、１２はワイヤである。上記
の構成は従来例と同様であるからその説明は省略する。FIG. 1 is a cross-sectional view of a high-frequency molded package according to an embodiment of the present invention, viewed from a plane. In Figure 1,
The same reference numerals as those shown in FIG. 2 relating to the conventional example indicate the same parts, portions, etc. indicated by the reference numerals. That is, in FIG. 1, reference numeral 2 includes a signal lead 4 (consisting of an exposed lead part 4a and a non-exposed lead part 4b) and a grounding lead 6 (consisting of an exposed lead part 6a and a non-exposed lead part 6b). ), 8 is a semiconductor chip, IO is a resin molded part, and 12 is a wire. Since the above configuration is the same as that of the conventional example, its explanation will be omitted.
本実施例は次の構成に特徴を有している。すなわち、信
号用リード４の露出リード部４ａの幅をａｌ、同じく信
号用リード４の非露出リード部４ｂの幅をａ２とし、信
号用リード４の露出リード部６ａと接扁用リード６の露
出リード部６ａとの相互間隔をＷｌ、信号用リード４の
非露出リード部４ｂと接地用リード６の非露出リード部
６ｂとの相互間隔をＷ２とする。そして、両露出リード
部４ａ 、６ａで構成される分布定数線路の特性インピ
ーダンス（露出側特性インピーダンス）を１０１両非露
出リード部４ｂ 、６ｂで構成される分布定数線路の特
性インピーダンス（非露出側特性インピーダンス）をＺ
ｏ’ とすると、露出側特性インピーダンスＺＯはａｌ
とＷｌとその周囲の媒体（この例では空気）の比誘電率
εｒとの関数、つまりＺｏ ＝Ｚｏ （ａ １．Ｗｌ、
εｒ ）となり、非露出側特性インピーダンスＺｏ’は
ａ２とＷ２とその周囲の媒体（この例では樹脂モールド
部１０）の比誘電率εｒ′との関数、つまりＺｏ’＝Ｚ
ｔ＋’（ａ２．Ｗ２．εｒ′）となる。そして、本実施
例では、露出側特性インピーダンスＺｏと非露出側特性
インピーダンスＺｏ’とが等しくなるように、信号用リ
ード４の露出リード部４ａの幅ａｌと、非露出リード部
４ｂの幅ａ２と、露出側と非露出側とにおける両リード
部４，６の相互間隔Ｗ１、Ｗ２とを、設定している。This embodiment is characterized by the following configuration. That is, the width of the exposed lead part 4a of the signal lead 4 is set to al, the width of the non-exposed lead part 4b of the signal lead 4 is set to a2, and the exposed lead part 6a of the signal lead 4 and the contact lead 6 are exposed. Let Wl be the distance between the lead portion 6a and W2, and W2 be the distance between the non-exposed lead portion 4b of the signal lead 4 and the non-exposed lead portion 6b of the ground lead 6. Then, the characteristic impedance (exposed side characteristic impedance) of the distributed constant line composed of both exposed lead parts 4a and 6a is 101. The characteristic impedance of the distributed constant line composed of both unexposed lead parts 4b and 6b (unexposed side characteristic impedance) to Z
o', the exposed side characteristic impedance ZO is al
is a function of Wl and the relative dielectric constant εr of the surrounding medium (air in this example), that is, Zo = Zo (a 1.Wl,
εr), and the non-exposed side characteristic impedance Zo' is a function of a2, W2, and the relative dielectric constant εr' of the surrounding medium (resin molded part 10 in this example), that is, Zo'=Z
t+'(a2.W2.εr'). In this embodiment, the width al of the exposed lead portion 4a of the signal lead 4 and the width a2 of the non-exposed lead portion 4b are adjusted so that the exposed side characteristic impedance Zo and the unexposed side characteristic impedance Zo' are equal. , the mutual spacings W1 and W2 between both lead portions 4 and 6 on the exposed side and the non-exposed side are set.
したがって、本実施例によれば、露出リード部４ａ 、
６ａと非露出リード部４ｂ 、６ｂそれぞれの周囲の媒
体の比誘電率が異なっていても、上記両特性インピーダ
ンスＺｏ 、Ｚｏ ’が一致するように上記の幅の寸法
と相互間隔とが設定されているから信号用リード４に高
周波信号が与えられた場合は、両リード４．６の前記境
界部分での不要な高周波信号の反射がなくなり、その結
果、半導体チップ８は所望の高周波特性でもって動作す
ることができる。Therefore, according to this embodiment, the exposed lead portions 4a,
Even if the relative dielectric constants of the media surrounding the lead portions 6a and the non-exposed lead portions 4b and 6b are different, the width dimension and the mutual spacing are set so that the characteristic impedances Zo and Zo' match. Therefore, when a high frequency signal is applied to the signal lead 4, there is no unnecessary reflection of the high frequency signal at the boundary between the leads 4 and 6, and as a result, the semiconductor chip 8 operates with the desired high frequency characteristics. can do.
なお、本実施例では、信号用リード４の幅の寸法と両リ
ード４．６の相互間隔の両方の設定で両特性インピーダ
ンスＺｏ 、Ｚｏ ’を一致させたが、信号用リード４
の幅寸法または両リード部４．６の相互間隔のいずれか
一方のみの設定で、上記の一致を行わせるようにしても
よい。In this embodiment, both characteristic impedances Zo and Zo' were made to match by setting both the width dimension of the signal lead 4 and the mutual spacing between both leads 4.6, but the signal lead 4.
The above matching may be achieved by setting only one of the width dimension of the lead portions 4.6 or the mutual spacing between the two lead portions 4.6.
（効果）
以上説明したことから明らかなように本発明によれば、
信号用リードの幅の寸法または信号用リードと接地用リ
ードとの相互間隔の少なくとも一方の設定でもって露出
リード部間で構成された分布定数線路の特性インピーダ
ンスと非露出リード部間で構成された分布定数線路の特
性インピーダンスとを一致させるように構成したから、
露出リード部周囲の媒体の比誘電率と非露出リード部周
囲の媒体のそれとが一致していなくとも両リード部の境
界部分での高周波信号の不要な反射が起こらなくなり、
その結果、半導体チップを所望の高周波動作特性で駆動
させることができる。(Effects) As is clear from the above explanation, according to the present invention,
The characteristic impedance of the distributed constant line configured between the exposed lead portions is determined by setting at least one of the width dimension of the signal lead or the mutual spacing between the signal lead and the grounding lead, and the characteristic impedance of the distributed constant line configured between the non-exposed lead portions. Since it is configured to match the characteristic impedance of the distributed constant line,
Even if the dielectric constant of the medium surrounding the exposed lead portion does not match that of the medium surrounding the non-exposed lead portion, unnecessary reflection of high-frequency signals at the boundary between both lead portions will not occur.
As a result, the semiconductor chip can be driven with desired high frequency operating characteristics.
第１図は本発明の一実施例に係る高周波用モールド型パ
ッケージの平面から見た断面図、第２図は第１図に対応
する従来例の断面図である。
２・・・リードフレーム、４・・・信号用リード、６・
・・接地用リード、８・・・半導体チップ、１０・・・
樹脂モールド部、！２・・・ワイヤ、４ａ 、６ａ・・
・露出リード部、４ｂ 、６ｂ・・・非露出リード部。
なお、図中同一符号は同一ないしは相当部分を示してい
る。FIG. 1 is a cross-sectional view of a high-frequency molded package according to an embodiment of the present invention, viewed from the top, and FIG. 2 is a cross-sectional view of a conventional example corresponding to FIG. 1. 2... Lead frame, 4... Signal lead, 6...
...Grounding lead, 8...Semiconductor chip, 10...
Resin mold part! 2...Wire, 4a, 6a...
- Exposed lead part, 4b, 6b... non-exposed lead part. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
ドフレームと、前記信号用リードと接地用リードそれぞ
れの先端部（露出リード部）を除く前記リードフレーム
の部分（非露出リード部）をパッケージングする樹脂モ
ールド部とを有する高周波用モールド型パッケージにお
いて、 前記信号用リードと接地用リードそれぞれの露出リード
部で構成される分布定数線路の特性インピーダンスと、
前記信号用リードと接地用リードそれぞれの非露出リー
ド部で構成される分布定数線路の特性インピーダンスと
が一致するように、前記信号用リードの幅、およびその
信号用リードと前記接地用リードとの相互間隔の少なく
とも一方が設定されていることを特徴とする高周波用モ
ールド型パッケージ。(1) A lead frame with grounding leads on both sides of the signal lead, and a portion of the lead frame (non-exposed lead portion) excluding the tips (exposed lead portions) of each of the signal lead and the grounding lead. In a high frequency molded package having a resin molded part for packaging, the characteristic impedance of a distributed constant line composed of exposed lead parts of the signal lead and the grounding lead,
The width of the signal lead and the width of the signal lead and the ground lead are adjusted so that the characteristic impedance of the distributed constant line composed of the non-exposed lead portions of the signal lead and the ground lead match each other. A high frequency molded package characterized in that at least one of the mutual intervals is set.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026905A JP2580674B2 (en) | 1988-02-08 | 1988-02-08 | High frequency mold package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63026905A JP2580674B2 (en) | 1988-02-08 | 1988-02-08 | High frequency mold package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01202853A true JPH01202853A (en) | 1989-08-15 |
| JP2580674B2 JP2580674B2 (en) | 1997-02-12 |
Family
ID=12206242
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63026905A Expired - Lifetime JP2580674B2 (en) | 1988-02-08 | 1988-02-08 | High frequency mold package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2580674B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5218230A (en) * | 1990-09-28 | 1993-06-08 | Fujitsu Limited | Ic package with electric conductor lines in dielectric package body |
| US6781223B2 (en) | 2001-11-30 | 2004-08-24 | Fujitsu Limited | Semiconductor device having a signal lead exposed on the undersurface of a sealing resin with an air gap between the signal lead and a mounting substrate |
| US7763966B2 (en) | 2007-03-06 | 2010-07-27 | Renesas Technology Corp. | Resin molded semiconductor device and differential amplifier circuit |
| US8829685B2 (en) * | 2009-03-31 | 2014-09-09 | Semiconductor Components Industries, Llc | Circuit device having funnel shaped lead and method for manufacturing the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61239650A (en) * | 1985-04-13 | 1986-10-24 | Fujitsu Ltd | High speed integrated circuit package |
-
1988
- 1988-02-08 JP JP63026905A patent/JP2580674B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61239650A (en) * | 1985-04-13 | 1986-10-24 | Fujitsu Ltd | High speed integrated circuit package |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5218230A (en) * | 1990-09-28 | 1993-06-08 | Fujitsu Limited | Ic package with electric conductor lines in dielectric package body |
| US6781223B2 (en) | 2001-11-30 | 2004-08-24 | Fujitsu Limited | Semiconductor device having a signal lead exposed on the undersurface of a sealing resin with an air gap between the signal lead and a mounting substrate |
| US7763966B2 (en) | 2007-03-06 | 2010-07-27 | Renesas Technology Corp. | Resin molded semiconductor device and differential amplifier circuit |
| US8829685B2 (en) * | 2009-03-31 | 2014-09-09 | Semiconductor Components Industries, Llc | Circuit device having funnel shaped lead and method for manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2580674B2 (en) | 1997-02-12 |
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