JPH01200665A - Manufacture of amorphous silicon thin-film transistor array substrate - Google Patents

Abstract

PURPOSE:To prevent the surface of a glass substrate of a connection terminal part from being roughened or a film of a gate wiring part from being stripped off by a method wherein, when a protective insulating layer is to be patterned, the connection terminal of the gate wiring part and a region exposed at the glass substrate are coated with a photoresist. CONSTITUTION:Silicon nitride or silicon oxide to be used as a gate insulating layer 3 and silicon nitride or silicon oxide to be used as an i-a-Si layer 4 and a protective insulating layer 5 are deposited on a glass substrate 1 where a gate electrode and a gate wiring part have been formed, by a plasma CVD method by using a metal mask and by making use of a connection terminal part of the gate wiring part 2 as a mask; in succession, a photoresist 7 as an etching mask of the protective insulating layer 5 to be used to expose the i-a-Si layer of a source-drain part of a TFT is formed in a pattern of a prescribed shape. Then, the protective insulating layer is etched by using a buffer solution of hydrofluoric acid by making use of the photoresist pattern as the mask. During this operation, because the glass surface of a connection terminal part of the gate wiring part is covered with the photoresist 7, the surface is not corroded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention is applied to amorphous silicon (amorphous-8Tl) used in active matrix type liquid crystal displays, etc.
1eo11. Hereinafter a-8i) Thin film transistor (T
bln Fil+++Transistor, hereinafter TF
T) Regarding a method for manufacturing an array substrate.

[Prior art] In recent years, liquid crystal matrix displays,
In particular, so-called active matrix type liquid crystal displays in which a switching element is provided for each pixel are being researched and developed in various places. As a switching element, an old S-type TI'T using a-9I is mainly used.

FIG. 2 schematically shows a configuration example of an active matrix type liquid crystal display using TPT. When, for example, XI is selected along the length of the scanning line 11, the gates of the TPTs 13-a connected to it are turned on all at once, and signals corresponding to image information are transmitted from each signal line 12 through the sources of these turned-on TPTs. A voltage is transmitted to the drain of each TPT 13-a.

A pixel electrode (not shown) is connected to the drain, and the light transmittance of the liquid crystal layer 14 is controlled by the voltage difference between this pixel electrode and a counter electrode 15 formed on the other two plates with the liquid crystal layer 14 in between. Display the image by changing it. When Xi becomes unselected, the gates of the TFTs 13-a connected to it are turned off, Xi+1 is subsequently selected, and each TFT 13-a connected to it is turned off.
The gate of FT 13-b is turned on and the same operation as above is performed. Note that even after the gate is turned off, the voltage difference between the pixel electrode and the counter electrode 15 is preserved by the liquid crystal layer 14 until the same scanning line is selected, so the liquid crystal corresponding to each pixel is statically driven. As a result, a high contrast display can be obtained.

By the way, the a-8t TPT used in TPT H is manufactured by sequentially depositing a gate insulating layer, an a-8i layer, and a protective insulating layer. This is a desirable manufacturing method.

FIG. 3 schematically shows an example of the manufacturing process of an a-3i TFT used in an active matrix type liquid crystal display having the above manufacturing method, and the process will be explained.

(a) A metal layer such as Or is selectively deposited on a glass substrate 21, a gate electrode 22 and a gate wiring (not shown) are formed, and then a gate insulating layer 23 of silicon nitride or silicon oxide is formed. Intrinsic A-3 contains almost no impurities and becomes the active layer.
A layer 24 and a protective insulating layer 25 made of silicon nitride or silicon oxide are deposited by, for example, plasma CVD.

(b) The protective insulating layer 25 is selectively etched with a buffered hydrofluoric acid solution so that it partially overlaps the gate electrode 22.
1-a-8i layer 24 is exposed.

(C) An n-type a-8I (hereinafter referred to as na-9i) layer 26 containing an appropriate amount of phosphorus as an impurity, and a metal layer 27 such as TI
The metal layer 27 is selectively etched and patterned into the shape of the source and drain electrodes. Using the patterns of the metal layer 27 and the protective insulating layer 25 as a mask, the na-81 layers 2G and I -a-9i layer 2
4 is etched using an alkaline solution to form an island-like structure.

(d) A transparent conductive layer 28 such as ITO is deposited and selectively removed to form source lines and pixel electrodes.

By the process described above, a-9t as shown in Fig. 3 is obtained.
TPT is completed.

Incidentally, although the above explanation has mainly concerned the manufacturing process of the TPT main body, the manufacturing process was carried out in the peripheral area of the substrate, particularly at the end of the gate wiring, with the following points in mind. Since the gate wiring needs to be connected to the external circuit via the gate wiring connection terminal, it must ultimately be exposed, but in order to simplify the process, for example, As shown in FIG. 4, each layer was deposited by placing a metal mask 32 on a glass substrate 31 to prevent each layer from being deposited on the connection terminal portion of the gate wiring.

[Problem to be solved by the invention] By the way, when each layer is deposited using a metal mask,
Each layer is not deposited not only on the connection terminal of the gate wiring but also on the surrounding glass substrate. Therefore, the aforementioned 'f' F T
In the manufacturing process, when the protective insulating layer made of silicon nitride or acidic silicon is etched using a buffered hydrofluoric acid solution, the surface of the glass substrate is also etched at the same time.

FIG. 5 schematically shows the state of the connection terminal portion of the gate wiring at this time. 21 is a glass substrate, 22 is a gate wiring, 23 is a gate insulating layer, 24 is 1-a-S
This is the t layer. In the conventional method, since the surface of the glass substrate is etched, there are problems such as roughness 29 of the glass surface or undercut 30 at the end of the gate wiring.

In particular, the undercut 30 causes peeling of the end portion of the gate wiring, contributing to a decrease in manufacturing yield.

The present invention has been made in view of the above-mentioned drawbacks of the conventional art, and aims to eliminate roughness on the glass surface or undercuts at the connecting terminal portions of gate wiring.

[Means for Solving the Problem] According to the present invention, a gate insulating layer is formed on a glass substrate on which a gate electrode and gate wiring having a predetermined shape are provided.
The method includes a step of sequentially depositing an amorphous silicon layer and a protective insulating layer so as not to cover the connecting terminal portion of the gate wiring, and a step of patterning the protective insulating layer into a predetermined shape, and after the steps In a method for manufacturing an amorphous silicon thin film transistor array substrate manufactured through a predetermined manufacturing process to include at least an amorphous silicon thin film transistor array, a gate wiring, and a source wiring, when patterning the protective insulating layer, the gate The above object is achieved by manufacturing an amorphous silicon thin film transistor array substrate characterized in that the wiring connection terminals and exposed areas of the glass substrate are covered with photoresist.

The photoresist is preferably coated in the same process as the photoresist used to expose the amorphous silicon layer of the source and drain portions.

[Example] Hereinafter, an example of the present invention will be described using FIG. 1. This is a diagram schematically showing a cross section of a connection terminal portion of a gate wiring. 1 is the glass substrate, 2 is the gate wiring,
3 is silicon nitride or silicon oxide which becomes a gate insulating layer, 4 is a 1-a-3i layer, 5 is silicon nitride or silicon oxide which is a protective insulating layer, 6 is a connection terminal, and 7 is a photoresist. Note that the structure or manufacturing method of the TPT main body is unchanged from the conventional one, so the parts related to the manufacturing process of the TPT main body in the following explanation will be explained in Part 3.
Preferably, reference is made to the figures.

(a) Silicon nitride or silicon oxide that will become the gate insulating layer 3, 1-a-St layer 4, and nitride that will become the protective insulating layer 5 on the glass substrate 1 on which the gate electrode (not shown) and gate wiring 2 are installed. silicon or silicon oxide,
The connection terminal portion of the gate wiring 2 is masked using a metal mask, and the protective insulating layer 5 is deposited by, for example, plasma CVD, and then the protective insulating layer 5 is deposited to expose the 1-a-81 layer of the source and drain portions of the TPT. A photoresist is patterned into a predetermined shape as an etching mask. At this time, the connection terminal portion of the gate wiring 2 is also covered with the photoresist 7 at the same time. Note that the photoresist pattern for the TPT portion and the photoresist pattern for the connection terminal portion of the gate wiring 2 are preferably formed using the same photomask.

(b) Using the photoresist pattern as a mask, the protective insulating layer is etched using a buffered hydrofluoric acid solution. At this time, since the glass surface of the connection terminal portion of the gate wiring 2 is covered with the photoresist 7, it is not attacked by the buffered hydrofluoric acid solution. After etching is completed, the photoresist is peeled off.

(c) n-a-31 layer (not shown); metal layer (not shown);

) was sequentially deposited, the metal layer was patterned into the shape of source and drain electrodes, and using this as a mask, na-81
The layer 1-a-8i layer 4 is etched using an organic alkaline solution. Finally, a transparent conductive layer such as ITO is deposited and selectively removed to form source wiring and pixel electrodes.

By going through the above steps, a connecting terminal portion of the gate wiring 2 without roughness due to etching on the surface of the glass substrate as shown in FIG. 1(C) can be obtained.

[Effects of the Invention] As described above, according to the present invention, when the protective insulating layer is etched with a buffered hydrofluoric acid solution, since the connection terminal portion of the gate wiring is covered with the photoresist, the connection terminal The surface of the glass substrate is not attacked in any way, so there is no roughness on the surface of the glass substrate or peeling of the gate wiring film due to undercuts at the ends of the gate wiring, which contributes to improved manufacturing yields. .

In particular, by coating the photoresist in the same process as the photoresist used to expose the amorphous silicon layer in the source and drain regions, it is only necessary to change the pattern of the photomask, reducing the number of manufacturing steps. nothing to bring about.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the manufacturing process of an embodiment of the present invention;
Figure 2 is an electric circuit diagram showing the principle of an active matrix liquid crystal display, Figure 3 is a cross-sectional view showing an example of the manufacturing process of an amorphous silicon thin film transistor, and Figure 4 is a diagram showing the structure of a glass substrate and metal mask. FIG. 5 is a perspective view showing the relationship, and FIG. 5 is a cross-sectional view showing a connecting terminal portion by a conventional manufacturing method. 1...Glass substrate, 2...Gate wiring, 3...
・Gate insulating layer, 4... Amorphous silicon layer 5... Protective insulating layer, 6... Connection terminal, 7... Photoresist and above Applicant Seikosha Co., Ltd.

Claims (2)

[Claims] (1) A gate insulating layer, an amorphous silicon layer, and a protective insulating layer are sequentially placed on a glass substrate on which a gate electrode and gate wiring having a predetermined shape are installed, without covering the connection terminals of the gate wiring. and patterning the protective insulating layer into a predetermined shape, and after the step, a predetermined manufacturing process is performed to form at least an amorphous silicon thin film transistor array, a gate wiring, and a source wiring. In the method for manufacturing an amorphous silicon thin film transistor array substrate, when patterning the protective insulating layer, connecting terminals of the gate wiring and exposed areas of the glass substrate are covered with photoresist. 1. A method of manufacturing an amorphous silicon thin film transistor array substrate. (2) The amorphous silicon thin film transistor array substrate according to claim 1, wherein the photoresist is coated in the same process as the photoresist used to expose the amorphous silicon layer of the source and drain portions. manufacturing method.