JPH01199398A - Non-volatile semiconductor memory - Google Patents

Abstract

PURPOSE:To read data at a high speed by providing a latch to a sense amplifier output and controlling the transfer of the data latched with a block selecting signal to an output buffer. CONSTITUTION:At the time of a page mode reading, sense amplifiers 15 of respective memory arrays are all activated, the contents of memory cells of the same X and Y addresses of respective arrays are read by the sense amplifiers 15, and they are latched by latches 17. For example, the data of 8 bits are latched. By switching block selecting signals BS thereafter, the data of 8 bits are sent to an output buffer 16 in an arbitrary order, and the data are read. Since a time when the contents of the memory cells are sensed by the sense amplifiers 15 is longer than the time when the block selecting signals BS are switched and the latched data are sent to the output buffer 16, the data can be read at a high speed by the page mode.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device, and in particular to an EP
Regarding the read mode of ROM and EEPROM.

[Conventional technology]

FIG. 2 shows a block diagram of a read system of a conventional EEPROM. FIG. 3 shows a detailed circuit diagram of the memory array. In these figures, l is a 1-bit memory cell, and bit line selection transistors 2. Control gate line selection transistor 3. It is composed of a memory transistor 4.

The focus line 5 is connected to l/Om8 via a transistor 7 whose gate receives the output of the column decoder 6.

The control gate line 9 is connected to C(J!1
Connected to 1. The gate of selection transistor 2.3 is connected to word line 12, and the source of memory transistor 4 is connected to source line 13. Word line 12 is connected to row decoder 14 . I/O line 8 is sense amplifier 15
The sense amplifier 15 is connected to the output cover 77a16.

Next, the operation will be explained. During reading, a read voltage is applied to the CG line 11, and the source line 13 is grounded. One word line 12 becomes "H" in response to the input address, and one of the output lines of the column decoder becomes "H", thereby causing the drain of the memory transistor 4 of the selected memory cell 1 to become "H". Bit line 5 and further I/O line 8
connected to. Further, its gate is connected to the control gate line 9 and further to the CG line 11, and a read voltage is applied thereto. Further, its source is grounded via source line 13.

The sense amplifier 15 selects the selected memory transistor 4
Whether "1'" or "0" is stored in the memory transistor 4 is sensed by whether or not current flows through the memory transistor 4. If "1" is written in the memory transistor 4 and electrons are injected into the floating gate, the threshold value of the memory transistor 4 becomes high and the transistor 4 is turned off. On the other hand, when /O'' is written and electrons are extracted from the floating gate, the threshold value of the memory transistor 4 becomes low and the transistor 4 is turned on.

[Problem to be solved by the invention]

Conventional nonvolatile semiconductor memory devices are configured as described above, but have the disadvantage that multiple bytes cannot be read out at high speed.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a nonvolatile semiconductor memory device that has a page mode read function and can read data at high speed.

[Means to solve the problem]

A non-volatile semiconductor memory device according to the present invention has a latch provided at the sense amplifier output, reads out each memory block simultaneously, and selects data to be transferred to an output buffer using a block selection signal.

[Effect]

In this invention, by latching the sense amplifier output with a latch and controlling the connection between the latch output and the output buffer using a block selection signal, page mode reading is possible, and multiple bytes of data can be output at high speed. can.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 17 is a latch provided at the output of the sense amplifier 15, and its output is connected to the output buffer 16 via a transistor 18 whose gate receives the block selection signal BS.

The memory array is divided into four large blocks, each of which is further divided into two. The addresses specifying the bits within each array are all the same input address signal.

Next, the operation will be explained. During page mode reading, all sense amplifiers 15 in each memory array are activated, and the contents of the memory cells at the same -X and Y addresses in each array are read out by the sense amplifiers 15 and latched into the latch 17. In the example of FIG. 1, 8-bit data is latched. Thereafter, by switching the block selection signal BS, 8-bit data can be sent to the output buffer 16 in any order and read out. Since the time it takes for the sense amplifier 15 to sense the contents of the memory cell is longer than the time it takes to switch the block selection signal BS and send the latched data to the output buffer 116, data can be read out faster in page mode.

In addition, in the above example, the memory array was divided into 8, but
This can be any number of minutes.

〔Effect of the invention〕

As described above, according to the nonvolatile semiconductor memory device according to the present invention, a latch is provided at the sense amplifier output, and the transfer of the latched data to the output buffer is controlled by the block selection signal. It is possible to read data, and there is an effect that data can be read out at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a read system of a non-volatile semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a read system of a conventional non-volatile semiconductor memory device, and FIG. 3 is a more detailed diagram. This is a circuit diagram. 5 is a bit line, 6 is a column decoder, 8 is an I/O line, 1
5 is a sense amplifier, 16 is an output buffer, 17 is a lunch, BS6 or BS? is the block selection signal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] (1) The memory array is divided into multiple blocks, and in each block, the bit line is connected to an I/O line via a transistor whose gate receives a column selection signal, and a sense amplifier is connected to the I/O line. A nonvolatile semiconductor memory device connected to each other, wherein each of the blocks includes a latch whose input is the output of each of the sense amplifiers, and whose connection between the output and the output buffer is controlled by a block selection signal. A nonvolatile semiconductor memory device characterized by: