JPH01198133A - Burst wave preamble extracting circuit - Google Patents

Abstract

PURPOSE:To draw in the timing reproduction of phase modulated waves received in the form of burst at a high speed under a low C/N condition by constituting the '0' and '1' alternate pattern extracting circuit at the leading edge section of burst waves as a narrow-band filter with the Nyquist frequency of demodulated base band signals as the center frequency. CONSTITUTION:The orthogonal and same-phase signals of the demodulated base band signals 1 of received waves become the phase difference information with the reference clock 10 of a timing reproducing system PLL 3 after the signals are supplied to a phase comparator 2 and this information is inputted as the phase controlling information of the reference clock 10 of the PLL 3. At the timing reproducing system PLL 3, operations under a low C/N condition are compensated by suppressing an inter-PLL noise band width to the utmost and high-speed drawing-in operations are coped with by means of a timing extracting circuit 4 at the outside of the PLL 3. The timing component extracting circuit 4 is constituted of, for example, a band-pass filter which uses the Nyquist frequency of the demodulated base band signals 1 as its center frequency and has a high Q.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a receiver for digital phase modulated waves that arrive in burst form, and is particularly suitable for high-speed pull-in of timing regeneration and burst wave reception detection. This invention relates to a preamble extraction circuit.

[Conventional technology]

In a conventional burst phase modulated wave receiver, as a means of extracting the timing from the demodulated pace pad signal of the received wave, "Applications of Digital Signal Processing" edited and published by the Institute of Electronics and Communication Engineers, p. 169 (1981) or I.E.
E.E., Transaction, C.O.M.-2
3, Zui 2 (1975), p. 269 (IEEE, Tra
ns, C0M-25, N112 (1975) P269.
), there is a method in which a nonlinear operation is applied to a modulation pattern signal, and then the output is further improved in C/Nft using a narrow band filter to obtain the extraction timing.

Furthermore, as a method for the purpose of high-speed phase pull-in, Japanese Patent Application Laid-open No. 60-223243 ``Timing phase synchronization device''
As described in , there is a method in which the phase difference between the nonlinear extracted output and the timing recovery reference clock is calculated and corrected during the initial training period, and then the PLL is operated.

However, if the nonlinear extraction circuit is included in the PLL, even though the initial phase settings provide timing for sampling the discriminant points, that information does not appear in the narrowband filter output until a considerable time later. Because of this problem, it is not suitable for timing recovery of burst receivers that require high-speed pull-in.

[Problem to be solved by the invention]

The above conventional technology uses a non-linear extraction method to extract a data timing component and synchronizes the extracted signal with a reference clock using a PLL to control the sampling time to configure a timing recovery circuit using digital processing. is effective, but a narrowband filter is used for the above PLL
Because it is included internally, the extraction clock phase change of the narrowband filter output is considerably small with respect to the sample value input change after sampling time control, so the PL
The loop gain of L is reduced and high-speed retractability is lost. On the other hand, since the sample value is inputted to error correction and the like as a signal indicating identification point information of the received signal, there is a problem that the error rate of the signal received during the time until the pull-in is completed increases.

Furthermore, for the purpose of adding high speed, the phase difference between the sampling timing and the received signal identification point is calculated from the output value of the extraction filter, and the initial phase correction of the sampling timing is performed at the beginning of signal reception. Since a clock component consisting of a corrected sample value is not output as a filter output, the PLL operation behaves in the same manner as a phase offset response, resulting in a problem of loss of high speed.

The object of the present invention is to solve the problems of the prior art described above,
The purpose of the present invention is to enable timing recovery of phase modulated waves received in burst form at high speed under low C/N.

[Means to solve section @]

The above problem is that in order to achieve high-speed pull-in of the timing regeneration of burst-shaped received waves, the front part of the burst wave (preamble) must be configured in the order of an unmodulated data pattern and a 0°1 alternating pattern. Detects the arrival of a 0,1 alternating pattern that includes a timing component, calculates the phase difference with the recovered clock (reference clock) from the timing component, and corrects the sampling timing. Focusing on the necessity of not giving a shadow*f, a 0,1 alternating pattern extraction circuit (timing component extraction circuit) in the burst wave Psimple is provided outside the timing reproduction system to detect the arrival of the burst wave. The phase difference between the reproduction clock and the discrimination point is calculated from the sample value extracted at the time, and correction is applied to the reproduction system PLL.The reproduction system PLL 1 is configured with a zero-cross comparison type PLL of the demodulated pace pad signal waveform, and the loop is created. This is achieved by a burst wave preamble extraction circuit that eliminates the need for a nonlinear extraction circuit inside.

[Effect]

The above burst wave preamble extraction circuit consists of a 0,1 alternating pattern extraction circuit at the beginning of the burst wave as a narrow band filter centered around the Nyquist frequency of the demodulated pace pad signal. Since the Kffi transmission during the reception time of Batai is being regenerated, and there is no carrier wave offset when receiving the 0°1 alternating pattern of the demodulated pace pad signal (the Q of the narrowband filter mentioned above can be made high, but Since the C/N'fI of the clock of the received signal extracted by Even in level discrimination using the threshold value of the extracted signal, it is possible to increase the detection probability and reduce the probability of burst wave reception false detection and false detection.Furthermore, the above narrowband filter can be placed outside the timing regeneration thread PLL system. Because of this provision, the high speed of the loop response is not lost.

〔Example〕

An embodiment of the present invention will be explained below with reference to the drawings.

The figure is a functional block diagram showing an embodiment of a burst wave preamble extraction circuit according to the present invention. In the figure, 1 is a demodulated pace pad signal, 2 is a phase comparator, 3 is a timing recovery system PLL, 4 is a timing component extraction circuit (timing extraction filter), 5 is a level judgment threshold, 6 is a level comparator, 7 8 is a level judgment output hold circuit, 8 is a phase error calculation section, 9 is a phase correction amount setting value switch, and 10 is a reference clock.

With the above configuration, the orthogonal and in-phase signals of the demodulated pace pad signal 1 of the received wave are transferred to the timing recovery system P by the phase comparator 2.
This information becomes the phase difference information with respect to the reference clock 10 of the LL 3, and this information becomes the reference clock 10 of the timing reproduction system PLL 3.
input as phase control information. This system is a timing regeneration system (circuit) that has been commonly used in the past.

In the present invention, a timing component extraction circuit 4 is provided outside the timing reproduction system PLi. In a line where received waves are transmitted in time division, the carrier wave of the received waves is regenerated in the af-toned pattern section in the preamble at the beginning of the burst wave, and then in the 0.1 alternating pattern that follows. Perform timing playback. Therefore, high-speed pull-in operation is required for timing regeneration, and furthermore, synchronization must not occur even under low C/N. In order to satisfy both of these conflicting demands, in the present invention, the timing extraction system PLL 3 suppresses the noise bandwidth within the PLL as much as possible to compensate for operation under low C/N, and the timing extraction circuit 4 outside the regeneration system PLL 3
This enables high-speed retracting operation. The timing component extraction circuit 4 is, for example, a high-Q band-pass filter whose center frequency is the Nyquist frequency of the demodulated pace pad signal 1. Now, in the 0.1 alternating pattern section at the beginning of the burst wave, the spectrum of the demodulated pace pad signal 1 appears as a single carrier at the Nyquist frequency. 4, the C/N ratio of the received signal can be increased. Furthermore, by comparing this output with the level determination threshold value 5 in the level comparator 6, the arrival of the burst wave can be detected and held in the level determination output hold circuit 7.

Therefore, when detecting the arrival of the burst wave, the phase difference signal calculated by the phase error calculation section 8 from the output of the bandpass filter 4 is sent from the phase correction amount setting value switch 9 to the timing reproduction thread P.
By providing K as the phase offset correction amount of LL3, high-speed pull-in of timing reproduction is completed.

〔Effect of the invention〕

According to the present invention, it is possible to rapidly reproduce the timing of a modulated wave received in a burst form and maintain synchronization stably under a low C/N, and furthermore, the timing extraction circuit is integrated into the system of the regenerated yarn PLL. Since it does not exist, there is an effect that the PLL K does not generate a phase offset response at the initial phase setting.

[Brief explanation of the drawing]

The figure is a functional block diagram showing an embodiment of a burst wave preamble extraction circuit according to the present invention. 1... Demodulated pace pad signal 2... Phase comparator 3... Timing regeneration system PLL 4... Timing component extraction circuit (timing extraction filter) 5... Level judgment threshold 6... Level Comparator 7...Level judgment output hold circuit 8...Phase error calculation unit 9...Phase correction amount setting value switch 10...Reference clock.

Claims (1)

[Claims] 1. A phase modulated wave arrives in a burst, and the beginning of each burst is configured in the order of a non-modulated pattern and a 0, 1 alternating pattern, and data timing is recovered from the received wave of the modulated wave. A burst wave preamble extraction circuit characterized in that, in the timing reproduction system, an extraction means for extracting the fundamental wave component of the 0, 1 alternating pattern from the demodulated pace pad signal of the received wave is provided outside the timing reproduction system. 2. Providing means for determining the amount of phase offset from the reference clock of the timing reproduction system from the output of the extraction means,
2. The burst wave preamble extraction circuit according to claim 1, wherein the timing reproduction system is corrected based on the output thereof. 3. The burst wave preamble extraction circuit according to claim 1, further comprising means for comparing the output level of said extraction means with a set threshold value, and the output thereof being used as a burst arrival detection signal.