JPH01198076A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01198076A JPH01198076A JP63023252A JP2325288A JPH01198076A JP H01198076 A JPH01198076 A JP H01198076A JP 63023252 A JP63023252 A JP 63023252A JP 2325288 A JP2325288 A JP 2325288A JP H01198076 A JPH01198076 A JP H01198076A
- Authority
- JP
- Japan
- Prior art keywords
- region
- trench
- base layer
- electrode
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 17
- 239000012535 impurity Substances 0.000 claims abstract description 14
- 238000009792 diffusion process Methods 0.000 abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229920005591 polysilicon Polymers 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 10
- 229910052710 silicon Inorganic materials 0.000 description 10
- 239000010703 silicon Substances 0.000 description 10
- 239000000758 substrate Substances 0.000 description 10
- 238000010586 diagram Methods 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001590 oxidative effect Effects 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002747 voluntary effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/01—Manufacture or treatment
- H10D12/031—Manufacture or treatment of IGBTs
- H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
- H10D12/038—Manufacture or treatment of IGBTs of vertical IGBTs having a recessed gate, e.g. trench-gate IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
- H10D12/481—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs
Landscapes
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
この発明は、例えば大電力高速スイッチング素子をモノ
リシックで実現した半導体装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device in which, for example, a high-power high-speed switching element is realized monolithically.
平面ゲート形のＭＯＳＦＥＴ（電界効果トランジスタ）
やＩ Ｇ Ｂ Ｔ （Ｉｎ５ｕｌａｔｅｄ Ｇａｔｅ
ＢｉｐｏｌａｒＴｒａｎｓｉｓｔｏｒ：絶縁ゲート形電
界効果トランジスタ）に比較して縦型ゲート構造のＭＯ
ＳＦＥＴやＩ ＧＢＴはゲートを集積化することができ
るので、より小形で大きい電流駆動能力が得られる。Planar gate MOSFET (field effect transistor)
ya I G B T (In5ulated Gate
Bipolar Transistor: MO with vertical gate structure compared to insulated gate field effect transistor
Since the gates of SFETs and IGBTs can be integrated, they can be made smaller and have larger current drive capabilities.
第３図は縦形ゲート構造の従来のＮチャンネルＩＧＢＴ
の構造を示す側断面図である。Figure 3 shows a conventional N-channel IGBT with a vertical gate structure.
It is a side sectional view showing the structure of.
この図において、２１はｐ形不純物がドープされたｐ＋
ドレイン層となるシリコン基板で、不純物濃度は一般に
高＜ １０ ”ｃｍ−３程度である。２２は前記シリコ
ン基板２１上にエピタキシャル成長によって形成された
ｎ−ベース層、２３は前記ｎ−ベース層２２にｐ形不純
物を拡散して形成したｐ＋ベース層、２４は前記ｐ＋ベ
ース層３にざらに遭択拡散を行って形成したｎゝエミッ
タ層、２５はゲート形成用のトレンチ溝で、ｎ９工ミツ
タ層２４、ｐ１ベース層２３を突き抜けてｎ−ベース層
２２まで達する深さで掘られている。２６はゲート酸化
膜で、トレンチ溝２５の内壁を酸化するか、または酸化
シリコンを表面成長させることによって形成されている
。２７は前記トレンチ溝２５を埋め込むポリシリコン、
２８はソース電極（エミッタ電極に相当）で、ラッチア
ップ耐量を増加させるためにｐ＋ベース層２３、ｎ＋エ
ミッタ層２４をショートしている。２９はゲート電極（
ベース電極に相当）で、ゲート酸化膜２６の表面に形成
されている。３０はドレイン電極（コレクタ電極に相当
）で、シリコン基板２１の裏面全体に形成されている。In this figure, 21 is p+ doped with p-type impurities.
A silicon substrate serving as a drain layer has an impurity concentration of generally high <10"cm-3. 22 is an n-base layer formed on the silicon substrate 21 by epitaxial growth, and 23 is an n-base layer formed on the n-base layer 22. A p+ base layer formed by diffusing p-type impurities, 24 an n emitter layer formed by rough selective diffusion into the p+ base layer 3, 25 a trench groove for gate formation, and an n9 emitter layer. 24, it is dug to a depth that penetrates through the p1 base layer 23 and reaches the n-base layer 22. 26 is a gate oxide film, which is formed by oxidizing the inner wall of the trench groove 25 or by growing silicon oxide on the surface. 27 is polysilicon that fills the trench groove 25;
28 is a source electrode (corresponding to an emitter electrode), and the p+ base layer 23 and the n+ emitter layer 24 are short-circuited to increase latch-up resistance. 29 is the gate electrode (
(equivalent to a base electrode) is formed on the surface of the gate oxide film 26. Reference numeral 30 denotes a drain electrode (corresponding to a collector electrode), which is formed on the entire back surface of the silicon substrate 21.
また、第４図は第３図に示したＩ ＧＢＴの等価回路図
である。Further, FIG. 4 is an equivalent circuit diagram of the IGBT shown in FIG. 3.
この図において、第３図と同一符号は同一部分に対応し
、３１は前記ｐ＋ベース層２３中のシリーズ抵抗成分、
３２は前記ｎ１工ミツタ層２４゜前記ｐ４ベース層２３
および前記ｎ−ベース層２２から構成されるＮＰＮトラ
ンジスタ、３３は前記ｐ＋ベース層２３．前記ｎ−ベー
ス層２２および前記シリコン基板２１から構成されるＰ
ＮＰトランジスタ、３４は前記ｎ−ベース層２２中の可
変抵抗成分、３５は縦形ゲート部分に形成されているＭ
ＯＳＦＥＴである。なお、この縦形ゲートのＭＯＳＦＥ
Ｔ３５の部分は、例えば特開昭６１−２６２６１号公報
に記載されたような工程によって製作される。In this figure, the same symbols as in FIG. 3 correspond to the same parts, and 31 is a series resistance component in the p+ base layer 23;
32 is the N1 base layer 24° and the P4 base layer 23
and an NPN transistor 33 composed of the n-base layer 22, the p+ base layer 23. P composed of the n-base layer 22 and the silicon substrate 21
NP transistor; 34 is a variable resistance component in the n-base layer 22; 35 is an M transistor formed in the vertical gate portion;
It is an OSFET. In addition, this vertical gate MOSFE
The T35 portion is manufactured by the process described in, for example, Japanese Patent Laid-Open No. 61-26261.
次に動作について説明する。Next, the operation will be explained.
ソース電８ｉ２８に対してゲート電８ｉ２９を正に電圧
印加すると、ｐ＋ベース層２３とトレンチ溝２５の界面
にＮ型チャネルが形成され、ＭＯＳＦＥＴ３５が導通状
態となる。また、ソース電極２８に対して正の電圧がド
レイン電極３ｏに印加されているので、電子がＮ型チャ
ネルを通ってｎ′″エミッタ層２４からｎ−ベース層２
２に流れ込む。これによってｎ−ベース層２２の電位が
低下し、正孔がシリコン基板２１のｐ＋ドレイン層から
ｎ−ベース層２２に注入される。この結果、ｎ″″ベー
ス層２２に多数の正孔と電子が蓄積されｎ−ベース層２
２の比抵抗値が減少する。等価回路図上では可変抵抗成
分３４が減少することになり、ソース電極２８とドレイ
ン電極３０との間に大電流が流れ、ＩＧＢＴは導通状態
になる。When a positive voltage is applied to the gate voltage 8i29 to the source voltage 8i28, an N-type channel is formed at the interface between the p+ base layer 23 and the trench groove 25, and the MOSFET 35 becomes conductive. Further, since a positive voltage is applied to the drain electrode 3o with respect to the source electrode 28, electrons pass through the N type channel from the n'' emitter layer 24 to the n- base layer 2.
Flows into 2. This lowers the potential of the n- base layer 22, and holes are injected into the n- base layer 22 from the p+ drain layer of the silicon substrate 21. As a result, a large number of holes and electrons are accumulated in the n'' base layer 22, and the n-base layer 22
The specific resistance value of 2 decreases. On the equivalent circuit diagram, the variable resistance component 34 decreases, a large current flows between the source electrode 28 and the drain electrode 30, and the IGBT becomes conductive.
この時、ｐ＋ドレイン層から注入された正孔の大部分は
ｎ″″ベース層２層内２内いて、ソース電極２８から流
れ込む電子と再結合するが、残りの正孔はｐ＋ベース層
２３へ流れ込む。この残りに当たる正孔電流は、等価回
路図上のＰＮＰトランジスタ３３を経てＮＰＮトランジ
スタ３２のベース側とシリーズ抵抗成分３１を通ってソ
ース電極２８へ流れ込んでいる。このソース電極２８は
ｎ０工ミツタ層２４とｐ′″ベース層２３をショートし
ているのでシリーズ抵抗成分３１は原理的にゼロである
が、ｐ１ベース層２３に流れ込んだ正孔電流の経路によ
って寄与される抵抗成分の総和を考えたときのシリーズ
抵抗成分３１は無視できない。そして、ソース電極２８
とドレイン電極３０の間を流れる電流が増加するに従っ
て、シリーズ抵抗成分３１を流れる正孔電流も増加する
。At this time, most of the holes injected from the p+ drain layer enter the n″″ base layer 2 and recombine with the electrons flowing from the source electrode 28, but the remaining holes flow into the p+ base layer 23. Flow into. The remaining hole current flows into the source electrode 28 via the PNP transistor 33 on the equivalent circuit diagram, the base side of the NPN transistor 32, and the series resistance component 31. Since this source electrode 28 short-circuits the n0 semiconductor layer 24 and the p'' base layer 23, the series resistance component 31 is theoretically zero, but it is contributed by the path of the hole current flowing into the p1 base layer 23. The series resistance component 31 cannot be ignored when considering the total resistance component of the source electrode 28.
As the current flowing between the drain electrode 30 and the drain electrode 30 increases, the hole current flowing through the series resistance component 31 also increases.
その結果、ソース電極２８とＮＰＮトランジスタ３２の
ベース間の電位差が広がり、ついにはＮＰＮトランジス
タ３２をオン状態にしてしまうことになる。この現象を
ラッチアップといい、ＭＯＳＦＥＴ３５を経由してドレ
イン電極３０からソース電極２８へ流れていた電流が、
Ｎ Ｐ Ｎトランジスタ３２を経由して流れることにな
り、ゲート電極２９によるＩＩＨＸＩが不可能となる。As a result, the potential difference between the source electrode 28 and the base of the NPN transistor 32 increases, eventually turning the NPN transistor 32 on. This phenomenon is called latch-up, and the current flowing from the drain electrode 30 to the source electrode 28 via the MOSFET 35 is
The current flows through the N P N transistor 32, and IIHXI by the gate electrode 29 becomes impossible.
上記のような従来の縦形ゲート構造Ｉ ＧＢＴでは、ｎ
“エミツタ層２４とｐ＋ベース層２３をショートしてい
るが、これだけではラッチアップを完全に防止できない
ので、電流密度が高くなると等価回路図上のＮＰＮトラ
ンジスタ３２がラッチアップし、素子をゲートでコント
ロールできなくなっていた。In the conventional vertical gate structure IGBT as described above, n
“The emitter layer 24 and the p+ base layer 23 are short-circuited, but this alone cannot completely prevent latch-up, so when the current density increases, the NPN transistor 32 on the equivalent circuit diagram will latch-up, and the device will be controlled by the gate. I couldn't do it anymore.
この発明は、かかる課題を解決するためになされたもの
で、縦形ゲート構造ＩＧＢＴの利点である大電流駆動能
力と低オン抵抗の特徴を損なうことなく、かつプロセス
に大幅な変更を与えることなしにラッチアップ耐量が従
来のものより格段に増加する半導体装置を得ることを目
的とする。This invention was made in order to solve such problems, and without impairing the characteristics of large current drive capability and low on-resistance, which are the advantages of vertical gate structure IGBTs, and without making significant changes to the process. An object of the present invention is to obtain a semiconductor device whose latch-up resistance is significantly increased compared to conventional devices.
この発明の第１の発明に係る半導体装置は、第１の導電
型の第１の領域と、この第１の領域の主表面上に形成さ
れた第２の導電型の第２の領域と、この第２の領域の主
表面上に形成された第１の導電型の第３の領域と、この
第３の領域の主表面上から選択的に不純物を拡散して第
３の領域内に形成された第２の導電型の第４の領域と、
この第４の領域の主表面上から形成され、その側面に少
なくとも第４の領域および第３の領域を露出させ、その
底面に第２の領域を露出させる第１のトレンチ溝と、こ
の第１のトレンチ溝の側面および底面に形成された酸化
膜と、この酸化膜上に形成され、第４の領域、第３の領
域および第２の領域と対向する制御電極と、第３の領域
の主表面上から形成され、その側面の一部または全部に
第４の領域を露出させ、その底面に第３の領域を露出さ
せる第２のトレンチ溝と、この第２の゛トレンチ溝の側
面および底面と第４の領域の主表面上に形成された第１
の主電極と、第１の領域の他の主表面上に形成された第
２の主電極とから構成したものである。A semiconductor device according to a first aspect of the present invention includes: a first region of a first conductivity type; a second region of a second conductivity type formed on the main surface of the first region; A third region of the first conductivity type formed on the main surface of this second region, and a third region formed in the third region by selectively diffusing impurities from the main surface of this third region. a fourth region of a second conductivity type,
a first trench formed on the main surface of the fourth region, exposing at least the fourth region and the third region on the side surfaces thereof, and exposing the second region on the bottom surface; an oxide film formed on the side and bottom surfaces of the trench groove, a control electrode formed on the oxide film and facing the fourth region, the third region, and the second region; a second trench groove formed on the surface, exposing a fourth region on a part or all of the side surface and exposing a third region on the bottom surface; and a side surface and a bottom surface of the second trench groove. and the first region formed on the main surface of the fourth region.
and a second main electrode formed on the other main surface of the first region.
また、この発明の第２の発明に係る半導体装置は、第１
の発明における第２のトレンチ溝の代わりに第３の領域
の主表面上から第１の導電型で高不純物濃度め第５の領
域を形成し、この第５の領域と第４の領域とを第１の主
電極により短絡したものである。Further, a semiconductor device according to a second aspect of the present invention is a semiconductor device according to a second aspect of the present invention.
In the invention, a fifth region of the first conductivity type and high impurity concentration is formed on the main surface of the third region instead of the second trench, and the fifth region and the fourth region are connected to each other. This is short-circuited by the first main electrode.
この発明の第１の発明においては、第２のトレンチ溝の
形成によって、また第２の発明においては、低抵抗値の
第５の領域の形成によって、第３の領域が縮小されるこ
とにより、第３の領域と第１の主電極間のシリーズ抵抗
成分が小さくなり、第３．の領域をベースとする寄生ト
ランジスタがオンしにくくなる。In the first aspect of the present invention, the third region is reduced by forming the second trench, and in the second invention, by forming the fifth region having a low resistance value. The series resistance component between the third region and the first main electrode becomes smaller, and the third. The parasitic transistor based on the region becomes difficult to turn on.
（実施例）
第１図（ａ）〜（Ｃ）はこの発明の第１の発明の半導体
装置の一実施例の製造工程を示す側断面図である。(Embodiment) FIGS. 1A to 1C are side sectional views showing the manufacturing process of an embodiment of a semiconductor device according to the first aspect of the present invention.
これらの図において、１はｐ形不純物がドープされたｐ
＋ドレイン層（第１の領域）となるシリコン基板、２は
前記シリコン基板１上にエピタキシャル成長によって形
成された第２の領域とじてのｎ−べ一諷層、３は前記ｎ
−ベース層２にｐ形不純物を拡散して形成した第３の領
域としてのｐ０ベース層、４は前記ｐ３ベース層３にさ
らに選択拡散を行って形成した第４の領域としてのｎ０
工ミツタ層、５ａはゲート形成用の第１のトレンチ溝、
５ｂは第２のトレンチ溝、６はゲート酸化膜で、第１の
トレンチ溝５ａの内壁を酸化するか、または酸化シリコ
ンを表面成長させることによって形成されている。７は
前記第１および第２のトレンチ溝５ａ、５ｂを埋め込む
ポリシリコン、８は第１の主電極としてのソース電極（
エミッタ電極に相当）で、ラッチアップ耐量を増加させ
るためにｐ′″ベース層３とｎ０工ミツタ層４をショー
トしている。９は制御電極としてのゲート電極（ベース
電極に相当）で、ゲート酸化膜６の表面に形成されてい
る。１０は第２の主電極としてのドレイン電極（コレク
タ電極に相当）で、シリコン基板１の裏面全体に形成さ
れている。１１は前記第２のトレンチ溝５ｂを形成する
ためのレジスト膜である。In these figures, 1 is p doped with p-type impurities.
2 is a silicon substrate that will become a drain layer (first region); 2 is an n-base layer that is a second region formed on the silicon substrate 1 by epitaxial growth; 3 is an n
- a p0 base layer as a third region formed by diffusing p-type impurities into the base layer 2, and 4 an n0 region as a fourth region formed by further selectively diffusing the p3 base layer 3;
5a is a first trench groove for gate formation;
5b is a second trench groove, and 6 is a gate oxide film, which are formed by oxidizing the inner wall of the first trench groove 5a or by growing silicon oxide on the surface. 7 is polysilicon that fills the first and second trench grooves 5a and 5b; 8 is a source electrode (as a first main electrode);
9 is a gate electrode (corresponding to a base electrode) as a control electrode, and the p''' base layer 3 and n0 emitter layer 4 are shorted to increase latch-up resistance.9 is a gate electrode (corresponding to a base electrode) as a control electrode. It is formed on the surface of the oxide film 6. Reference numeral 10 is a drain electrode (corresponding to a collector electrode) as a second main electrode, which is formed on the entire back surface of the silicon substrate 1. Reference numeral 11 is the second trench groove. This is a resist film for forming 5b.
次に製造工程について説明する。Next, the manufacturing process will be explained.
まず、第１図（ａ）に示すように、ソース電極８および
ドレイン電極１０の形成前の従来と同じ形の縦形ゲート
構造ＩＧＢＴのソース側表面を平坦化し、このソース側
表面なｐ“ベース層３の露出領域を除いてレジスト膜１
１で覆う。First, as shown in FIG. 1(a), the source side surface of the conventional vertical gate structure IGBT before the formation of the source electrode 8 and drain electrode 10 is planarized, and a p" base layer is formed on this source side surface. Resist film 1 except for the exposed area of 3
Cover with 1.
次に第１図（ｂ）に示すように、レジスト膜１１をマス
クとして第２のトレンチ溝５ｂを掘り、２１ベ一ス層３
の表面側領域を削除する。Next, as shown in FIG. 1(b), a second trench groove 5b is dug using the resist film 11 as a mask, and a second trench groove 5b is dug using the resist film 11 as a mask.
Delete the surface area of .
この後、レジスト膜１１を除去し、第１図（Ｃ）に示す
ように、第２のトレンチ溝５ｂの側壁および底面まで伸
長した形でソース電極８を形成し、次いで、ドレイン電
極１０を従来と同じ要領で形成するとともに、第２のト
レンチ溝５ｂをポリシリコン７で埋め込めば半導体装置
が完成する。Thereafter, the resist film 11 is removed, and as shown in FIG. The semiconductor device is completed by forming the second trench groove 5b in the same manner as above and filling the second trench groove 5b with polysilicon 7.
すなわち、この第１の発明の半導体装置では、第２のト
レンチ溝５ｂを形成してｐ４べ５−ス層３を縮小すると
ともに、この第２のトレンチ溝５ｂの底面まで伸長した
形でソース電極８を形成したので、ｐ＋ベース層３とソ
ース電極８間のシリーズ抵抗成分が大幅に小さくなり、
従来のＩＧＢＴと同じ電流駆動条件で使用した場合、ｐ
１ベース層３をベースとする寄生トランジスタ（第４図
中のＮＰＮトランジスタ３２に対応）にかかるベース駆
動電圧が低下し、同トランジスタがオンしにくくラッチ
アップが生じにくくなることがわかる。That is, in the semiconductor device of the first invention, the second trench groove 5b is formed to reduce the size of the p4 base layer 3, and the source electrode is extended to the bottom surface of the second trench groove 5b. 8, the series resistance component between the p+ base layer 3 and the source electrode 8 is significantly reduced.
When used under the same current drive conditions as conventional IGBTs, p
It can be seen that the base drive voltage applied to the parasitic transistor (corresponding to the NPN transistor 32 in FIG. 4) based on the 1-base layer 3 is reduced, making it difficult for the transistor to turn on and to cause latch-up.
また、第２図（ａ）、（ｂ）は、この発明の第２の発明
の半導体装置の一実施例の製造工程を示す側断面図であ
る。Moreover, FIGS. 2(a) and 2(b) are side sectional views showing the manufacturing process of an embodiment of the semiconductor device of the second invention of the present invention.
これらの図において、第１図（ａ）〜（Ｃ・）と同一符
号は同一のものを示し、１２は第５の領域としてのｐ＋
＋高濃度拡散領域である。In these figures, the same reference numerals as in FIGS.
+ High concentration diffusion region.
この発明でも、第２図（ａ）に示すように、まずソース
側表面を平坦化し、このソース側表面をｐ＋ベース層３
の露出部分を除いてレジスト膜１１で覆う。次いで、矢
印のようにｐ形不純物のデポジションを行い、２１ベ一
ス層３の表面領域に第２図（ｂ）に示すようなｐ＋４高
濃度拡散領域１２を形成する。なお。この時のデポジシ
ョンおよび拡散の条件によりレジスト膜１１のエツジの
位置は微妙に変化する。そして、この後レジスト膜１１
を除去し、ソース電極８とドレインｔ８ｉ１０を形成す
れば半導体装置が完成する。In this invention as well, as shown in FIG.
It is covered with a resist film 11 except for the exposed portion. Next, a p-type impurity is deposited as shown by the arrow to form a p+4 high concentration diffusion region 12 in the surface region of the 21 base layer 3 as shown in FIG. 2(b). In addition. The position of the edge of the resist film 11 changes slightly depending on the deposition and diffusion conditions at this time. After this, the resist film 11
The semiconductor device is completed by removing the source electrode 8 and forming the drain t8i10.
すなわち、この第２の発明では低抵抗値のｐ０高濃度拡
散領域１２を設けてｐ１ベース層３とソース電極８間の
シリーズ抵抗成分を小さくしているが、上記第１の発明
と同様にラッチアップ耐量を向上させることが可能であ
る。That is, in this second invention, the p0 high concentration diffusion region 12 with a low resistance value is provided to reduce the series resistance component between the p1 base layer 3 and the source electrode 8, but as in the first invention, the latch It is possible to improve the up resistance.
なお、上記実施例では、縦形ＩＧＢＴの場合について説
明したが、■字形のＩＧＢＴであってもよく、Ｐチャネ
ル形ＩＧＢＴにおいても同様の効果を奏することはいう
までもない。In the above embodiment, a vertical IGBT has been described, but it may be a square-shaped IGBT, and it goes without saying that a P-channel IGBT can also produce the same effect.
この発明の第１の発明は以上説明したとおり、第１の導
電型の第１の領域と、この第１の領域の主表面上に形成
された第２の導電型の第２の領域と、この第２の領域の
主表面上に形成された第１の導電型の第３の領域と、こ
の第３の領域の主表面上から選択的に不純物を拡散して
第３の領域内に形成された第２の導電型の第４の領域と
、この第４の領域の主表面上から形成され、その側面に
少なくとも第４の領域および第３の領域を露出させ、そ
の底面に第２の領域を露出させる第１のトレンチ溝と、
この第１のトレンチ溝の側面および底面に形成された酸
化膜と、この酸化膜上に形成され、第４の領域、第３の
領域および第２の領域と対向する制御電極と、第３の領
域の主表面上から形成され、その側面の一部または全部
に第４の領域を露出させ、その底面に第３の領域を露出
させる第２のトレンチ溝と、この第２のトレンチ溝の側
面および底面と第４の領域の主表面上に形成された第１
の主電極と、第１の領域の他の主表面上に形成された第
２の主電極とから構成し、また、この発明の第２の発明
は、上記の第２のトレンチ溝の代わりに第３の領域の主
表面から第１の導電型で高不純物濃度の第５の領域を形
成し、この第５の領域と第４の領域とを第１の主電極に
より短絡したので、第３の領域と第１の主電極間のシリ
ーズ抵抗成分が小さくなり、第３の領域をベースとする
寄生トランジスタがオンしにくく、ラッチアップの発言
を抑止でき、より大きい電流駆動能力が得られるという
効果がある。As explained above, the first aspect of the present invention includes a first region of a first conductivity type, a second region of a second conductivity type formed on the main surface of the first region, A third region of the first conductivity type formed on the main surface of this second region, and a third region formed in the third region by selectively diffusing impurities from the main surface of this third region. a fourth region of a second conductivity type formed on the main surface of the fourth region, at least the fourth region and the third region are exposed on the side surfaces thereof, and a second conductivity type is formed on the bottom surface of the fourth region. a first trench exposing the region;
An oxide film formed on the side and bottom surfaces of the first trench groove, a control electrode formed on the oxide film and facing the fourth region, the third region, and the second region; a second trench groove formed on the main surface of the region, exposing the fourth region on a part or all of the side surface thereof, and exposing the third region on the bottom surface thereof; and the side surface of the second trench groove. and a first region formed on the bottom surface and the main surface of the fourth region.
and a second main electrode formed on the other main surface of the first region. A fifth region of the first conductivity type and high impurity concentration was formed from the main surface of the third region, and this fifth region and the fourth region were short-circuited by the first main electrode. The effect is that the series resistance component between the region and the first main electrode is reduced, the parasitic transistor based on the third region is difficult to turn on, latch-up can be suppressed, and a larger current drive capability can be obtained. There is.
第１図はこの発明の第１の発明の半導体装置の一実施例
の製造工程を示す側断面図、第２図はこの発明の第２の
発明の一実施例の製造工程を示す側断面図、第３図は従
来の縦形ゲート構造ｒＧＢＴの構造を示す側断面図、第
４図はＩＧＢＴの等価回路図である。
図において、１はシリコン基板、２はｎ−ベース層、３
はｐ＋ベース層、４はｎ＋エミッタ層、５ａは第１のト
レンチ溝、５ｂは第２のトレンチ溝、６はゲート酸化膜
、７はポリシリコン、８はソース電極、９はゲート電極
、１０はドレイン電極、１１はレジスト膜、１２はｐ−
高濃度拡散領域である。
なお、各図中の同一符号は同一または相当部分を示す。
第１図
第２図
１２、ρ００高漬鷹拡散領域
第３因
第４図
手続補正書（自発）FIG. 1 is a side sectional view showing the manufacturing process of an embodiment of a semiconductor device according to the first invention of the present invention, and FIG. 2 is a side sectional view showing the manufacturing process of an embodiment of the second invention of the invention. 3 is a side sectional view showing the structure of a conventional vertical gate structure rGBT, and FIG. 4 is an equivalent circuit diagram of the IGBT. In the figure, 1 is a silicon substrate, 2 is an n-base layer, and 3 is a silicon substrate.
is a p+ base layer, 4 is an n+ emitter layer, 5a is a first trench groove, 5b is a second trench groove, 6 is a gate oxide film, 7 is polysilicon, 8 is a source electrode, 9 is a gate electrode, 10 is a Drain electrode, 11 resist film, 12 p-
This is a high concentration diffusion region. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1 Figure 2 Figure 12, ρ00 Takatsuka Diffusion Area 3rd Factor Figure 4 Procedural Amendment (Voluntary)
Claims (2)
主表面上に形成された第２の導電型の第２の領域と、こ
の第２の領域の主表面上に形成された第１の導電型の第
３の領域と、この第３の領域の主表面上から選択的に不
純物を拡散して第３の領域内に形成された第２の導電型
の第４の領域と、この第４の領域の主表面上から形成さ
れ、その側面に少なくとも第４の領域および前記第３の
領域を露出させ、その底面に前記第２の領域を露出させ
る第１のトレンチ溝と、この第１のトレンチ溝の側面お
よび底面に形成された酸化膜と、この酸化膜上に形成さ
れ、前記第４の領域、前記第３の領域および前記第２の
領域と対向する制御電極と、前記第３の領域の主表面上
から形成され、その側面の一部または全部に前記第４の
領域を露出させ、その底面に前記第３の領域を露出させ
る第２のトレンチ溝と、この第２のトレンチ溝の側面お
よび底面と前記第４の領域の主表面上に形成された第１
の主電極と、前記第１の領域の他の主表面上に形成され
た第２の主電極とから構成したことを特徴とする半導体
装置。(1) A first region of a first conductivity type, a second region of a second conductivity type formed on the main surface of this first region, and a second region formed on the main surface of this second region. A third region of the first conductivity type is formed, and a fourth region of the second conductivity type is formed within the third region by selectively diffusing impurities from the main surface of the third region. and a first trench formed on the main surface of the fourth region, exposing at least the fourth region and the third region on its side surfaces, and exposing the second region on its bottom surface. a trench, an oxide film formed on the side and bottom surfaces of the first trench trench, and a control layer formed on the oxide film and facing the fourth region, the third region, and the second region. an electrode; and a second trench groove formed on the main surface of the third region, exposing the fourth region on part or all of the side surfaces thereof, and exposing the third region on the bottom surface thereof; , a first trench formed on the side and bottom surfaces of the second trench groove and the main surface of the fourth region.
A semiconductor device comprising: a main electrode; and a second main electrode formed on the other main surface of the first region.
ンチ溝の代わりに第３の領域の主表面上から第１の導電
型で高不純物濃度の第５の領域を形成し、この第５の領
域と第４の領域とを第１の主電極により短絡したことを
特徴とする半導体装置。(2) In the semiconductor device according to claim 1, a fifth region of the first conductivity type and a high impurity concentration is formed from above the main surface of the third region in place of the second trench, and the fifth region has a high impurity concentration. A semiconductor device characterized in that the region and the fourth region are short-circuited by a first main electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63023252A JPH01198076A (en) | 1988-02-02 | 1988-02-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63023252A JPH01198076A (en) | 1988-02-02 | 1988-02-02 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01198076A true JPH01198076A (en) | 1989-08-09 |
Family
ID=12105408
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63023252A Pending JPH01198076A (en) | 1988-02-02 | 1988-02-02 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01198076A (en) |
Cited By (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5316959A (en) * | 1992-08-12 | 1994-05-31 | Siliconix, Incorporated | Trenched DMOS transistor fabrication using six masks |
| US5329142A (en) * | 1991-08-08 | 1994-07-12 | Kabushiki Kaisha Toshiba | Self turn-off insulated-gate power semiconductor device with injection-enhanced transistor structure |
| US5385852A (en) * | 1993-01-14 | 1995-01-31 | Siemens Aktiengesellschaft | Method for manufacturing vertical MOS transistors |
| EP0654173A1 (en) * | 1992-08-07 | 1995-05-24 | Advanced Power Technology Inc. | High density power device structure and fabrication process |
| US5572055A (en) * | 1992-11-09 | 1996-11-05 | Fuji Electric Co., Ltd. | Insulated-gate bipolar transistor with reduced latch-up |
| US5578851A (en) * | 1994-08-15 | 1996-11-26 | Siliconix Incorporated | Trenched DMOS transistor having thick field oxide in termination region |
| EP0755076A2 (en) * | 1995-07-21 | 1997-01-22 | Mitsubishi Denki Kabushiki Kaisha | Vertical MOS semiconductor with recessed gate and method of manufacturing the same |
| US5597765A (en) * | 1995-01-10 | 1997-01-28 | Siliconix Incorporated | Method for making termination structure for power MOSFET |
| US5623152A (en) * | 1995-02-09 | 1997-04-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
| US5925899A (en) * | 1997-05-27 | 1999-07-20 | Mitsubishi Denki Kabushiki Kaisha | Vertical type insulated gate bipolar transistor having a planar gate structure |
| US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| US6118150A (en) * | 1996-04-01 | 2000-09-12 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and method of manufacturing the same |
| WO2001065606A3 (en) * | 2000-02-28 | 2002-02-14 | Infineon Technologies Ag | Field effect transistor configuration having a high latch-up strength and method for the production thereof |
| KR100429475B1 (en) * | 1998-06-02 | 2004-05-03 | 실리코닉스 인코퍼레이티드 | Vertical trench-gated power mosfet having stripe geometry and high cell density, and manufacturing method thereof |
| JP2006140263A (en) * | 2004-11-11 | 2006-06-01 | Sanken Electric Co Ltd | Semiconductor element and manufacturing method thereof |
| CN105374859A (en) * | 2015-11-10 | 2016-03-02 | 株洲南车时代电气股份有限公司 | Trench gate type IGBT chip and manufacturing method therefor |
| US9508596B2 (en) | 2014-06-20 | 2016-11-29 | Vishay-Siliconix | Processes used in fabricating a metal-insulator-semiconductor field effect transistor |
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Cited By (40)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5801417A (en) * | 1988-05-17 | 1998-09-01 | Advanced Power Technology, Inc. | Self-aligned power MOSFET device with recessed gate and source |
| US5329142A (en) * | 1991-08-08 | 1994-07-12 | Kabushiki Kaisha Toshiba | Self turn-off insulated-gate power semiconductor device with injection-enhanced transistor structure |
| US5648283A (en) * | 1992-08-07 | 1997-07-15 | Advanced Power Technology, Inc. | High density power device fabrication process using undercut oxide sidewalls |
| EP0654173A1 (en) * | 1992-08-07 | 1995-05-24 | Advanced Power Technology Inc. | High density power device structure and fabrication process |
| EP0654173A4 (en) * | 1992-08-07 | 1996-08-14 | Advanced Power Technology | STRUCTURE OF A HIGH DENSITY POWER DEVICE AND METHOD FOR THE PRODUCTION THEREOF. |
| US5316959A (en) * | 1992-08-12 | 1994-05-31 | Siliconix, Incorporated | Trenched DMOS transistor fabrication using six masks |
| US5572055A (en) * | 1992-11-09 | 1996-11-05 | Fuji Electric Co., Ltd. | Insulated-gate bipolar transistor with reduced latch-up |
| US5624855A (en) * | 1992-11-09 | 1997-04-29 | Fuji Electric Co., Ltd. | Process of producing insulated-gate bipolar transistor |
| US5385852A (en) * | 1993-01-14 | 1995-01-31 | Siemens Aktiengesellschaft | Method for manufacturing vertical MOS transistors |
| US6323508B1 (en) | 1994-02-21 | 2001-11-27 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| US6107650A (en) * | 1994-02-21 | 2000-08-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| US6331466B1 (en) | 1994-02-21 | 2001-12-18 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and manufacturing method thereof |
| US5578851A (en) * | 1994-08-15 | 1996-11-26 | Siliconix Incorporated | Trenched DMOS transistor having thick field oxide in termination region |
| US5639676A (en) * | 1994-08-15 | 1997-06-17 | Siliconix Incorporated | Trenched DMOS transistor fabrication having thick termination region oxide |
| US5614751A (en) * | 1995-01-10 | 1997-03-25 | Siliconix Incorporated | Edge termination structure for power MOSFET |
| US5597765A (en) * | 1995-01-10 | 1997-01-28 | Siliconix Incorporated | Method for making termination structure for power MOSFET |
| US5623152A (en) * | 1995-02-09 | 1997-04-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device |
| EP1237201A3 (en) * | 1995-07-21 | 2003-04-23 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and method of manufacturing the same |
| KR100250350B1 (en) * | 1995-07-21 | 2000-04-01 | 다니구찌 이찌로오 | Manufacturing method of an insulated gate type semiconductor device |
| EP0755076A2 (en) * | 1995-07-21 | 1997-01-22 | Mitsubishi Denki Kabushiki Kaisha | Vertical MOS semiconductor with recessed gate and method of manufacturing the same |
| EP1237201A2 (en) * | 1995-07-21 | 2002-09-04 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and method of manufacturing the same |
| EP0755076A3 (en) * | 1995-07-21 | 1997-02-19 | Mitsubishi Electric Corp | |
| KR100272057B1 (en) * | 1996-04-01 | 2000-11-15 | 다니구찌 이찌로오 | Insulated gate semiconductor device and method of manufacturing the same |
| US6118150A (en) * | 1996-04-01 | 2000-09-12 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and method of manufacturing the same |
| KR100353605B1 (en) * | 1996-04-01 | 2002-09-27 | 미쓰비시덴키 가부시키가이샤 | Isulated Gate Semiconductor Device |
| USRE38953E1 (en) | 1996-04-01 | 2006-01-31 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate semiconductor device and method of manufacturing the same |
| US5925899A (en) * | 1997-05-27 | 1999-07-20 | Mitsubishi Denki Kabushiki Kaisha | Vertical type insulated gate bipolar transistor having a planar gate structure |
| KR100429475B1 (en) * | 1998-06-02 | 2004-05-03 | 실리코닉스 인코퍼레이티드 | Vertical trench-gated power mosfet having stripe geometry and high cell density, and manufacturing method thereof |
| WO2001065606A3 (en) * | 2000-02-28 | 2002-02-14 | Infineon Technologies Ag | Field effect transistor configuration having a high latch-up strength and method for the production thereof |
| JP2006140263A (en) * | 2004-11-11 | 2006-06-01 | Sanken Electric Co Ltd | Semiconductor element and manufacturing method thereof |
| US9935193B2 (en) | 2012-02-09 | 2018-04-03 | Siliconix Technology C. V. | MOSFET termination trench |
| US9614043B2 (en) | 2012-02-09 | 2017-04-04 | Vishay-Siliconix | MOSFET termination trench |
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| US9842911B2 (en) | 2012-05-30 | 2017-12-12 | Vishay-Siliconix | Adaptive charge balanced edge termination |
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| US9882044B2 (en) | 2014-08-19 | 2018-01-30 | Vishay-Siliconix | Edge termination for super-junction MOSFETs |
| CN105374859B (en) * | 2015-11-10 | 2018-09-14 | 株洲南车时代电气股份有限公司 | A kind of trench gate igbt chip and preparation method thereof |
| CN105374859A (en) * | 2015-11-10 | 2016-03-02 | 株洲南车时代电气股份有限公司 | Trench gate type IGBT chip and manufacturing method therefor |
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