JPH01197800A - Sound recording and reproducing method using adpcm code - Google Patents

Abstract

PURPOSE:To perform sound recording and reproduction without spoiling the reproduced waveform by reading out the ADPCM code of one cycle before from a memory and calculating the function value required for decoding the ADPCM code, and then, setting the function value to a waiting state before a new ADPCM code is written in the memory. CONSTITUTION:When sound recording is stopped at an address (n) of Y-th cycle by means of a sound recording stopping instruction and reproduction is started, the ADPCM code LnY<-1> of the address (n) stored in a memory 32 at the (Y-1)th cycle which is one cycle before of the Y-th cycle is read out and sent to an ADPCM decoding circuit 26 through an output latch 21. At the circuit 26, XnY<-1> and nY<-1> are calculated following a decoding formula and the calculated values are held until the next cycle. On the other hand, the then inputted new ADPCM code LnY is written in the address (n) of the memory 32. Thereafter, the reproducing operations are started by means of a sound recording stopping signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a recording/playback method in a recording/playback system capable of recording and reverse upstream playback using ADPCM codes.

[Prior art] Figure 2 shows PCM (Pulse Code Mod).
This is a general recording and playback system that uses ration) codes. The configuration is roughly divided into a recording system (10), a playback system (20), a data storage section (30), and a control section (40).

The recording system (lO) is MIC (microphone') (11
) and AMP (Amblifier - Signal Amplifier) (
12), or an audio LINE IN input and an AMP that further amplifies the input signal.
(11), LPF (low pass filter) that cuts high frequency components (14>, and L P F (14)
It is connected to an ADC (AD converter) (15) that converts analog signals into digital signals, and an input latch (1B) that temporarily stores digital values.

The digital input signal stored in the input latch (1B) is appropriately controlled by the memory control circuit (31) and stored in the subsequent memory (32).

The reproduction system (20) includes an output latch circuit (21) that temporarily stores the digital output signal taken out as appropriate under the control of the memory control circuit (31), and a DAC (DA converter) that converts the output digital signal into an analog signal. (2)
and LP F (23) that cuts high frequency components. Then, the output of LPF (23) is made the audio LINE OUT,
Or A M P (24) and SP (speaker) (
25).

The data storage section (30) includes the aforementioned memory control circuit (31).
) and a memory (32), and the memory (32) is a semiconductor memory device such as RAM or EEFROM for boat fishing. This memory (32) is an input latch (1B)
and an output latch (21) through a data line (33), and a memory control circuit (31) through an address and other control line (34).

The control unit (40) controls external recording and playback, and
This system correctly executes the aforementioned recording system, playback system, and memory control in response to commands such as CP and stop.
It consists of USROM, RAM, etc.

When using a recording/playback system as shown in Figure 2 to create, for example, a decoupling machine (a recording/playback device that listens all the time but can play back in time repeatedly when necessary), the conventional method is as follows. A method is being adopted.

FIG. 3 is a circuit diagram of the data storage section (30) when realizing the above-mentioned deduction machine.

FIG. 4 is a state diagram showing the memory (32) and the contents of data stored in the memory using analog signals.

The capacity of the memory (32) in Figure 3 is the capacity for t time required for playback, and the number of memory addresses (N+1)
It is determined by the product of and the number of bits (K).

The memory control circuit (31) in Fig. 3 is an address counter (
35), address latch (3B) and matching circuit (37)
It consists of

The address counter (35) performs a cyclic operation in which it counts up the addresses in the memory (32) sequentially from 0 to M from the bottom, returns to 0 again when it reaches M, and counts up again from the bottom. During recording, bit data is written and accumulated according to the write command signal every time the count is up.If one cycle is from address 0 to address M, then in the next cycle,
Starting from address 0, previous data is destroyed and new data is stored.

FIG. 4 is a diagram showing a state in which the aforementioned recording cycle has extended to X cycles and the address has progressed to N (0≦N≦M). In this state, data at addresses 0 to N in the (X-1)th cycle has already been updated. If a recording stop command is input at this point and then a play command command is input, a read command signal is input to the memory (32), the playback system is enabled, and the addresses are counted up in order from (N+1). bit data begins to be read out.

Then, when the address reaches M, it similarly returns to 0, counts up again, and reaches N. Address (N+1
) to MN corresponds to exactly one cycle, which means that playback for t hours can be realized.

The address latch (36) in FIG. 3 receives a latch signal when a reproduction instruction command is input, and temporarily stores the data at address N. For example, when stopping the reproduction after one cycle, the address latch (36) is connected to a matching circuit (37). In conjunction, a stop signal is generated just when the address returns to N.

In addition, if you want to repeat playback one after another without worrying about one cycle, ignore the stop signal and change the addresses ~M, 0~ until a forced stop command signal is input from the outside.
'M, cyclically repeats the addresses 0 to M.

When a recording start command is received again after a playback stop signal or an external forced stop command, the control system stops the playback system and operates the recording system, and the command signal to the memory is a command signal from read to write. Switch to .

And the address counter (35) is the address (N+1
), the count-up will start again and the same operation as in the initial recording state will be performed.

With such a device, in order to record and play back the same time t,
If the memory capacity is to be further reduced, a compression technique such as ADPCM must be added in place of the PCM code. For example, the bit length of PCM is 12 bits (or 8 bits), while that of ADPCM is 4 bits. Therefore, it is possible to configure a similar system with 1/3 to 1/2 the memory capacity.

FIG. 5 is a block diagram of a recording/playback system using ADPCM codes. Compared to Figure 2, the recording system (to) is inserted after the ADC (5), and the playback system (20) is inserted after the ADC (5).
(22) This can be realized by simply inserting the ADPCM decoding circuit (2B) before (7).

[Problem to be solved by the invention] However, with this recording and playback system shown in Fig. 5, PCM
With the same control as when using codes, smaller memory (for example, M (address) becomes smaller or K
(number of bits) becomes smaller. ), the sixth
Problems as shown in the figure arise.

FIG. 6 is an explanatory diagram of reproduced waveforms of this system. For example, the ADPCM code string corresponding to the time is LO, Ll
, L2. ......LM. It is assumed that Ln of this human DPCM code string is composed of a 4-bit digital value. Further, the digital code strings decoded by each of the above Ln are XO and XI.

X2.・・・・・・If it is XM, - boat fishing ADPCM
Based on the principle, Xn is derived from the following formula.

Xn −Xn−1+ q n −(1)
Qn - (Ln + 1/2) Δn - (2) Δ
n-Δn-1 ・M (I Ln-11) −(3)
Here, qn is the digital difference value, Δn is the quantization width 1
M is a function of t and n.

In order to accurately obtain Xn using the above equations (1), (2), and (3), Xn-1 and Δn must be clearly defined. Due to the principle of ADPCM, X n-
1 and Δn are determined by the accumulation from the beginning, so in this system, X at time t before starting reverse upstream playback.
If n and Δn are known, a reproduced waveform (1) as shown in (a) in Figure 6 will be obtained; however, if xn is not accurate, a reproduced waveform (2) as shown in (b) in Figure 6 will be obtained. If .DELTA.n is not accurate, the reproduced waveform (3) as shown in FIG. 6(c) will be obtained, which is different from the expected reproduced waveform.

To solve this problem, when recording, Xn and Δn should always be stored in memory together with the ADPCM code Ln every tn times, but in that case, Ln is 4 bits, while Xn is 12 bits. , .DELTA.n are 6 bits, resulting in a total of 22 bits of data, which creates a new problem in that the data amount exceeds the data amount by PCM described above.

This invention was made in order to solve the above-mentioned problems, and is an ADPC that does not damage the reproduced waveform by storing only the ADPCM code as the data stored in the memory.
The purpose is to obtain a recording/playback method using M code.

[Means to solve the problem] FIG. 1 is an explanatory diagram showing the configuration of the present invention.

A recording/playback method using an ADPCM code according to the present invention is a recording/playback method in which writing to and reading from a memory is performed cyclically using an ADPCM code.
Due to memory address specification during recording, 1 from now.
a step of reading the ADPCM code stored at the address before the cycle; a step of calculating a function value necessary for decoding the ADPCM of the previous cycle based on the read ADPCM code; and writing the ADPCM code.

[Effect]

In this invention, when recording, before sequentially writing each ADPCM code to the memory, the ADPCM code stored in the same address one cycle before is read out, and functions (Xn, Δn) necessary for decoding the ADPCM code are read. ), the current new ADPCM code is written to memory. When a recording stop command is input, the ADP is started based on the function (Xn, Δn) at that time and the ADPCM code of the next address in the memory, as in the conventional case.
The CM code is decoded to generate a reproduced signal.

[Embodiment] FIG. 7 is a block diagram of a recording/playback system for carrying out a method according to an embodiment of the present invention. The difference from the system of FIG. 5 is in the control circuit (41), Although the code structure itself is the same, the multiple timings at which control signals are sent out are different. Therefore, the data storage section (3
0) is used as is.

FIG. 8 is an explanatory diagram showing the operation of the above system, and FIG. 9 is a time chart thereof.

The memory (32) used in this embodiment is similar to that shown in the conventional example, and has a capacity that allows recording for hours. Address control of the memory (32) is performed when the address is "
It is configured so that it rises from 0 and returns to 0 again when it reaches a predetermined value (M in Figure 7), and repeats the cycle in a ring shape from a recording start command, and stops when a recording stop command is issued. (Address n in Figure 8). Then, when a recording stop command is issued, that is, playback starts, the process starts to proceed again from the address increased by "1" from the address where it stopped, and returns to rnJ after one cycle.

First, in the first cycle when recording starts, the MIC (11
), A M P (12), A M P (13) and L P F (14), the input signals are
After being converted into a digital value by ADC (15), ADPC
LO, Ll, L are ADPCM encoded by the M encoding circuit (17) and stored in the memory (32) via the input latch (16).
2... and so on. LM is stored at address M at the end of the first cycle. In addition, in this first cycle, the initial conditions necessary for ADPCM decoding XO,...
・.

Δ0... is not calculated and obtained by the ADPCM decoding circuit (2B)).

In the second cycle, first, the data LD at address "0"
is read from the memory (32) and the output latch (21)
The signal is sent to the ADPCM decoding circuit (2B) via the ADPCM decoding circuit (2B).

This ADPCM decoding circuit (2B) calculates and stores Xi and Δl using the above-mentioned decoding equations (1), (2), and (3), and holds them until the next cycle. and,
In the memory (32), the new ADPCM code LO input at that time is written to address "0".

When proceeding to the next address "1", the data L of the previous cycle
l is read from the memory (32), and X2 and Δ are read out again in the ADPCM decoding circuit (2B) in the same manner as above
2 is calculated, and the new ADPCM code L1° input at that time
is written.

These steps are repeated one after another, and the memory (32
) new ADPCM codes are written in order as the address numbers increase. At the same time, ADP
In the CM decoding circuit (2B), Xn and Δn from exactly one cycle before are always formed in an orderly manner and updated repeatedly. During this recording operation, Xn and Δn are D A C
(22) is not output and is simply held.

Next, an explanation will be given of the operation when recording is stopped at address rnJ of the Y-th cycle by a recording stop command and is played back.

The memory (3
2) ADPC code Lnv-1 of address n stored in
is read out, which is passed through the output latch (21) to the AD
The signal is sent to the PCM decoding circuit (26). This ADPC
The M decoding circuit (2B) calculates Xn and Δn from the above-mentioned decoding y- using equations (1), (2) and (3), holds it until the next cycle, and stores it in the memory (32). Then, the new ADPCM code LnY input at that time is written to address rnJ (see FIG. 9).

Thereafter, upon receiving the recording stop signal, the playback operation begins. Next, ADPCM at address (n+1) of memory (32)
The code (data from one cycle before) Ln÷1 is read out and sent to the ADPCM decoding circuit (2B) via the output latch (21). At this time, the DPCM decoding circuit (2B
), Y-I Y-1 Xn and Δn are held as shown in FIG. 9, and these XnY-
Applying IY-I Y-1 and Δn and L n+1, Y-I
While calculating and holding Y-1 is obtained.

In this way, when playback starts from address "n+1" after the address stops at rnJ due to the input of a recording stop command, Xn and Δn necessary for decoding the ADPCM code one cycle before are used for recording operation. obtained when
Since it is in a standby state, the appropriate ADPCM
A decoded signal is obtained, and the expected reproduced waveform is obtained.

[Effects of the Invention] As explained above, according to the present invention, in a recording/playback method that allows recording by cyclically writing data into a memory using ADPCM codes, and also allowing reverse playback by reading from the memory, Before writing a new ADPCM code to the memory, the ADPCM code from one cycle before is read from the memory, the function values necessary for ADPCM decoding are constantly calculated, and the recording is stopped until the next address is moved. When a command is input and the playback operation starts, ADPCM decoding can be performed using the function value that was put on standby. Therefore, since there is no need for a memory to store the function value in advance, the number of circuits constituting the system is not increased, and the expected reproduced waveform can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a flow chart showing the method of the present invention. Fig. 2 is a block diagram of a conventional recording/playback system using PCM codes, Fig. 3 is a block diagram showing details of the data storage section of Fig. 2, and Fig. 4 is an operation of the recording/playback system of Fig. 2. FIG. FIG. 5 is a block diagram of a conventional recording/playback system using ADPCM codes, and FIG. 6 is a playback waveform diagram of the recording/playback system of FIG. FIG. 7 shows an AD that implements a method according to an embodiment of the present invention.
A block diagram of a recording and reproducing system using PCM codes, FIG. 8 is an explanatory diagram showing its operation, and FIG. 9 is a time chart thereof. (lO)... Recording system, (17)... ADPCM encoding circuit (20)... Playback system, (27)... ADPC
M decoding circuit (30)...Data storage unit 4 Shudomoto Mitsuo's method Figure 1

Claims (1)

[Claims] (1) In a recording/playback method that allows recording by cyclically writing data into memory using ADPCM codes, reading the ADPCM codes from the memory, and replaying them backwards, there are , 1 from now
a step of reading the ADPCM code stored at the address before the cycle; a step of calculating a function value necessary for decoding the ADPCM code of the previous cycle based on the read ADPCM code; A recording/playback method using an ADPCM code, comprising the step of writing a current ADPCM code to an address.