JPH01196981A - Title picture inserting device - Google Patents

Abstract

PURPOSE:To improve the general-purpose application by controlling a write timing and a readout timing of a picture data to a memory means stored with a picture data being a title picture by a memory control means controlled externally. CONSTITUTION:A titler circuit 13 writes a picture data supplied to a memory control circuit 53 via a picture data input terminal 65 into a memory 14 by the operation of a 1st operation switch 31 and the picture data written in the memory 14 is read to a memory control circuit 53 when the operation of a 2nd operation switch 32 is accepted and the data is outputted as a title picture signal via a color designation circuit 54. Then the write timing and readout timing of the picture data to the memory 14 are controlled by an externally controllable memory control circuit 53. Thus, the general-purpose application in the video system with different write timing and read timing is enhanced.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B1 Overview of the invention C1 Prior art 9 Problems to be solved by the invention 80 Means for solving the problems F1 Effect G. Examples (G 1-1) Camera to which the present invention is applied integrated 8 wa
VTR configuration (Figures 2 and 3) (G 1-2) Titler circuit configuration (Figure 1) (Gl
-3) Operation of the titler circuit (Figure 1) (Gl-4) Specific configuration of variable delay (Figures 4 and 5) (G2) Application example H1 Effect of the invention A, Industrial application field Book The present invention relates to a title image insertion device that forms a title image signal and inserts it into a video signal, and more particularly to a title image insertion device used in so-called titlers, captioners, and the like.

B9 Summary of the Invention The present invention provides a title image insertion device for writing image data formed by digitizing an input video signal into a memory means, and inserting a title image signal formed by reading this image data from the memory means into a video signal. By making it possible to externally control the write timing and read timing of the image data to the memory means, the present invention has versatility for video systems having different write timings and read timings.

C1 Prior Art Conventionally, a title image insertion device such as a so-called titler or telopper forms an image signal of a title image such as title information or subtitle information according to the content of an image to be reproduced from a video signal and inserts the image signal into the video signal. is known as a peripheral device for video tape recorders (VTRs).

These titlers, captioners, etc. are equipped with a character generator, etc. that stores various character patterns, and insert the title image signal formed by the character generator into the input video signal supplied from the playback VTR, imaging device, etc. (so-called superimpose).

Further, in a camera-integrated VTR that includes an imaging section that captures an image of a subject and a recording section that records a video signal formed from the imaging output obtained from the imaging section, the image captured by the imaging section may be The luminance signal ('Y) is separated from the video signal with a low-pass filter, and the image data obtained by digitizing this luminance signal (Y) using an analog-to-digital (A/D) conversion circuit is written into memory. , a device incorporating a title image insertion device that forms a title image signal from image data read from this memory and inserts it into a video signal is disclosed in Japanese Patent Application No. 62-094.
It was proposed and used in the specification and drawings of No. 682.

This title image insertion device performs image signal processing using the synchronization signal supplied to the imaging section as a reference synchronization signal. However, in this title image insertion device, when writing the image data to the memory, the image data supplied to the memory passes through a low-pass filter, an A/D conversion circuit, etc., so the timing is more constant than the reference synchronization signal. There will be a time delay. Therefore, in this title image insertion device, the write timing of the memory is controlled by delaying the reference synchronization signal by a certain period of time so that the write timing of the memory coincides with the timing of the image data. There is. Further, in this title image insertion device, when reading the image data from the memory, the synchronization of the title image signal formed from this image data is made to match the synchronization of the video signal into which this title image signal is inserted. , the reference synchronization signal is delayed by a certain period of time to control the read timing of the memory.

D1 Problems to be Solved by the Invention By the way, the above-mentioned title image insertion device is composed of a memory for storing image data and its control +BIC, etc.
Used in various video systems.

However, with conventional title image insertion devices, even if it is attempted to realize all of the title image insertion devices used in these various video systems with the same IC, the image of the low-pass filter, A/D conversion circuit, etc. used in each system cannot be realized. Since the delay times of the signal processing circuits are different, the writing timing and reading timing of image data to the memory do not match, making it impossible.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a title image insertion device with a novel configuration that has versatility for video systems with different timings for writing and reading image data from memory. .

81 Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides means for digitizing an input video signal to form image data, memory means for storing the image data, and memory means for storing the image data. means for forming a title image signal from image data read from the memory means; means for inserting the title image signal into the input video signal; and memory control means capable of externally controlling the writing timing and reading timing of the image data with respect to the memory means. Consisting of

F0 operation In the title image insertion device according to the present invention, the externally controllable memory control means controls the writing timing and reading timing of the image data to the memory means in which the image data to be the title image is stored. Ru.

G. Examples Examples of the present invention will now be described in detail with reference to the drawings.

(G 1-1) 8 mm integrated camera to which the present invention is applied
Configuration of VTR (Figures 2 and 3) Figures 2 and 3 show the imaging unit lO
and a recording section 20 that records the video signal obtained by the imaging section 10 in a predetermined format of 8 mm video are integrally provided in the main body 30 of the NTSC camera with a built-in title image insertion device. This shows R.

As shown in the external perspective view of FIG. 3, the apparatus main body 30 is provided with an imaging lens 35 that guides imaging light to the solid-state imager l of the I-most image section 10, and also An electronic viewfinder 40 for monitoring the image of the subject being photographed, various operation switches 31,
32, 33, etc. are provided.

Furthermore, as shown in the block diagram of FIG. It is driven by a COD drive circuit 3 that operates based on a signal, and supplies an imaging output of a subject image obtained by the solid-state imager 1 to an imaging processing signal circuit 4.

The imaging signal processing circuit 4 forms a luminance signal (Y) and color difference signals (RY) and (B-Y) representing a subject image from the imaging output from the solid-state imager 1. A luminance signal (Y) and a color difference signal (R
-Y) and (B-Y) are impose circuits 5 and 6, respectively.
．． 7 to an NTSC encoder 8.

The NTSC encoder 8 generates an NTSC encoder that indicates a subject image from the luminance signal (Y), color difference signals (RY), and (B-Y).
Forms an SC video signal. The video signal formed by this NTSC encoder 8 is supplied to a 1-bit analog/digital (A/D) conversion circuit 12 via a low pass filter (LPF) 11 for separating the luminance signal (Y). At the same time, it is supplied to the electronic viewfinder 40 and the recording section 20 that performs a recording operation in a predetermined format of 8ma+video.

The above-mentioned 1-bit A/D conversion circuit 12 is the above-mentioned PFII
It consists of a level comparator that compares the luminance signal (Y) of the video signal separated by a predetermined signal level,
When the level of the luminance signal (Y) is higher than the predetermined signal level, it is indicated as "0", and when it is smaller, it is indicated as "1".
Form the image data shown in . This A/D conversion circuit 1
The image data formed in step 2 is written into a memory 14 via a titler circuit 13.

The memory 14 is composed of a static RAM that stores the image data formed by the A/D conversion circuit 12, and is configured so that the data will not be lost even if the main power is cut off. Backup power is supplied from a lithium battery 15. Furthermore, this lithium battery 1
5 is monitored by a voltage drop detection circuit (not shown), and a warning is displayed in the electronic viewfinder 40 before the backup function of the memory 14 is lost.

The titler circuit 13 is supplied with a synchronization signal from the synchronization signal generation circuit 2, forms write/read address data for the memory 4 from this synchronization signal, and controls writing/reading of image data to/from the memory 14. conduct. Further, this titler circuit 13 supplies three primary color signals (R, G, B) that become a title image to a conversion circuit 16, and also supplies each of the above-mentioned impose circuits 5, 6 according to the image data read out from the above-mentioned memory 14. It is designed to perform motion control of 7 degrees.

The conversion circuit 15 converts the three primary color signals (R, G, B) supplied from the titler circuit 13 into a luminance signal (Y) and color difference signals (RY) and (B-Y), The signal is supplied to each impose circuit 5, 6.7.

These impose circuits 5, 6.7, under the operation control of the titler circuit 13, receive a luminance signal (Y) and a color difference signal (R-Y) supplied from the kojikan circuit 15, (
B-Y) is inserted into the output signal of the imaging signal processing circuit 4.

(Gl-2) Structure of Titler Circuit (FIG. 1) FIG. 1 is a circuit diagram showing the structure of the titler circuit 13. As shown in FIG.

In FIG. 1, the titler circuit 13 has a first
．． Second variable delay 51W, 51R.

1st. It is composed of second sequencers 52W and 52R, a memory control circuit 53, a color designation circuit 54, and the like.

Among these, the first variable delay 51W has input terminals for each signal as a horizontal synchronization input terminal 61h and a clock input terminal 6.
2, a data input terminal of a predetermined bit is connected to a delay data input terminal group 63, and an output terminal is connected to the memory control circuit 53 via the first sequencer 52W. Further, the input terminal of the second variable delay 51R for each signal is the horizontal synchronization input terminal 6.
1h and the clock input terminal 62, and the data input terminal of a predetermined bit is connected to the delay data input terminal group 6.
4, and the output end is connected to the second sequencer 5.
It is connected to the memory control circuit 53 via 2R. The delay data input terminal groups 63 and 64 are connected to the variable delay data input terminals 51 and 51 from the system controller (not shown).
Data for setting the amount of delay for W and 51R is supplied. Further, a horizontal synchronization signal is supplied from the synchronization signal generation circuit 2 to the horizontal synchronization input terminal 61h. In addition, the clock input terminal 62
is supplied with a clock signal having a predetermined frequency.

The memory control circuit 53 has input terminals connected to an image data input terminal 65 and a vertical synchronization input terminal 61v, and an output terminal for image data connected to the color specifying circuit 54, as well as to the memory 14. , the image data input/output terminal is connected via the image data input/output terminal 70, the address data output terminal of a predetermined bit is connected via the address data output terminal group 71, and the control data output terminal for writing/reading instructions etc. is controlled. They are connected via a data output terminal group 72. Note that a vertical synchronization signal is supplied from the synchronization signal generation circuit 2 to the vertical synchronization input terminal 61v.

The color designation circuit 54 is connected to color designation input terminals 66, 67, and 68 connected to a system controller (not shown), as well as color signal output terminals 73 and 74 for the three primary color signals (R, G, and B). 75 are connected to each other. A system controller (not shown) connected to each of the color designation input terminals 66, 67, and 68 is connected to the third operation switch 33 provided in the device main body 30, and the color designation data is inputted to the color designation circuit 54. It is designed to supply

The titler circuit 13 also includes the device main body 30.
A registration operation designation input terminal 76 to which the first operation switch 31 disposed in the input terminal 76 is connected, and an insertion operation designation input terminal 77 to which the second operation switch 32 is connected are provided. In addition, an input terminal 78 for a drive power source, a ground terminal 79, and the like are provided.

(G1-3) Operation of the titler circuit (Fig. 1) The titler circuit 13 is operated by the panel 100 in the image pickup section 10.
When a registration operation is specified by operating the first operation switch 31 while photographing arbitrary characters, illustrations, etc. drawn on the screen, the data is sent to the memory control circuit from the A/D conversion circuit 12 via the image data input terminal 65. A registration operation is performed to write the image data supplied to the memory 14 into the memory 14.

At this time, the memory control circuit 53 receives the vertical synchronization signal supplied via the vertical synchronization input terminal 61v, the horizontal synchronization input terminal 61h, the first variable delay 51W, and the first sequencer 52W. Write address data for the image data is generated based on the horizontal synchronization signal and is supplied to the memory 14.

Here, the first variable delay 51W receives a horizontal synchronization signal supplied from the horizontal synchronization input terminal 61h so that the memory restriction circuit 53 generates address data synchronized with the writing timing of image data. , and is delayed for a predetermined time set by the delay amount setting data supplied from the delay data input terminal group 63. In other words, the first variable delay 51W delays the horizontal synchronizing signal supplied to the memory control circuit 53 by the same amount of time as the delay of the image data caused by the LPF 11, A/D conversion circuit 12, etc. , the write address data of the memory 14 is delayed. Further, the first sequencer 52W supplies the horizontal synchronization signal output from the first variable delay 51W to the memory control circuit 53 when this registration operation is specified. By using the variable delay 51W, the titler circuit 13 can arbitrarily set the delay time of the horizontal synchronization signal using the delay amount setting data supplied from the delay data input terminal group 63. This can easily be applied to video systems with different delay times.

Therefore, according to this registration operation, this titler circuit 13
The image data supplied to the memory 14 is written to the address of the memory 14 specified by the address data whose timing matches the image data.

In addition to the characters and illustrations drawn on the panel, the image data of the title image written to the memory 14 includes
For example, it is possible to take images of landscapes, people's faces, etc. and create them without being paid.

Further, when the titler circuit engineer 3 accepts the operation of the second operation switch 32, it reads out the image data written in the memory 14 by the registration operation to the memory control circuit 53, and controls the memory. An insertion operation is performed in which the circuit 53 outputs the title image signal via the color designation circuit 54. At this time, the memory control circuit 53
is the vertical synchronization signal supplied from the synchronization signal generation circuit 2 via the vertical synchronization input terminal 61v, and the above-mentioned signal via the horizontal synchronization input terminal 61h, the second variable delay 51R, and the second sequencer 52R. Based on the horizontal synchronization signal supplied from the synchronization signal generation circuit 2, read address data for the image data is generated and supplied to the memory 14.

Here, the second variable delay 51R applies a predetermined delay specified by the delay amount setting data supplied from the delay data input terminal group 64 to the horizontal synchronization signal supplied from the horizontal synchronization input terminal 61h. A horizontal synchronization signal is generated so that the timing of the title image signal supplied to the impose circuits 5, 6, and 7 coincides with the horizontal synchronization of the output signal of the imaging signal processing circuit 4. It has become. In other words, the second variable delay 51R delays the horizontal synchronizing signal to control the readout timing of image data to the memory 14, so that the image signal processing circuit This is to synchronize the title image signal to be inserted into the output signal of No. 4. By using the variable delay 51R, the titler circuit 13 can arbitrarily set the delay time of the horizontal synchronizing signal using the delay amount setting data supplied from the delay data input terminal group 64. This can easily be applied to video systems with different delay times.

The image data read from the memory 14 is supplied to the color designation circuit 54, and each color designation input terminal 66.
The three primary color signals (R, G, B) specified by the color specification data given to 61.68 are output as title image signals from the above color signal output terminals 73.74.75 to the above conversion circuits 16 to the above respective inputs. The signal is supplied to the pause circuits 5, 6.7, and inserted into the output signal of the image signal processing circuit 4.

In this way, according to this insertion operation, it is possible to insert into the video signal output from the image pickup signal processing circuit 4 a title image signal formed from image data synchronized with this video signal.

By this insertion operation, the title image signal output from the titler circuit 13 is converted into three primary color signals (R, G, B) according to the operation of the third operation switch 33.
The combinations are specified cyclically.

At this time, the designated color is displayed in the electronic viewfinder 40 in the form of letters or the like. Further, the color designation of the title image can be performed even when the insertion operation is designated by operating the second operation switch 32.

(Gl-4) Specific configuration of variable delay (FIGS. 4 and 5) Here, the above 1. Second variable delay 51W.

51R is the load input terminal (LOA) as shown in FIG.
A horizontal synchronizing signal is supplied to the clock input terminal (CL
It is possible to use a counter 80 configured such that a predetermined clock is supplied to K) and delay amount setting data is supplied to preset data input terminals CPI to Pn). This counter 80 is connected to the load input terminal (LOAD)
The delay amount setting data is preset to the value indicated by the delay amount setting data supplied to the preset data input terminals (PI to Pn) every horizontal opening period by the horizontal synchronization signal supplied to the preset data input terminals (PI to Pn). This counter 80 has a clock input terminal (C
Counting is performed at the timing of a predetermined clock supplied to LK), and when the count reaches a predetermined value (for example, 0), a pulse is output from the carry output terminal (CARRY). Therefore, this counter 80 can output from the carry output terminal (CARRY) a horizontal synchronization signal delayed by the delay amount set by the delay amount setting data supplied to the preset data input terminals (CPI to Pn). .

Alternatively, the above 1. Second variable delay 51W, 51
As shown in FIG. 5, R represents the shift register 90 and each data output terminal (Q1-Qm
) and a selector 91 connected to the selector 91. In this FIG. 5, the shift register 9
0 shifts the horizontal synchronization signal supplied to the data input terminal (DIN) at the timing of a predetermined clock supplied to the clock input terminal (CLK), and outputs each data output terminal (Q
l to Qm). Further, the selector 91 is
The data output terminal of the shift register 90 specified by the select data supplied to the select data input terminal (SL-3n) is connected to the data output terminal CD0UT).

Therefore, by supplying data for setting the delay amount to the select data input terminal (S1=Sn), the horizontal synchronization signal delayed by this delay amount is sent to the data output terminal (DO).
It can be output from UT).

(G2) Application example The titler circuit 13 can also be configured to convert the image data supplied from the A/D conversion circuit 12 into parallel data and supply it to the memory 14. Further, in the above embodiment, the present invention is applied to a camera-integrated VTR with a built-in title image insertion device, but for example, an image of an input video signal supplied from a playback side VTR etc. is stored in a memory, and this image data is The present invention can also be applied to a title image insertion device used in a stationary titler, captioner, etc. that forms a title image signal and inserts it into an input video signal.

H6 Effects of the Invention In the present invention, an externally controllable memory control means controls the writing timing and reading timing of the image data to the memory means in which the image data serving as the title image is stored. Therefore, the title image insertion device according to the present invention externally controls the write timing and read timing of the image data to the memory means in which the image data serving as the title image is stored, thereby inserting the image data into the memory means. Good writing and reading can be performed, and versatility can be provided for video systems having different writing timings and reading timings.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of a titler circuit of a camera-integrated VTR to which the present invention is applied, FIG. 2 is a block diagram showing the configuration of the camera-integrated VTR, and FIG. FIG. 4 is a circuit diagram showing a specific example of a variable delay using the titler circuit 9, and FIG. 5 is a circuit diagram showing another specific example of the variable delay. 5.6.7...Impose circuit 11...Low pass filter 12...A/D conversion circuit 13...Titler circuit 14...Memory 51W, 51R...Variable delay 53...Memory control circuit

Claims (1)

[Scope of Claims] Means for digitizing an input video signal to form image data; memory means for storing said image data; means for forming a title image signal from image data read from said memory means; A title image insertion device comprising: means for inserting a title image signal into an input video signal; and a memory control means capable of externally controlling the writing timing and reading timing of image data to the memory means.