JPH01194886A - Driving unit for brushless motor - Google Patents

Abstract

PURPOSE:To detect the induced voltage of stator windings at a high speed and exactly, and enable a position detecting signal to be obtained, and enhance response property to sudden speed fluctuation, by using a logic means through the position detecting signal, and by avoiding spike-formed voltage component. CONSTITUTION:From induced voltage induced in stator windings 38U, 38V, 38W of the plural phases of a brushless motor 37, position detecting signal is obtained by a voltage dividing circuit 40, a differential amplifying means 49, a reference voltage signal generating means 79, and a comparing means 56. After the input of the position detecting signal to a logic means 72 and a delay means 63 is provided and spikeformed voltage component is avoided, input to a control circuit 78 is provided. By the control circuit 78, transistors 25-28 of an output circuit 24 are turned ON in order, and current conduction to the stator windings 38U, 38V, 38W of the brushless motor 37 is controlled.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention (Industrial Application Field) The present invention relates to a brushless motor drive device that obtains a position detection signal based on an induced voltage induced in a stator winding.

(Prior art) In a brushless motor, the relative position between the stator winding and the permanent magnet rotor is determined using the induced voltage induced in the stator winding, without using a position detection element such as a Hall element. Increasingly, detection methods are being adopted.

This conventional example is shown in FIG. That is, 1 is a DC power supply, and 2 is a stator winding 3U of the brushless motor 3.

Inverter circuit for energizing 3V and 3W, 4.5
and 6 are filter circuits that phase-shift the induced voltages UV, VV, and VW induced in the stator windings 3U, 3V, and 3W by 90 degrees, and 7 is a filter circuit that calculates the neutral point voltage NV from the output signals of these filter circuits 4 to 6. 8, 9 and 10 are comparators that compare the output signals of the filter circuits 4.5 and 6 with the neutral point voltage NV, respectively. 11 is a control circuit. FIG. 5 is a time chart showing the operation of the conventional example, and now, referring to this chart, let us consider the U phase. The induced voltage UV induced in the stator winding 3U (see FIG. 5(a)) includes a spike-like voltage component generated by conduction of the paired arm freewheeling diode during commutation of the inverter circuit 2. In order to eliminate the influence of this spike-like voltage component, the phase of the induced voltage UV is shifted by 90 degrees by the filter circuit 4 to obtain a phase-shifted voltage DυV as shown in FIG. 5(b).

Thereafter, this phase shift voltage DUV and the neutral point voltage NV shown in FIG. 5(b) are compared by a comparator 8 to obtain a position detection signal PSU as shown in FIG. 5(c). The same goes for the other V and W phases, and position detection signals PSV and PSW are obtained from the comparators 9 and 10 as shown in FIGS. 5(d) and (e) based on the induced voltages V and WV. These position detection signals PSU, PSV, and PSW are signals with a 180-degree main conduction phase and a 20-degree phase difference, and when these are given to the control circuit 11, the control circuit 11 outputs six energization timing signals to control the inverter. It is applied to the base of the transistor which is the switching element of circuit 2.

(Problems to be Solved by the Invention) In the conventional configuration, filter circuits 4 to 6 having phase characteristics delayed by 90 degrees are provided in order to remove spike-like voltage components included in the induced voltages UV, VV, and WV. Therefore, the time constants of filter circuits 4 to 6 are large, and therefore,
There is a problem that rapid speed fluctuations cannot be followed, and there is also a problem that position detection in a low speed region is difficult. Furthermore, the magnitude of the spike-like voltage components included in the induced voltages UV, VV, and Wv varies depending on the current of the stator windings 3U, 3V, and 3W, that is, the magnitude of the load, so if the load fluctuation is large, the filter circuit A phase error occurs in the signal waveforms from 4 to 6 onwards, making it impossible to operate over a wide range, and therefore, there is a problem in that the application is limited to compressors with small load fluctuations.

In order to solve this problem, Japanese Unexamined Patent Publication No. 61-1
The one disclosed in Japanese Patent No. 70290 is being considered. This is done by inserting an impedance element between the transistor (commutating element) and the stator winding (drive winding).
A bridge circuit is constructed in which one side is the winding between two arbitrary terminals of the stator winding, and a position detection signal is obtained by a differential amplifier circuit that detects the potential difference between two vertices of this bridge circuit. However, in such a configuration, when a large current (for example, several tens of amperes) flows, such as in a small brushless motor, the impedance element inserted between the transistor and the stator winding generates a large amount of heat. In addition, since the current change with respect to time is small even in the low speed region, the problem of difficulty in position detection in the low speed region remains unresolved.

The present invention has been made in view of the above circumstances, and its purpose is to control the energization of the stator winding based on the induced voltage of the stator winding. It is possible to obtain a position detection signal by detecting the It is an object of the present invention to provide a brushless motor drive device which can obtain a position detection signal and is free from the problem of large heat generation of an impedance element.

[Structure of the Invention] (Means for Solving the Problems) A brushless motor drive device of the present invention divides induced voltages induced in stator windings of multiple phases in response to rotation of a permanent magnet rotor. a voltage dividing circuit for generating a voltage, a differential amplifying means for detecting a potential difference between any two phases of the divided voltage signals of each phase by the voltage dividing circuit, and a reference voltage signal generating means for generating a reference voltage signal; Comparing means for comparing the reference voltage signal of the reference voltage signal generating means and the output signal of the differential amplifying means is provided, and delay means is provided for delaying the output signal of the comparing means, and the output signal of the delay means and the output signal of the differential amplifying means are provided. A logic means for processing the output signal of the comparison means and outputting a position detection signal is provided, a control circuit is provided for outputting an energization timing signal based on the position detection signal from the logic means, and The present invention is characterized in that it includes an output circuit that controls energization of the stator winding based on a energization timing signal.

The reference voltage signal generation means includes a differential amplification means for detecting the difference between the voltage applied to the brushless motor and a voltage proportional to the rotation speed of the brushless motor, and an output signal of the differential amplification means for detecting the difference between the voltage applied to the brushless motor and the voltage proportional to the rotation speed of the brushless motor. It is preferable to include a switching means for switching between positive and negative based on the position detection signal.

(effect) A voltage divider circuit for the induced voltage induced in the stator winding.

A position detection signal containing a spike-like voltage component is obtained by processing by the differential amplification means, the reference voltage signal generation means, and the comparison means, and the spike-like voltage component of this position detection signal is processed by the delay means and logic. A position detection signal is obtained which is removed by the means and applied to the control circuit. Therefore, there is no need to provide a filter circuit with a large time constant as in the conventional case, so response can be improved and rapid speed fluctuations can be avoided.

It is possible to perform high-speed position detection even in response to current changes in the stator winding, that is, load fluctuations, and there is no need to insert an impedance element between the stator winding and the output circuit. There will be no problem with heat generation.

In addition, the value of the reference voltage signal from the jA quasi-voltage signal generating means changes depending on the voltage applied to the brushless motor, that is, the DC power supply type J) and the rotation speed of the brushless motor. Even if the rotational speed of the brushless motor decreases when a load is applied and the current increases, and the induced voltage decreases accordingly, the detection timing of the position detection signal will not be delayed, and the maximum The resulting phase can be controlled and efficiently operated.

(Embodiment) An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

First, the overall configuration will be described according to FIGS. 1 and 2. Reference numeral 21 denotes a voltage-adjustable DC power supply, the positive and negative terminals of which are connected to busbars 22 and 23, with busbar 23 being grounded. 24 is an inverter circuit which is an output circuit, and NPN type transistors 25 to 27 and 28 to 3 which are switching elements are connected between bus lines 22 and 23.
0 connected in a three-phase bridge. Note that 31 to 36 are diodes connected in parallel to the transistors 25 to 30. 37 is a brushless motor, which includes a stator 38 having U, V and W phase stator windings 38U, 38V and 38W, and a permanent magnet rotor 39.
It is equipped with One terminal of the stator windings 38U, 38V and 38W is connected in common, and each other terminal is an output terminal OU, which is a common connection point of the transistors 25 and 28.
They are connected to an output terminal OV, which is a common connection point of transistors 26 and 29, and an output terminal OW, which is a common connection point of transistors 27 and 30, respectively. 4o is a voltage divider circuit, which consists of a series circuit of resistors 41 and 42, 2 resistors 43 and 44, between the output terminals OU, OV, and OW and the bus bar 23.
and a series circuit of resistors 45 and 46 are connected, and the resistors 41 and 42 . The common connection points of resistors 43 and 44 and resistors 45 and 46 are connected to output terminals 40U and 40
V and 40W. 47 is a buffer circuit;
This is an operational amplifier 48U with tJ, V and W soma.

48V and 48W, each non-inverting input terminal is connected to the output terminals 40U, 40V and 40W, respectively, and each inverting input terminal is connected to its own output terminal, respectively. 4
Reference numeral 9 denotes differential amplification means, which, as shown in FIG. 2, consists of differential amplification circuits 50U, 50V and 50W with U, V and W soma.

The U-phase differential amplifier circuit 50U includes resistors 51U, 52U,
53U, 54U and an operational amplifier 55U, a resistor 53U is connected between the inverting input terminal and the output terminal of the operational amplifier 55U, and the non-inverting input terminal of the operational amplifier 55U is grounded via a resistor 54U. It is composed of The other V and W soma differential amplifier circuits 50V and 50W have the same configuration, and the differential amplifier circuit 50
The same parts as U are shown with suffixes V and W added instead of the suffix U. The inverting input terminal of the operational amplifier 55U and the non-inverting input terminal of the operational amplifier 55W are connected to the output terminal of the U-soma operational amplifier 48U via resistors 51U and 52W, respectively, and the inverting input terminal of the operational amplifier 55V and the non-inverting input terminal of the operational amplifier 55W are The non-inverting input terminals of 55U each have a resistor of 51
The inverting input terminal of the operational amplifier 55W and the non-inverting input terminal of the operational amplifier 55V are connected to the output terminal of the operational amplifier 48V of the W soma through resistors 51W and 52V, respectively. is connected to the output terminal of Reference numeral 56 denotes a comparison means, which, as shown in FIG.
It consists of 7U, 57V and 57W. U Soma comparison circuit 5
7U is 1. Comparator 58U, photocoupler 59U, resistor 6
0U and 61U, the output terminal of the comparator 58U is connected to the bus 62 to which DC voltage VC1 is applied via the light emitting diode 59Ua of the photocoupler 59U and the resistor 60U.
The resistor 61U and the collector and emitter of the phototransistor 59Ub of the photocoupler 59U are connected in series between the bus 622 connected to the bus 622 to which the DC voltage vc2 is applied and the ground. The other V and W soma comparison circuits 57V and 57W have the same configuration, and the same parts as the comparison circuit 57U are shown with suffixes V and W added instead of the suffix U to their reference numerals. And comparator 58U.

Each inverting input terminal of 58V and 58W is an operational amplifier 55U.
, 55V and 55W output terminals, respectively.

63 is a delay means, which, as shown in FIG.
U, V and W Soma delay circuit 64U, 64V and 64W
Consisting of The U-soma delay circuit 64U is an inverter 65
U and 66U.

Consisting of resistors 67U and 68U, inverters 69U and 70U, and capacitor 71U; inverters 65U and 66U, resistors 67U and 68U, and inverter 69U.
and 70U are connected in series, and a capacitor 71U is connected in parallel to a series circuit of an inverter 66U and a resistor 67U. Other V and W soma delay circuits 6
4V and 64W have the same configuration, and the same parts as the delay circuit 64U are shown with suffixes V and W in place of the suffix U. The input terminal of the U-soma inverter 65U is connected to the collector of the phototransistor 59Ub,
(2) The input terminal of the soma inverter 65V is connected to the collector of the phototransistor 59Vb, and the input terminal of the W soma inverter 65W is connected to the collector of the phototransistor 59Wb. 72 is a logic means, which, as shown in FIG. 2, consists of logic circuits 73U, 73V and 73W of U, V and W soma. The U-soma logic circuit 73U consists of an inverter 74U and D-type flip-flop circuits 75U, 76U, and 77U, and the reset input terminal R and data input terminal of each flip-flop circuit 75U, 76U, and 77U are grounded, and the flip-flop circuits 75U, 76U, and 77U are grounded. The reset output terminal Q of the circuit 75U is connected to the clock input terminal C of the flip-flop circuit 77U, and the reset output terminal 0 of the flip-flop circuit 76U is connected to the set input terminal S of the flip-flop circuit 77U. The clock input terminal C of the inverter circuit 74U is connected to the output terminal of the inverter circuit 74U. The other V and W soma logic circuits 73V and 73W have the same configuration, and the same parts as the logic circuit 73U are indicated by the same reference numerals with suffixes V and W added instead of the suffix U.

In the U-soma logic circuit 73U, the clock input terminal C of the flip-flop circuit 75U and the input terminal of the inverter 74U are connected to the collector of the phototransistor 59Ub, and the set input terminal S of the flip-flop circuit 75U is connected to the V-soma delay circuit. The set input terminal S of the flip-flop circuit 76U is connected to the output terminal of the inverter 69V at the delay circuit 64V. Also,■
In the Soma logic circuit 73V, the clock input terminal C of the flip-flop circuit 75V and the input terminal of the inverter 74V are connected to the collector of the phototransistor 59vb, and the set input terminal S of the flip-flop circuit 75V is connected to the collector of the phototransistor 59vb.
is connected to the output terminal of the inverter 70W in the W Soma delay circuit 64W, and the set input terminal S of the flip-flop circuit 76V is connected to the output terminal of the inverter 69W in the delay circuit 64W. Further, in the W-soma logic circuit 73W, the clock input terminal C of the flip-flop circuit 75W and the input terminal of the inverter 74W are connected to the collector of the phototransistor 59Wb, and the set input terminal S of the flip-flop circuit 75W is connected to the U-soma delay circuit. The set input terminal S of the flip-flop circuit 76W is connected to the output terminal of the inverter 69U in the delay circuit 64U. Therefore, each U.

The reset output terminals 0 of the flip-flop circuits 77U, 77■, and 77W of the ■ and W Soma are connected to the three input terminals of the control circuit 78, and the six output terminals of the control circuit 78 are connected to the transistors in the inverter circuit 24. Connected to 25 to 30 bases. Now, 79 is a reference voltage generating means, which will be described below. That is, 8
0 is a voltage dividing circuit, which is constructed by connecting resistors 81 and 82 in series between the bus bar 22 and the ground.

83 is a voltage detection circuit, which, as shown in FIG. 2, consists of operational amplifiers 84 and 85 and resistors 86 and 87; The output terminal is connected to the non-inverting input terminal of the operational amplifier 85, and the output terminal of the operational amplifier 85 is grounded through a resistor 86.87 in series, and the common connection point of the resistors 86.87 is connected to the operational amplifier 85.
It is configured by being connected to the inverting input terminal of. and,
A non-inverting input terminal of an operational amplifier 84 in this voltage detection circuit 83 is connected to a resistor 80 which is a detection terminal in a voltage dividing circuit 79.
．． 81 common connection points. Reference numeral 88 denotes differential amplification means, which, as shown in FIG.
A non-inverting input terminal of the operational amplifier 93 is grounded via a resistor 92. In this operational amplifier 93, an inverting input terminal is connected to an output terminal of an operational amplifier 85 via a resistor 89, and a non-inverting input terminal is connected to a control terminal of a control circuit 78 which outputs a signal as described later. . Reference numeral 94 denotes a switching means, which, as shown in FIG.
It consists of 5V and 95W. The U Soma switching circuit 95U is
Consisting of resistors 96U, 97U, 98U, operational amplifier 99U, and analog switch 100U, in operational amplifier 99U, the inverting input terminal and non-inverting input terminal are connected to resistor 96U.
and 97U to the output terminal of the operational amplifier 93, and the non-inverting input terminal is grounded via the analog switch 100U. The other V and W soma switching circuits 95V and 95W have the same configuration, and the same parts as the U soma switching circuit 95U are indicated with suffixes V and W instead of the suffix U. In the U-soma switching circuit 95U, the output terminal of the operational amplifier 99U is connected to the non-inverting input terminal of the comparator 58U in the U-soma comparison circuit 57U, and the gate terminal of the analog switch 100U is connected to the W-soma logic circuit. It is connected to the reset output terminal 0 of the flip-flop circuit 77W in 73W. Also, in the Soma switching circuit 95V, the operational amplifier 9
The 9V output terminal is connected to the non-inverting input terminal of the comparator 58V in the V Soma comparison circuit 57V, and the gate terminal of the analog switch 100V is connected to the reset output terminal Q of the flip-flop circuit 77U in the U Soma logic circuit 73U.
L is connected. Furthermore, W Soma switching circuit 95W
, the output terminal of the operational amplifier 99W is connected to the non-inverting input terminal of the comparison circuit 558W in the W Soma comparison circuit 57W, and the gate terminal of the analog switch 100W is connected to the gate terminal of the analog switch 100W.
Flip-flop circuit 7 in Soma logic circuit 73V
Connected to 7V reset output terminal 0.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG.

During the rotation of the rotor 39, induced voltages UV, VV, and WV, which are voltage signals, are induced in each stator winding 38U, 38V, and 38W, and these are divided by the voltage dividing circuit 40 to generate TTL (
Transistor transistor logic) level is lowered to the output terminal 40U.

Figure 3 (a), (b) and (e) from 40V and 40W
As shown in FIG.
Furthermore, the divided voltage induced voltages UVa and VVa of the U and V soma are outputted as WVa and WVa.
It is applied to the U-soma differential amplifier circuit 50U via 8V,
The divided voltages VVa and WVa of the and W soma are passed through the operational amplifiers 48V and 48W to the differential amplifier circuit 5 of the V soma.
0V, and the divided induced voltages WVa and UVa of the W and U soma are given to the differential amplifier circuit 50W of the W soma via operational amplifiers 548W and 48U.
, V and W soma differential amplifier circuits 50U, 50V and 50
W is a differential voltage output signal 550U as shown in FIGS. 3(d), (e) and (f).

Outputs 550V and 550W. These differential voltage output signals 550U, 550V and 550W are input to comparison circuits 57U, 57V and 57W. The comparison circuits 57U, 57V and 57W are supplied with a reference voltage signal 595 in advance from the switching circuits 95U, 95V and 95W as described later.
U, 595V and 595W [see Figures 3(d), (e) and (f)] are given. Therefore, the comparison circuit 57
U, 57■ and 57W are reference voltage signals 595U, 595
FIG. 3(g) compares V and 595W with differential voltage output signals 550U, 55QV and 550W, respectively.

High level comparison detection signal 55 shown in (h) and (i)
Outputs 7U, 557V and 557W.

Now, these comparison detection signals (position detection signals) S57U
, 557V and 557W are the partial voltage induced voltages UVa, VVa
and the spike-like voltage component of WVa (this is caused by the freewheeling diodes 31 to 3 for the arm during commutation of the inverter circuit 24
This occurs when any one of 6 becomes conductive. ), so it needs to be removed. First, when a comparison detection signal 557V is given to the Soma delay circuit 64V, the inverter 70V of the delay circuit 64V outputs a high-level delayed output signal 570V as shown in FIG. It is applied to the set input terminal S of the flip-flop circuit 75U in the circuit 73U. The flip-flop circuit 75U is configured so that a comparison detection signal 557U is applied to its clock input terminal C, and reads the contents of the data input terminal, that is, the low level, when the comparison detection signal 557U rises from a low level to a high level.
The delay output signal 570V is repeatedly set from the low level to the rise of the noise level, and as a result,
A high level output signal 575U as shown in FIG. 3(k) is output from the reset output terminal 0. Therefore, this output signal 575U is from the low level of the comparison detection signal 557U! - This means that the rise to the level has been detected. or,
The inverter 69V in the delay circuit 64V outputs an output signal obtained by inverting the delayed output signal 870v, and applies it to the set input terminal S of the flip-flop circuit 76U in the U-soma logic circuit 73U. This flip-flop circuit 7
6U is configured such that a signal obtained by inverting the comparison detection signal 557U is applied to the clock input terminal C, and operates in the same manner as the flip-flop circuit 75U, and as a result, from the reset output terminal 0 to the signal shown in FIG. ), a high-level output signal 576U is output.Therefore, this output signal 576U is a signal obtained by detecting the fall of the comparison detection signal 357U from high level to low level.These output signals 575U and 576U is applied to the clock input terminal C and set input terminal S of the flip-flop circuit 77U, respectively, and the flip-flop circuit 77U is connected to the flip-flop circuit 75U.
As a result, a high-level position detection signal PSU as shown in FIG. 3(m) is output from the reset output terminal. This position detection signal PSU
When compared with the comparison detection signal 557U, the spike-like voltage component of the comparison detection signal 557H is removed from the position detection signal PSU.

In this case, since the flip-flop circuits 75U and 76U detect the rise and fall of the comparison detection signal 557U, chattering that may occur in the comparison circuit 57U can also be removed.

Although the above-L describes the operation of the U-soma logic circuit 73U, other V- and W-soma logic circuits 73V
The operating principle of 73W and 73W is also the same as that of logic circuit 73U,
As a result, position detection signals PSV and PSW as shown in FIGS. 3(n) and 3(o) are output from each reset output terminal 0 of flip-flop circuits 78V and 78W in logic circuits 73V and 73W. Therefore,
Induced voltages UV, VV and WV, ie, divided voltage induced voltage UVa.

It is possible to obtain position detection signals PSU, PSV and PSW which are energized through 180 degrees and have different phases by 120 degrees from VVa and WVa. These position detection signals PSU, PSV, and PSW are given to the control circuit 78, and the control circuit 78 uses the signals in FIGS. 3(p) and (Q
), (r).

Energization timing signals TUa, TUb, TVa, TVb, TWa and TW as shown in (s), (t) and (u)
b will be output. The energization timing signals TUa and TUb are applied to the U-soma transistors 25 and 28.
The energization timing signals TVa and TVb are applied to the bases of the Soma transistors 26 and 29, and the energization timing signals T W a and TWb
is applied to the bases of transistors 27 and 30 of the W soma, and transistors 25 to 30 are turned on in sequence to supply a current to stator windings 38U, 38V and 38W.

By the way, in the characteristics of the brushless motor 37, since the number of rotations is proportional to the input voltage (DC power supply voltage) during no-load operation, the induced voltage is also proportional to the number of rotations. Therefore, for example, as shown in FIG. 3(v),
Figure 3 (w
), a comparative detection signal 557U' may be obtained, and this may be processed by the delay means 63 and logic means 72 as described above, thereby obtaining a position detection signal from which spike-like voltage components have been removed. However, due to the characteristics of the brushless motor 37, a constant input voltage (constant applied voltage)
As the load increases, the rotational speed decreases, so the value of the induced voltage also decreases. Therefore, if the zero-crossing point is detected as described above, the detection speed will increase as the load increases. As a result, the phases of the two phases are shifted (that is, the points where the phase voltage values of the two phases are equal are shifted), making it impossible to generate the maximum torque and causing a decrease in efficiency.

Therefore, in this embodiment, the base i11 voltage regulating means 79 operates as follows to prevent the above problem from occurring. That is, the DC power supply voltage from the DC power supply 21 is lowered to the TTL level by the voltage dividing circuit 80 and then applied to the voltage detection circuit 83.

Therefore, the voltage detection circuit 83 outputs a detection voltage signal S83 proportional to the DC power supply voltage, and this detection voltage signal 3
83 is applied to differential amplification means 88. On the other hand, the differential amplifying means 88 receives the energization timing signal TU from the control circuit 78.
a, TUb, TVa.

A voltage signal S78 proportional to the rotational speed obtained from TVb, TWa, and TWb is provided. In this case, assuming that the DC power supply voltage is constant, if the brushless motor 37 is in a no-load state, the voltage signal 37g will be equal to the detection voltage signal S83 of the voltage detection circuit 83, and the output of the differential amplification means 88 will be zero. (This corresponds to the case of zero-crossing point detection described above). In this state, when the load on the brushless motor 37 increases, the rotational speed becomes low, so the voltage signal S78 also decreases, and the differential amplification means 88 generates a differential voltage signal ΔV between the detected voltage signal S83 and the voltage signal S7h. . This differential voltage signal ΔV is applied to switching circuits 95U, 95V and 95W.

Then, this difference voltage signal ΔV is transmitted to the switching circuit 95 of the U soma.
At U, W given to the analog switch 100U
It is switched between positive and negative depending on the high level and low level of the soma position detection signal PSW and is output as a reference voltage signal 595V, and in the V soma switching circuit 95V, the U soma position detection signal P is given to the analog switch 100V.
It is switched between positive and negative depending on the high level and low level of SU and is outputted as a basic IIFI voltage signal of 595V.
In the W soma switching circuit 95W, the V soma position detection signal PS is applied to the analog switch 100W.
It is switched between positive and negative by V and is output as a reference voltage signal of 595W. In this way, if the output level of the differential amplifying means 88 is matched to the level of the differential voltage output signals 557U, 557V, and 557W, that is, if the values of the reference voltage signals 595U, 595V, and 595W are changed, the brushless motor Even if the load on the motor 37 increases and the rotational speed decreases, and the induced voltage decreases accordingly, it is possible to always control the phase at which the maximum torque can be obtained.

In this way, in this embodiment, the stator windings 38U, 3
Induced voltages UV, VV and W induced at 8V and 38W
V is divided by the voltage dividing circuit 40, and the voltage induced by the voltage TJ is
From Va, VVa and WVa to the buffer circuit 47. Comparison detection signals (position detection signals) S57U, 557V, and 557W are obtained through the differential amplification means 49 and comparison means 56, and these comparison detection signals 557U, 557V, and 55
7W through the delay means 63 and logic means 72 to remove the spike-like voltage component and generate the position detection signals PSU, PSV.
and PSW. Therefore, unlike the conventional case, there is no need to provide filter circuits 4 to 6 with large time constants for phase-shifting the induced voltages UV, VV, and WV.

It is possible to obtain position detection signals PSU, PSV and PSW by detecting vv and Wv at high speed and accurately, has good responsiveness to sudden speed fluctuations, and can operate over a wide range of load fluctuations. , it is possible to reliably obtain a position detection signal even in a low speed region. Furthermore, since there is no need to insert an impedance element between the output circuit 24 and the stator windings 38U, 38V and 38W, there is no problem of large heat generation from the impedance element.

Furthermore, in this embodiment, the reference voltage signal generating means 79 which supplies the reference voltage signals 595U, 595V and 595W to the comparing means 56 is connected to a voltage dividing circuit 80° voltage detecting circuit 83. A reference voltage signal S 95 U, constituted by differential amplifier means 88 and switching means 94.

595V and 595W as a differential voltage output signal 557U.

It changes according to the levels of 557V and 557W, and is switched between positive and negative by position detection signals PSW, PSU and PSV of other phases. Therefore, even if the load on the brushless motor 37 increases and its rotational speed decreases, and the induced voltage decreases accordingly, the brushless motor 37 can be controlled at a phase that can always produce the maximum torque.

In the above embodiment, the reference voltage signal given to the comparison means is changed depending on the DC power supply voltage and the rotation speed, but since the increase in load is proportional to the load current, it is changed according to the load current. Alternatively, it may be changed depending on the load current and rotation speed.

In addition, the present invention is not limited to the embodiments described above and shown in the drawings, but can be applied not only to three-phase brushless motors but also to multi-phase brushless motors in general. It goes without saying that the present invention may be modified and implemented as appropriate without departing from the scope of the invention.

[Effects of the Invention] Since the present invention has been explained above, it has the following effects.

According to the brushless motor drive device according to the first aspect, the position detection signal is generated from the induced voltage induced in the stator windings of multiple phases by the voltage dividing circuit, the differential amplification means, the reference voltage signal generation means, and the comparison means. Since the spike-like voltage component is removed from this position detection signal through the delay means and logic means, the induced voltage in the stator winding is detected at high speed and accurately to obtain the position detection signal. It has good responsiveness to sudden speed fluctuations, can operate over a wide range of load fluctuations, can reliably obtain position detection signals even in low speed regions, and has a high responsiveness to impedance elements. There are no major heat problems.

According to the brushless motor drive device according to claim 2, the reference voltage signal generation means for supplying the reference voltage signal to the comparison means is a differential amplifier means for detecting a difference between an applied voltage and a voltage proportional to the rotation speed, and its output. Since it is configured with a switching means that switches the signal between positive and negative depending on the position detection signal of the other phase, even if the load on the brushless motor increases and its rotational speed decreases, and the induced voltage decreases accordingly, The brushless motor can be controlled at a phase that can always produce maximum torque.

[Brief explanation of the drawing]

1 to 3 show one embodiment of the present invention, FIG. 1 is an overall electrical configuration diagram, and FIG. 2 is a buffer circuit, differential amplification means, comparison means, delay means, logic means, and reference. A concrete electrical configuration diagram of the voltage signal generating means, FIG. 3 is a time chart for explaining the operation, FIG. 4 is a conventional electrical configuration diagram, and FIG. 24 is an inverter circuit (output circuit), 25 to 30 are transistors (switching elements), 37 is a brushless motor, 38 is a stator, 38U, 38V and 38W are stator windings, 39 is a rotor, 40 is a voltage divider circuit , 49 is a differential amplification means, 56 is a comparison means, 63 is a delay means, 72 is a logic means, 78 is a control circuit, 79 is a reference voltage signal generation means, 80 is a voltage dividing circuit, 83 is a voltage detection circuit, 88 is a Differential amplification means, 94 indicates switching means.

Claims (2)

[Claims] 1. A brushless motor includes a permanent magnet rotor and a stator having multiple phases of stator windings that apply a magnetic field to provide rotational force to the rotor. a voltage divider circuit that divides the induced voltages induced in the stator windings of the stator windings, a differential amplification means that detects the potential difference between any two phases of the divided voltage signals of each phase by the voltage divider circuit, and a reference voltage. a reference voltage signal generation means for generating a signal; a comparison means for comparing a reference voltage signal of the reference voltage signal generation means with an output signal of the differential amplification means; and a delay means for delaying the output signal of the comparison means. , a logic means for processing the output signal of the delay means and the output signal of the comparison means to output a position detection signal, and a control circuit for outputting an energization timing signal based on the position detection signal from the logic means; A brushless motor drive device comprising: an output circuit that controls energization of the stator winding based on an energization timing signal from the control circuit. 2. The reference voltage signal generation means includes a differential amplification means for detecting the difference between the voltage applied to the brushless motor and a voltage proportional to the rotation speed of the brushless motor, and an output signal of the differential amplification means as a position detection signal of the other phase. 2. The brushless motor drive device according to claim 1, further comprising a switching means for switching between positive and negative based on.