JPH0119469Y2 - - Google Patents

Description

[Detailed explanation of the idea]

The present invention relates to a multiplication circuit that converts an input pulse into a multiple including arbitrary non-integer numbers. In recent years, there has been a trend toward the adoption of automatic meter reading systems for gas meters, for example, in apartment complexes, etc. In such cases, the measured values from gas meters are converted into electrical signals instead of the conventional mechanical integration and display. Expression is advantageous for centralized management and processing. For this reason, the measured value is converted into an electrical signal in the gas meter by an appropriate method, and after the signal is integrated, the integrated value is displayed and sent to, for example, a centralized control processing device. Here, the substitution to the predetermined unit in the meter,
If rate conversion, correction of instrumental errors, etc. are required, it is necessary to convert the measured value into an appropriate multiple value. FIG. 1 shows a conventional multiplier circuit, in which an input pulse train 1 is multiplied by N by a frequency multiplier 2, and then multiplied by 1/N by a frequency divider 3 (N, M are integers). We can obtain multiples of M that include non-integers. Note that reference numeral 4 is a setting device for setting the value of M. In this multiplier circuit, if N = 100 and the multiple value is 0.8, for example, M
= 125 and the multiple value is 1.10, it is sufficient to set M = 90.90909. However, according to this method, if a large multiple value is required, the value of N of frequency multiplier 2 must also be changed greatly according to the multiple value, and frequency divider 3 is a digital division. Therefore, there is an inconvenience that the values of N and M must be increased for calculations below the decimal point. The present invention was developed in view of the above circumstances, and it is possible to easily set the multiple value, that is, the value to be multiplied can be used as the set value, and the multiple value can be easily and reliably performed. The purpose is a multiplier circuit with A preferred embodiment of the present invention illustrated in FIG. 2 will be described in detail below. The circuit according to the invention consists of two latched binary 10
decimal registers 10, 12, decimal adder 14, and 10
It is composed of a leading subtracter 16, a down counter 18, an oscillator 20, a flip-flop 22, and an AND gate 24, and further includes an edge trigger gate 26 and an edge trigger gate 26, which open in response to a rising signal φ _A at the leading edge of an input pulse. Falling signal φ _B of trailing edge of input pulse
An edge trigger gate 28 is provided which opens in response to. Adder 14 sends its input to two registers 1
0 and 12, and the output is connected via gate 28 to the input of register 12 again. The integer part output a of the register 12 and the integer part output b of the adder 14 are connected to the input of a subtracter 16, the output of which is connected via a gate 26 to a preset input PR of a down counter 18. The borrow output BR of the down counter 18 is sent to the flip-flop 22.
is connected to its reset input R, and its set input S
receives the falling signal φ _B of the trailing edge of the input pulse.
The output Q of flip-flop 22 is AND gate 2
4, and the output of the oscillator 20 is connected to the other input. AND gate 24
The output of is connected to the input DW of the down counter 18 and also to the output P of this multiplier circuit. Register 10 binarizes the value to be multiplied.
It is stored in decimal form. If you set the multiple value once and do not change it, register 10
A read-only memory or the like can be used as the setting, and a digital switch or the like can be used to change the setting. The initial contents of register 12 are cleared to zero. The calculation result in the adder 14 is again input to the register 12 by the gate 28 at the timing of the falling signal φ _B of the input pulse. The integer part output a of the register 12 and the integer part output b of the adder 14 are input to a subtracter, and the integer part output a of the adder 14 is input to the register 12.
The integer value of is subtracted. This result is supplied to the preset input PR of the down counter 18 by the gate 26 at the timing of the rising edge signal φ _A of the input pulse. The calculations in this preset system are shown in the following table with numerical examples. Here, the multiple value A to be multiplied stored in the register 10 is shown as 1.23, and the initial value _B0 of the register 12 is shown as 0. Finally, the sum Σ of the values output by the subtractor 16 is shown.

【table】 …

Claims (1)

[Scope of utility model registration request] An oscillator that generates a pulse with a shorter period than an input pulse, a counter that counts the output pulses of this oscillator, and a gate that allows the output pulses of the oscillator to be input to the counter by the number of values preset in the counter. a pulse train multiplier circuit that outputs a pulse train obtained by converting the input pulse into an arbitrary multiple from the gate circuit, the circuit comprising: a first register storing a desired multiple; and an intermediate operation; a second register for temporarily storing a result; an adder configured to add the outputs of the first register and the second register and transfer the result to the second register; A pulse train multiplier circuit comprising: a subtracter that subtracts the integer part output of the second register from the integer part output of the adder and uses this value as a preset value of the counter.