JPH01193665A - Semiconductor tester - Google Patents

Abstract

PURPOSE:To achieve a higher test efficiency, by providing a plurality of circuits which generate decision strobe pulses in different phases to extract fail signal information by a specified cross pulse corresponding to the pulses. CONSTITUTION:EXOR circuits 3-6 compose four channels of timing decision circuits to receive outputs of comparators 16. A timing generation circuit 7 generates decision strobe pulses in different phases ACLK-DCLK at a fixed interval and has a circuit 8 for generating clock pulses of respective phases and a delay circuit 9. Outputs of the circuits 3-6 are transferred to a CPU10 to obtain the results of decision simultaneously at four timing positions with respect to an output waveform from a semiconductor to be inspected obtained by one test. Thus, the phase interval (timing decision time range) between the pulses ACLK-DCLK is evenly divided to shift the strobe pulses with the delay circuit 9 sequentially thereby enabling the obtaining of a measuring data with a fourfold range while only requiring a quarter of time.

Description

[Detailed Description of the Invention] [Industrial Applicability] The present invention relates to a semiconductor tester, and more specifically, when performing a characteristic test of an LSI, it efficiently performs level judgment processing on an output waveform of an LSI, and improves performance in characteristic measurement. The present invention relates to a semiconductor tester that can increase throughput.

[Prior Art] FIG. 3 shows the overall configuration of this type of semiconductor tester. In the figure, 10 is a CPU, which sets a program necessary for pattern generation in a pattern generator 12 via an interface 11, and sets necessary timing generation data in a timing generation circuit 13. The data from the pattern generator 12 and timing generation circuit 13 are sent to the pin electronics 17, and the driver 15 of the pin electronics 17 sends the data to the device under test (
Test waveform patterns etc. are output corresponding to the 18 pins of the DUT.

In addition, 14 is a test voltage generation circuit, and the CPU1
Based on the data from 0, the bias voltage of DUT18 etc.
Generate a setting voltage etc. to set the level of a test waveform pattern etc. The pin electronics 17 are respectively supplied.

The pattern generator 12 is usually one having an instruction memory composed of ROM and RAM, or an arithmetic pattern generator, and generates addresses for the DUT 17 and generates data such as pattern data and expected value data. In addition to the generation of (D), read/write control signals and the like for the DUTl 8 are also generated.

On the other hand, the output waveform obtained from the DUTl8 is compared with a judgment reference voltage by a comparator 16 as a level judgment circuit built into the pin electronics 17, and the resulting data is temporarily stored in the fail pit memory or directly interfaced. The data is transferred to the CPU 10 via the CPU 11, stored in the memory of the CPU 10, and analyzed by the CPU 10.

- FIG. 4(a) is an explanatory diagram of the comparator portion in the pin electronics 17, and FIG. 4(b) is an explanatory diagram of its measurement state.

The determination reference voltage VD given as the output level determination value is supplied from the test voltage generation circuit 20, and the comparator 16 receives this voltage Vθ as one input and outputs the DU
The output voltage from Tl8 is used as another input, and these are compared to generate a result signal (pass signal) when the output waveform exceeds the comparison reference voltage VD, and a result signal (fail signal) when it does not exceed it. This is sampled by the EXOR circuit lea, which is a timing determination circuit, at a predetermined timing, and a pass signal or a fail signal (however,
In positive logic, the output of the EXOR circuit lea becomes an inverted signal) and is transferred to the CPU10 side.

In this case, as shown in (a) of the same figure (b), 0UT18
The timing generation circuit 13 generates the judgment clock pulse (decision strobe pulse) 2 shown in (b) for the output waveform 1 from
The result signal of the comparator 16 is output to the EXOR circuit 18.
Obtained in a. Next, under similar conditions, output waveform (a)
At this time, the judgment strobe pulse 2 is delayed for a certain period of time, and a similar judgment result is obtained using the next shifted judgment strobe pulse 2. are sequentially shifted for a certain period of time, the judgment results are collected each time, and when the test for one item in that measurement is completed, this time,
Similar measurements are made by changing the power supply voltages of the comparison type 11E V and the DUT 18.

[Problems to be Solved] Incidentally, as semiconductor integrated circuits become more highly integrated, it takes more time to evaluate their characteristics, and it has become necessary to evaluate them at more detailed stages. Therefore, as the number of test items for characteristic tests increases, it has become necessary to evaluate the output waveform from the DUT at various stages.

However, the above-mentioned judgment strobe pulse only has the function of determining the judgment position (timing) with respect to the output waveform, so when evaluating the dependence of access on the power supply voltage of the DUT, it is necessary to There is a problem in that it takes time to evaluate the characteristics because the comparison results (pass signal or fail signal) must be checked each time.

This invention solves these problems of the prior art, and enables efficient performance of characteristic tests.)
11 to provide a conductor tester.

[Means for Solving the Problems] Means in the semiconductor tester of the present invention for achieving such an object include a timing clock generator that generates clock pulses having different phases in correspondence with a plurality of different phases. , a delay circuit that receives multiple clock pulses of each phase and delays each of them by a certain period of time, and a level that compares the output waveform obtained from the device under test with a judgment reference level and generates an output corresponding to the comparison result. It is equipped with a judgment circuit and a plurality of comparison result extraction circuits provided for each phase to extract the output of the level comparison circuit, and a delay circuit sequentially delays the clock pulse of each phase by a certain period of time. The comparison result extraction circuit receives clock pulses of each phase, and a plurality of data obtained from the comparison result extraction circuit at respective timing positions corresponding to the delayed clock pulses of each phase are sequentially obtained as determination data.

[Operation] In this way, a circuit that generates a plurality of judgment strobe pulses (judgment clock pulses) at different phases using a timing generator and extracts information on a pass signal or a fail signal using a predetermined clock pulse can be used for these judgments. By providing multiple channels corresponding to the clock pulses for
By collecting data at a plurality of timing positions on the output waveform of the UT, a plurality of determination results can be obtained at the same time.

As a result, the measurement time is shortened in proportion to the number of channels, and one measurement result data can be transferred in parallel to the CPU side, increasing the throughput in semiconductor tester characteristic measurements, etc. .

[Example] Hereinafter, an example of the present invention will be described in detail using the drawings.

FIG. 1 is a block diagram centered on the determination circuit portion of an embodiment to which the semiconductor tester of the present invention is applied, and FIG.
It is a timing chart for explaining the operation.

Note that components equivalent to those in FIGS. 3 and 4 are designated by the same reference numerals.

In the figure, 3, 4, and 5.6 are each two-man EXO
The R circuit is a timing determination circuit with a 4-channel configuration. These are each comparator 16
The output of is received at one input terminal.

As shown in FIG. 2(a), the timing generation circuit 7 generates ACLK, BCLK, CCLK, and D, which correspond to four channels and have different phases at regular intervals.
It generates four determination strobe pulses for CL, and corresponds to the timing generation circuit 13 in FIG. 3. Therein, there is a clock pulse generation circuit 8 that generates clock pulses of each phase corresponding to each determination strobe pulse, and a delay circuit 9 that receives clock pulses of each phase from this clock pulse generation circuit 8. have.

This timing generation circuit 7 is controlled according to a control signal from CPU10, and its clock pulse generation circuit 8
determines the phase of the clock pulse according to this control, and the delay circuit 9 selects a delay time according to this control, and delays the determination strobe pulse by a certain period of time for each determination. shift. As a result, (a)
The determination strobe pulses of each phase as shown in FIG. 2 are sequentially shifted to generate determination strobe pulses as shown in FIG.

Among the determination strobe pulses generated from the timing generation circuit 7 , A CLK is input to the other input side of the EXOR circuit 3 , and BCLK is input to the other input side of the EXOR circuit 4 . In addition, CCLK is the EXOR circuit 5
DCLK is input to the other input side of the EXOR circuit 6.

The outputs of these EXOR circuits 3, 4, 5.6 are sent to the interface 11 and transferred to the CPU10 via the interface 11. As a result, as shown in the same figure (c), for output waveform 1 from I) UT 18 obtained by one test, judgment results were obtained at four timing positions simultaneously, and these judgment results were as follows: At the same time, it is transferred to the CPU10 side as parallel data.

In this way, as shown in the same figure (d), if the phase interval (timing judgment time width) of each judgment strobe pulse is equally divided and each strobe pulse is simultaneously and sequentially shifted by the delay circuit 9. , measurement data of four times the range can be obtained in one quarter of the measurement time. Therefore, as shown in FIG. 2, the time required to measure one test cycle of the rise characteristic of the output waveform of the DUT 18 can be reduced in proportion to the number of channels.

This is true not only for measuring the rise characteristic, but also for one test cycle for the fall characteristic of the output waveform, and also for one test item for the characteristic of the entire output waveform, which corresponds to Fig. 4(b). be.

For convenience of explanation, four EXOR circuits are arranged in parallel hereafter, but in reality, more EXOR circuits are arranged, and the timing judgment time width is determined by the command from CPU10 to determine the rise characteristic or rise. The number of EXOR circuits to be used in parallel (
Pass/fail information can be obtained in various formats by selecting the number of channels). Note that at this time, the number of strobe pulses in the timing determination time width may also be set, so that the shift time can be selected.

By the way, the pass/fail information obtained as described below is stored in the memory on the CPU10 side, and the pass/fail information obtained at the same time in one test is ACLK,
It is expanded into timing measurement information according to the phase of each clock pulse of BCLK, CCLK, and DCLK, converted into X and Y plane coordinate data in relation to the comparison reference voltage o, and then graphically processed. , will be displayed on the display.

As described above, the EXOR circuit is used in the embodiment, but this may be any other logic circuit or any circuit that can extract the comparison output of the comparator. .

Furthermore, in the embodiment, the measurement results are sent directly to the CPU side, but the measurement results may be stored in a file bit memory, a register, etc., and then transferred all together to the CPU side. .

Furthermore, ACLK, BCLK, (,C
Set the generation timing of each clock pulse of DCLK to the rising position that matches the evaluation grade of the device under test, measure the characteristics at each rising position, and adjust the grade evaluation data to each clock pulse. It can be used to obtain at the same time.

Note that the number of clock pulses may be plural and is not limited to four.

[Effect of the invention] As can be understood from the explanation in H below, this invention has the following effects:
A timing generator generates judgment strobe pulses with multiple different phases, and a plurality of circuits are provided corresponding to these judgment clock pulses to extract pass signal or fail signal information using a predetermined clock pulse, resulting in a multi-channel system. By collecting data at a plurality of timing positions for the output waveform of the DUT at -degrees, it is possible to obtain a plurality of determination results at the same time.

As a result, the measurement time is shortened in accordance with the number of channels, and the data of one measurement result can be transferred in parallel to the CPU side, thereby improving the throughput in characteristic measurements of the semiconductor tester.

[Brief explanation of the drawing]

FIG. 1 is a block diagram focusing on the judgment circuit portion of the embodiment in which the semiconductor tester of the present invention is applied, FIG. 2 is a timing chart for explaining its operation, and FIG.
The figure is a block diagram showing the overall configuration of a conventional semiconductor tester, centering on the pattern generator part.
is an explanatory diagram of the comparator portion in the pin electronics, and FIG. 4(b) is an explanatory diagram of its measurement state. 1... Output waveform from CUT, 2... Judgment strobe pulse, 3.4, 5.6. tea-・EXOR circuit, 7.13
... timing generation circuit, 8 ... clock pulse generation circuit, 9 ... delay circuit,
10...CPU111...Interface, 12.
...Pattern generator, 14...Test voltage generation circuit,
12... Pattern generator, 15... Driver, 16
···comparator.

Claims (2)

[Claims] (1) A timing clock generator that generates clock pulses with different phases corresponding to the plurality of different phases, and a delay circuit that receives the clock pulses of each of the plurality of phases and delays each of them by a certain period of time. a level determination circuit that compares the output waveform obtained from the device under test with a determination reference level and generates an output corresponding to the comparison result; and a plurality of circuits provided for each phase that extracts the output of the level comparison circuit. a comparison result extraction circuit, wherein the delay circuit sequentially delays the clock pulses of each phase by the predetermined time, the comparison result extraction circuit receives the delayed clock pulses of each phase, and the delayed clock pulses are A semiconductor tester characterized in that a plurality of data obtained from the comparison result extraction circuit are sequentially obtained as judgment data at respective timing positions corresponding to phase clock pulses. (2) The clock pulses of each phase are generated at equal intervals, and the fixed time for delaying the clock pulses is equal to 1 when the equal phase intervals are equally divided.
2. The semiconductor tester according to claim 1, wherein the reference level of the comparator is set to increase or decrease sequentially in response to completion of a predetermined test cycle.