JPH01190021A - Pulse amplifier circuit - Google Patents

Abstract

PURPOSE:To quicken the trailing edge of an output pulse by connecting a 2nd transistor(TR) between an output electrode of a 1st TR amplifying a pulse signal and a reference potential point and making a 2nd TR conductive at the trailing edge of the output pulse. CONSTITUTION:When a pulse P is inputted and a pulse is generated at the collector of the 1st TR Q3, the pulse P is subjected to the differentiation by a capacitor C2 and a resistor R11 and negative and positive differentiation pulses P1, P2 are applied to the base of the 4th TR Q6. Then a 3rd TR Q5 is turned on and a 4th TR Q6 is turned off by the negative pulse P1. The 3rd TR Q5 is turned off and the 4th TR Q6 is turned on by the positive pulse P2, the 2nd TR Q4 is turned on to discharge a capacitor CL rapidly. Thus, the trailing edge of the output pulse P3 is quickened and a delay in a conventional circuit is avoided.

Description

[Detailed Description of the Invention] Emperor's Retired Emperor Hadari Bon! The present invention relates to a pulse amplification circuit with a capacitive load.

Generally, when handling high-frequency signals in an IC, distributed capacitance cannot be ignored as a load.Such capacitance occurs not only in the signal line but also between the base of the transistor and the reference potential point. The figure shows a conventional IC pulse amplifier circuit that is forced to have such a capacitance as a load. In the figure, a pulse (P) given to the terminal (1) is transmitted through a diode (0+) It is applied to the base of one transistor (Q+) constituting the amplifier circuit (2), output from the collector of the other transistor ((b), and applied to the base of the transistor (Q3) constituting the emitter follower amplifier. , this transistor (Q3
) is output to the emitter of capacitance (C4) and resistance (Rt).
A load circuit (3) consisting of: Furthermore, (4) (5
) are constant current sources, and (Rt) to (R4) are bias resistors.

(R3) is the load resistance of the transistor (Q2).

When driving such a circuit with high-speed pulses, a problem arises in that the fall of the output pulse becomes slow. For example, the capacitive load circuit (3) uses a high-speed pulse with a pulse width of 15 to 20 ns and a rise time of about 3 to Sns.
When trying to drive, the output pulse waveform at the load end has a relatively quick rise (Ta) as shown in Figure 4, but
The fall (Tb) is delayed due to the influence of the discharge current from the capacitor (CL).

Therefore, the high speed performance of the circuit deteriorates.

The present invention has been made in view of these points, and it is an object of the present invention to provide a novel and effective pulse amplification circuit devised to hasten the fall of the output pulse.

Means for Solving the Problems A pulse amplification circuit of the present invention that achieves the above object includes: a second transistor connected between the output electrode of a first transistor that amplifies a pulse signal and a reference potential point; and a second transistor that amplifies the pulse signal. A configuration comprising: a differentiating circuit for differentiating; and means for applying a differentiated pulse corresponding to a falling edge of the pulse signal among the outputs of the differentiating circuit to a control electrode of the second transistor to make the second transistor conductive; It has become.

Operation-■ According to such a configuration, the second transistor becomes conductive at the falling edge of the output pulse and discharges the charge accumulated in the capacitive load, so that the falling edge of the output pulse becomes faster.

Disaster” 1 piece An embodiment of the present invention shown in the drawings will be described below.

In FIG. 1, the same parts as those in the conventional example shown in FIG. 3 are given the same reference numerals, and redundant explanation will be omitted. In this embodiment, a second transistor (Q,) and a resistor (R+) are connected in series between the emitter of the first transistor (C3) that amplifies the pulse given from the differential amplifier circuit (2) and the ground. .

Then, a third. The emitter of the fourth transistor (Qs) (Q, ) is connected to the base of the transistor Q4) in FIG. Said third
At the base of the transistor (Q,) there is a bias resistor (R&) (
Rff) and a capacitor (C,) apply a fixed bias with low impedance. The potential between this fixed bias and the path is applied to the fourth transistor (
It can also be added to the base of Q,). The base of this fourth transistor (Q,) is also connected to the base of the first transistor (C3) via a capacitor (C2), and the output pulse generated at the collector of the first transistor (Q,) is connected to a resistor (RII). It is differentiated by a differentiating circuit (7) consisting of and a capacitor (C2) and applied to the base of the fourth transistor (Q, ).

In (D2), when the load capacitance (CL) is large, the collector current of the first transistor (Q,) increases significantly at the rise of the pulse, the collector potential drops significantly, and the collector-emitter of the first transistor (C3) increases. When the voltage reaches zero (saturated state), the circuit will cause abnormal oscillation, so
To prevent this, a diode was introduced to suppress the large potential drop at the collector.

Next, the operation of the circuit shown in FIG. 1 will be explained with reference to the signal waveform diagram shown in FIG.

First, input power (P) given to terminal (1) [second
Figure (a)] is amplified by the differential amplifier circuit (2).

The output pulse of the first transistor (C3), which receives the pulse (P) given from the high-impedance differential amplifier circuit (2) as its base, rises due to the load capacitance (CL), as already mentioned in connection with Fig. 3. However, this problem can be corrected in the circuit of this embodiment as follows. That is, 3rd. Fourth transistor (Qs)
The base potential of (Qa) is at the same potential when no pulse is input to the amplifier circuit, and both emitter currents flow to the resistor (R8), but the voltage generated across the resistor (R1) is small and the second This does not lead to making the transistor (C4) conductive. However, when the pulse (P) is input and the collector of the first transistor (C3) is
When the pulse shown in b) is generated, this pulse is subjected to the differential action by the capacitor (C2) and the resistor (RII), and the fourth
The pulses are applied to the base of the transistor (C6) as downward and upward differential pulses (PI) (h) shown in FIG. 2 (c). The downward pulse (P,) turns on the third transistor (Q,) and turns off the fourth transistor (Q,).

However, since the base potential of the third transistor (Qs) is a fixed bias, the emitter potential is only about 0.6V lower than that, and the word that makes the second transistor (C4) conductive is still do not have. In the upward pulse (P2), the third transistor (QS) is turned off and the fourth transistor (Q6) is turned on, but its emitter is approximately 0.6 mm higher than the base of the fourth transistor (Q, ).
Since the potential is low, an upward pulse is generated at the emitter as shown in FIG. 2(d). This upward pulse turns on the second transistor (Q4) and rapidly discharges the capacitor (Ct). The upward pulse (d) is temporally the first
The output pulse (
P3) (FIG. 2 (c)) Corresponds to the falling part, so the fall of the output pulse (P3) occurs early, eliminating the conventional delay.

As described above, according to the present invention, in a pulse amplification circuit or circuit with a capacitive load, the falling characteristic of the output pulse becomes steeper, so the time delay is improved, especially when dealing with high frequency pulses. This has the effect of maintaining high speed.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a pulse amplification circuit embodying the present invention, and FIG. 2 is a diagram showing signal waveforms at various parts thereof. FIG. 3 is a circuit diagram of a conventional example, and FIG. 4 is an explanatory diagram thereof. (3) - Capacitive load, (7) - Differential circuit. (Q3) -・First transistor. (Q4)--Second transistor.

Claims (1)

[Claims] (1) In a pulse amplification circuit in which a capacitive load is equivalently connected to the output electrode of a first transistor that amplifies a pulse signal, a second transistor connected between the output electrode and a reference potential point, and a comprising a differentiating circuit for differentiating a signal, and means for applying a differentiated pulse corresponding to a falling edge of the pulse signal out of the output of the differentiating circuit to a control electrode of the second transistor to make the second transistor conductive. A pulse amplification circuit featuring: