JPH01185448A - Digital oscilloscope - Google Patents

Abstract

PURPOSE:To continuously convert an input signal to a sampling value to store and display said value, by storing the respective max. values in a plurality of sweep operations in the first frame memory of two sets of frame memories and storing the respective min. values in a plurality of the same sweep operations in the second frame memory. CONSTITUTION:A frame memory 19 stores the max. value from a multiplexer 15 and the content of this memory is read to be sent out as the part max. value. A frame memory 20 stores the max. value from the multiplexer 15 on the basis of the timing signal from a display control circuit 12. A frame memory 21 stores the min. value from a multiplexer 18 and the content of this memory is read to be sent out as the past min. value. A frame memory 22 stores the min. value from the multiplexer 18 on the basis of the timing signal from the display control circuit 12. A display circuit 23 displays the max. value given from the memory 20 and the min. value given from the memory 22 so as to be fitted to observation.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital oscilloscope for the purpose of observing waveforms of electrical signals and the like.

(Prior Art) FIG. 4 shows the configuration of a conventional waveform storage device. In FIG. 4, 1 is an AD converter (analog-digital converter) which samples an input signal input to a digital oscilloscope to obtain a sampling value.

Reference numeral 2 denotes a frame memory, which is composed of memories corresponding to the number of points sampled in one sweep. A display circuit 3 reads out the contents of the frame memory 2 and displays them on a cathode ray tube or the like.

Next, the operation of the above conventional example will be explained. In FIG. 4, when a sweep operation is generated by a trigger input as in a general oscilloscope, the AD converter 1 converts the input signal into sampled values at a constant sampling rate by the number of points corresponding to the number of memory words in the frame memory 2. Convert to The frame memory 2 stores the sampled values in the order in which they were generated. Display circuit 3 is frame memory 2
The contents stored in the computer are read out and displayed in a dot sequence or straight line for easy viewing.

(Problem to be Solved by the Invention) However, in the conventional digital oscilloscope described above, during high-speed sweep, the input signal is converted into a sampling value by an AD converter and compared to the sweep time, which is stored in the frame memory, the frame memory is The time it takes for the display circuit to display the stored content is longer. Therefore, even after one sweep is completed, it is necessary to wait for the time required for display, and there is a problem that the next sweep cannot be started.

The present invention solves these conventional problems by providing a digital oscilloscope that can continuously convert input signals into sampling values using an AD converter, store them in a frame memory, and display the results. The purpose is to provide

(Means for Solving the Problems) In order to achieve the above object, the present invention provides two sets of frame memories for storing waveforms, and the first frame memory stores each maximum waveform during a plurality of sweep operations. memorize the value, and then
The frame memory stores the respective minimum values during the same plurality of sweep operations, and the input signals during the plurality of sweep operations are displayed using these maximum and minimum values.

(Function) The present invention has the following effects due to the above configuration. In other words, even if the display operation is slower than the sweep operation, the maximum and minimum values at each point of the input signal obtained during the multiple sweep operations in between are memorized, and these maximum and minimum values can be used to display multiple This has the effect of being able to display the input signal during the sweep operation.

(Example) FIG. 1 shows the configuration of an embodiment of the present invention.

In FIG. 1, 11 is an AD converter.

The input signal input to the digital oscilloscope is sampled and used as a sampling value. 12 is a display control circuit that generates timing signals necessary for the operation of this device. A comparator 13 compares the sampled value from the AD converter 11 with a past maximum value and sends out a comparison signal. 14 is an AND circuit which ANDs the comparison signal from the comparator 13 and the timing signal from the display control circuit 12, and sends out a comparison signal. A multiplexer 15 selects either the sampling value from the AD converter 11 or the past maximum value based on the comparison signal from the AND circuit 14, and sends out the maximum value. A comparator 16 compares the sampling value from the AD converter 11 with a past minimum value and sends out a comparison signal. Reference numeral 17 denotes an AND circuit, which performs an AND operation on the comparison signal from the comparator 16 and the timing signal from the display control circuit 12, and sends out a comparison signal. 18 is a multiplexer which selects either the sampling value from the AD converter 11 or the past minimum value based on the comparison signal from the AND circuit 17, and sends out the minimum value. Reference numeral 19 denotes a frame memory, which is composed of memories for the number of points to be sampled in one sweep, and multiplexer 15.
Store the maximum value from. Also, the contents of this memory are read out and sent out as the past maximum value. Reference numeral 20 designates a frame memory which has the same capacity as the frame memory 19 and stores the maximum value from the multiplexer 15 in response to a timing signal from the display control circuit 12. A frame memory 21 has the same capacity as the frame memory 19, and stores the minimum value from the multiplexer 18 in response to a timing signal from the display control circuit 12. Also, the contents of this memory are read out and sent out as the past minimum value. Reference numeral 22 also designates a frame memory, which has the same capacity as the frame memory 19 and stores the minimum value from the multiplexer 18 in response to a timing signal from the display control circuit 12. 23 is a display circuit, and frame memory 20
The maximum value given by the frame memory 22 and the minimum value given by the frame memory 22 are displayed in a manner suitable for observation.
The configuration will be explained in detail later.

Next, the operation of the above embodiment will be explained. In the above embodiment, the operation of the display control circuit 12 will first be explained based on FIG. 2. In FIG. 2, each sweep operation from the first sweep operation to the fourth m-th sweep operation corresponds to the sweep operation after a trigger occurs in the oscilloscope. That is, when a first trigger occurs in the oscilloscope, the AD converter 11 converts the input signal into sampling values at a constant sampling rate by the number of points required by the frame memory,
When the second trigger occurs, the first trigger that generates the first sweep operation similarly converts the input signal into a sampled value, and the second
Generate a sweep motion. In this way, a third sweep operation and a fourth sweep operation can be generated by subsequent trigger inputs. In this embodiment, one display operation is made up of the first to fourth sweep operations, so if a trigger input continues after the fourth sweep operation, the first sweep operation is generated again in response to the trigger input. It will be repeated. In this case, the display control circuit 12 includes AND circuits 14 and 1
7 in the first sweep operation, and in the second to fourth sweep operations, an H comparison permission signal is output, and the frame memories 20 and 2
For 2, a write enable signal of [4] is sent in the first to third sweep operations, and a write permission signal of H is sent in the fourth sweep operation.

Next, the operation of each individual circuit will be explained. When a sweep operation is generated by a trigger input, the AD converter 11 inputs frame memories 19 and 21 at a constant sampling rate.
The input signal is sampled by the number of points corresponding to the number of memory words in , and converted to a sampling value. In the first sweep operation, the comparison permission signals given to the AND circuits 14 and 17 are L, so the outputs of the AND circuits 14 and 17 are L regardless of the outputs of the comparison circuits 13 and 16. Therefore, the output of the AD converter 11 is selected by the multiplexers 15 and 18, and the sampling values obtained from the converter 11 are written directly into the frame memories 19 and 21, respectively, as the maximum and minimum values in the order in which they were generated. Next, in the second sweep operation, the AND circuit 1
Since the comparison permission signals applied to the comparison circuits 4 and 17 are H, the multiplexers 15 and 18 are operated by the outputs of the comparison circuits 13 and 16. That is, in the second sweep operation, A
Every time the D converter 11 operates and obtains a sampling value, the contents of the frame memories 19 and 21 are read out as past maximum and minimum values, and a peak detection operation is performed by comparing with these. Specifically, the sampling value obtained by the operation of the AD converter 11 and the corresponding past maximum value are provided to the comparator 13 and the multiplexer 15. The comparator 13 compares the sampling value obtained by AD conversion with the past maximum value, and if the sampling value is thicker, the multiplexer 15 selects the sampling value, and if the past maximum value is larger, the multiplexer 15 selects the sampling value. The past maximum value is selected and sent to the frame memory 19 as the maximum value. Further, the sampling value obtained by operating the AD converter 11 and the past minimum value are transmitted to the comparator 16 and the multiplexer 18.
given to. The comparator 16 compares the sampling value obtained by AD conversion with the past minimum value, and if the sampling value is smaller, the multiplexer 18 selects the sampling value, and if the past minimum value is smaller, the past minimum value is selected. The minimum value is selected and sent to the frame memory 21 as the minimum value.

The procedure of the second sweep operation described above is performed in the same manner in the third sweep operation and the fourth sweep operation. However, in the fourth sweep operation, the write permission signal output from the display control circuit 12 is high.
Since the frame memories 20 and 22 become operational, the maximum and minimum values output from the multiplexers 15 and 18 are also written to the frame memories 20 and 22, respectively. That is, the maximum value of each corresponding sampling point in the first to fourth sweep operations within the display period is stored in the frame memory 20, and the minimum value is stored in the frame memory 22. This frame memory 20
The maximum value and minimum value stored in 22 are displayed on the display circuit 23.
This display operation will be explained next with reference to FIG. 3.

In FIG. 3, reference numerals 20 and 22 are the frame memories shown in FIG. 1, each storing the maximum value and minimum value within the display cycle. A graphics processor 31 has a function of connecting a pair of maximum and minimum values read from the frame memories 20 and 22 with a straight line. 32 is a frame memory, which has a size in the X direction that is the same as the number of sampling points for one sweep operation, and a size in the X direction that corresponds to the resolution of the sampling value of AD conversion; 33 is a raster scan type display; It has the same size in the X direction as the frame memory 32.

Next, the operation of the above configuration will be explained. First, at the beginning of a display cycle, the contents of the frame memory 32 are erased.Next, when the first pair of maximum and minimum values are read from the frame memory 20.22 in accordance with the storage order, the graphics processor 31 first erases the contents of the frame memory 32. The address in the X direction to be written to 32 is set to 1, and a straight line is drawn from the address in the X direction corresponding to the maximum value to the address in the X direction corresponding to the minimum value. Furthermore, frame memory 20.2
When the next pair of maximum and minimum values are read from 2, the graphics processor 31 sets the X-direction address to be written to the frame memory 32 as 2, and reads from the X-direction address corresponding to the maximum value to the X-direction address corresponding to the minimum value. Draw a straight line to the address in the direction. In this way, the pair of maximum and minimum values are sequentially read out from the frame memories 20 and 22, and the addresses in the X direction are incremented by 1 in the frame memory 32 until the last pair of maximum and minimum values are read out. Continue drawing. The display device 33 continues to read and display the contents drawn in the frame memory 32 according to the raster scan. The embodiment of the display circuit described here is just one example, and as a means of displaying the maximum value and minimum value within the display cycle in an easy-to-read manner, the maximum value is displayed with one straight line, and the minimum value is displayed with one straight line. A method of displaying the information or a method of displaying it on a vector scan type display may be used.

As described above, according to the above embodiment, at each sampling point in a series of sweep operations initiated from a trigger signal, the comparator 13. The multiplexer 15 stores the larger sampling value among the maximum values in the past sweep in the frame memory 19, and the comparator 16. By storing the smaller sampling value among the minimum values in the past sweeps in the frame memory 21 using the multiplexer 18, the maximum value and minimum value of each sampling point obtained during a plurality of sweeps can be obtained. By displaying the maximum and minimum values of each sampling point using the frame memories 20 and 22° display circuit 23, it is possible to display the information obtained during multiple sweeps in the next display operation. .

(Effects of the Invention) As is clear from the above embodiment, the present invention provides two sets of frame memories for storing waveforms, and each memory of the first frame memory stores the maximum value of sampling values in a plurality of sweeps. By storing the minimum sampling value in multiple sweeps in each memory of the second frame memory, the sweep can be performed continuously even if the display time is longer than the sweep time, and multiple sweep operations can be performed in between. This has the advantage that the information obtained during the display can be effectively stored and displayed in the next display operation.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of a digital oscilloscope according to an embodiment of the present invention, FIG. 2 is an operation timing diagram of the device, FIG. 3 is a block diagram of a display circuit of the device, and FIG.
The figure is a schematic block diagram of a conventional digital oscilloscope. 11... AD converter, 12... Display control circuit, 1
3, 14... Comparator, 15.18... Multiplexer, 19.20.21.22... Frame memory, 23... Display circuit, 31... Graphic processor, 32... Frame memory , 33... Indicator.

Claims (1)

[Claims] Two sets of frame memories for storing waveforms are provided, each memory of the first frame memory stores the maximum value of sampling values in a plurality of sweeps, and each memory of the second frame memory stores the maximum value of sampling values in a plurality of sweeps. A digital oscilloscope that stores the minimum value of.