JPH01176141A - Time division multidimensional exchange system - Google Patents

Abstract

PURPOSE:To attain time division exchange of a multidimensional a signal by preserving the time sequence by a channel memory by 2 frames if there is a difference from the phase of frame between input and output. CONSTITUTION:Even if the phase of frame between input and output is not coincident, the time sequence between plural signals is preserved in a time switch. A virtual frame coincident with the phase of frame of channel memories 104, 105 is to be considered in addition to the frame phase on a highway in the input or output time division signal and the relation of correspondence between input and output time slots is given. Thus, the time switch acts simply the phase conversion switch but also acts like a frame aligner in case of different frame phases between input and output highways.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a time division exchange system for exchanging multiple signals.

(Prior art) When exchanging multiple signals that collectively use a capacity that is an integer multiple of the basic bearer speed, which is a unit of communication capacity, using a time switch, multiple time division multiplexing is used to multiplex the multiple signals. The order of the signals on the input and output sides must match. In order to solve this problem, a conventional method has been known in which the frame phases of time-division multiplexed signals on the input/output highway are matched and a two-sided channel memory is used. A known time switch according to this prior art is described in Nikkei Electronics Magazine, March 9, 1987 issue, pages 96-98.

FIG. 5 is a block diagram showing the configuration of a time switch according to the prior art. The time division switching circuit includes an input highway 301, a demultiplexer 302 whose input is connected to the highway 301, and a first channel memory 304 whose data input DI is connected to a first output of the demultiplexer 302. a second channel memory 305 whose data input DI is connected to the $2 output of the demultiplexer 302;
The first input is the data output Do of the communication path memory 304,
a selector 306 whose second input is connected to the data output DO of the channel memory 305; a frame detection circuit 309 whose input is connected to the highway 301; a control input connected to the output of the frame detection circuit 309; A counter 310 whose empty bit output MSB is connected to the demultiplexer 302 and whose output is connected to the write address input WA of the channel memory 304 and 305, whose input is connected to the most significant bit output MSB of the counter 310 and whose output is connected to the selector 306
an inverting circuit 311 connected to the control input of the control circuit 3;
20, data input DI and write address WA are controlled (
The output of the wholesale circuit 320 consists of a control unit memory 321, in which the read address input word is connected to the output of the counter 310, and the data output Do is connected to the read address input RA of the call memory 304, 305.

In FIG. 5, a case will be described in which the multiple call signal (b, c) multiplexed in time slot 2.3 on input highway 301 is output to time slot 1.4 on output highway 308. FIG. 6 is a time chart showing the operating state of the time switch shown in FIG.

First, the counter 310 that controls the overall operation timing is
It is reset at the beginning of the frame F1 of the speech signal multiplexed on the input highway by the frame detection circuit 309. Using the output of the counter 310 as an address, the communication signals b1, co, b2, and C2 on the input highway are written to addresses #2 and #3 of the communication path memory 304 and addresses #2 and #3 of the communication path memory 305, respectively.

On the other hand, in order to output the multiple call signal (b, c) multiplexed in time slot 2.3 on the input highway to time slot 1.4 on the output highway,
The control circuit 320 writes 2 in advance to address #1 and 3 to address #4.

The speech signal written in the speech path memory is read out in accordance with the control memory in the next frame written from the speech memory opposite to the speech path memory currently being written. That is, in time slot 1.4 of frame F2, call signals b1 and C1 are read from addresses #2 and #3 of call path memory 304, respectively.

In this way, the speech signals multiplexed in all the time slots are stored in the speech memory for one frame and then outputted, thereby transmitting the speech signals b1, cl, b2, and C2 to the output highway while maintaining their order. time slot 1 of
．． It can be output to 4.

(Problem to be Solved by the Invention) When exchanging multiple signals while preserving the time order in the time switch based on the i-based technology shown in Fig. 5, the frame phases between the input and output highways must be matched. There is a need. Therefore, the temporal highway (T) and the spatial switch (
First-in-first-out (FI
It is necessary to align the frame phases of the input/output highway of the time switch using a frame aligner using a memory (FO) memory, etc., resulting in an increase in hardware.

(Means for solving the problem) According to the present invention, it has a communication path memory for two frames,
Time-division multiplexed signals including multiple signals multiplexed on the input highway are written to alternate communication path memories for each frame according to the frame phase of the input signal, and connections are made between multiple input/output time slots to be connected. The input side corresponds in numerical order from the first time slot of the input side frame, and the output side corresponds in numerical order from the output time slot with the same phase as the first time slot of the input side frame. A time division multiple switching system is obtained, which is characterized in that signals are read out from the idle channel memory.

Furthermore, it has a communication path memory for two frames, and writes time division multiplexed signals including multiple signals multiplexed on the input highway to alternate communication path memories for each frame according to the frame phase of the output signal. The plurality of input and output time slots to be connected are made to correspond in numerical order from the input time slot having the same phase as the first time slot of the output side frame on the input side, and in numerical order from the first time slot of the output side frame on the output side. A time division multiplexing system is obtained which is characterized in that a signal is read out from a channel memory in which no input time division multiplexed signal has been written in the frame.

(Function) In the time switch according to the present invention, in order to preserve the time order among a plurality of signals even when the frame phases between input and output do not match, on the input or output time division signal,
In addition to the single frame phase of the highway, we consider one friendly frame that matches the frame phase of the channel memory, and give the correspondence of time slots between input and output in that frame.

As a result, the time switch not only operates as a phase conversion switch but also as a frame aligner when the frame phases between the input and output highways are different.

(Example) The time switch of the present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. According to FIG. 1, a first embodiment of the invention includes an input highway 101, a demultiplexer 102 whose input is connected to the highway 101, and a data input DI connected to a first output of the demultiplexer 102. a first channel memory 104 connected to the channel memory 104; a second channel memory 105 whose data input DI is connected to the second output of the demultiplexer 102; and a second channel memory 105 whose first input is connected to the data output Do of the channel memory 104. , a selector 106 whose second input is connected to the data output DO of the communication path memory 105;
an output highway 108 connected to the output of the frame detection circuit 109 whose input is connected to the highway 101, a control input connected to the output of the frame detection circuit 109, and the most significant bit output MSB is output to the demultiplexer 102. is connected to the write address input WA of the channel memory 104, 105, and an inverting circuit 111 whose input is connected to the most significant bit output MSB of the counter 110 and whose output is connected to the control input of the selector 106.
, a control circuit 120 , a counter 112 , a latch 113 whose input is connected to the output of the counter 112 , whose latch pulse input is connected to the output of the frame detection circuit 109 , and whose output is connected to the input of the control circuit 120 , and a data input. DI and write address WA are connected to the output of the control circuit 120, the read address is connected to the output of the counter 112, and the data output Do is connected to the read address of the call memory 104, 105. It consists of 121.

In FIG. 1, a case will be described in which a multiplexed speech signal (b, c) multiplexed in time slot 2.3 on input highway 101 is output to time slot 1.4 on output highway 108. FIG. 2 is a time chart showing the operating state of the time switch shown in FIG. In this case, it is assumed that the frame phase between input and output is shifted by two time slots. Furthermore, this information is stored in the counter 11
2 is latched at the beginning of the input frame and provided to the control circuit 120.

First, the counter 11 controls the write timing of the input signal.
0 is reset at the beginning of one frame phase of the speech signal multiplexed on the input highway by the frame detection circuit 109. Using the output of this counter 110 as an address, the call signal on the input highway is
, c2 are written to addresses #2 and #3 of the communication path memory 104 and addresses #2 and #3 of the communication path memory 105, respectively.

On the other hand, in order to output the multiple call signal (b, c) multiplexed in time slot 2.3 on the input highway to time slot 1.4 on the output highway, there is a frame phase difference of 2 between input and output. Therefore, it is necessary to provide time loft correspondence between input and output from addresses #3 to j of the control memory 121. Therefore, output time slot 4
to correspond to input time slot 2 and output time slot 1 to input time slot 3, the control memory 12
The control circuit 120 writes 2 in advance to address #4 and 3 to address #1.

The call signal written in the call path memory is read out from the call path memory opposite to the call path memory currently being written in accordance with the contents of the control memory 121. In this case, the communication path memory is switched in the middle of the output frame. As a result, in time slot 1 of frame FO is read out.

In this way, although each signal making up the multiplex signal may be delayed beyond a frame, the speech signal
cl, b2, and C2 can be output to time slot 1.4 of the output highway while maintaining their order.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing a second embodiment of the invention. According to FIG. 3, a second embodiment of the invention includes an input highway 401, a demultiplexer 402 whose input is connected to the highway 401, and a data input DI connected to a first output of the demultiplexer 402. The first channel memory 404 and the data input DI are connected to the demultiplexer 4.
a second channel memory 40 connected to the second output of 02;
5, and the first input is the data output D of the communication path memory 404.
o, the second input is the data output D of the communication path memory 405.
Selector 406 connected to O and human power
01, a counter 410 whose control input is connected to the output of the frame detection circuit 409, whose MSB output is connected to the demultiplexer 402, whose output is the write address input of the channel memory 404, 405. A counter 412 connected to WA, an inverting circuit 411 whose input is connected to the MSB output of the counter 412 and whose output is connected to the control input of the selector 406, whose input is connected to the output of the counter 410, and whose launch pulse input is connected to the counter 412. a latch 413 connected to the output of the latch 413, a control circuit 420 whose input is connected to the output of the latch 413, data input DI and write address WA to the output of the control circuit 420, and read address manual input RA to the output of the counter 412. and the data output Do is connected to the call memory 404.4.
The control memory 421 is connected to the read address input RA of 05.

In FIG. 3, a case will be described in which the multiple call signal (b, c) multiplexed in time slot 2.3 on input highway 401 is output to time slot 1.4 on Hatake highway 408. FIG. 4 is a time chart showing the operating state of the time switch shown in FIG. In this case, it is assumed that the frame phase between input and output is shifted by two time slots. Furthermore, this information is stored in the counter 4
The output of No. 12 is latched at the beginning of the input frame and provided to the control circuit 420.

First, the counter 41 controls the write timing of input signals.
0 is reset by the frame detection circuit 409 at the beginning of the frame F11 of the speech signal multiplexed onto the input highway. A call signal on the input highway is written using the output of this counter 410 as an address, but since the side of the call path memory is switched in the middle of a frame, addresses #2 and #3 of the call path memory 104 are filled with the previous address. C8, bl of frame, address #2 of channel memory 105,
Co and b2 are respectively written in #3.

On the other hand, in order to output the multiple call signals (b, c) multiplexed in time slots 2 and 3 on the input highway to time slots l and 4 on the output highway, there is a frame phase difference of 2 between the input and output. Therefore, in the control memory, it is necessary to sequentially view input time slots from input time slot 3 and establish correspondence between input and output time slots. Therefore, in order to make output time slot 1 correspond to input time slot 3 and output time slot 4 to input time slot 2, address #1 of city IH wholesale memory 421 is set to 3, and address #4 is set to 2.
is written in advance by the control circuit 420.

The call signal written in the call path memory is read out from the call path memory opposite to the call path memory currently being written in accordance with the contents of the control memory 421. As a result, in time slot 1 of frame FO1, the speech signal C8 of the previous frame is read from address #3 in speech path memory 404, and in time slot 4, speech signal b0 is read from address #2 in speech path memory 404. Read out.

Thereafter, in the same manner, the communication signals C8, b, cl, b2 are sent to time slot 1 of the output highway while maintaining the order.
．． It can be output to 4.

Although the above two embodiments have been described using examples of sequential write and random read, similar operations can be obtained by random write and sequential read.

(Effects of the Invention) - As described above, according to the present invention, even when there is a difference in frame phase between input and output, the time order is preserved by the communication path memory for two frames, and multiple signals are time-divided. Exchanges can be made.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a first embodiment of the present invention, Fig. 4 is a time chart showing the operating state of the embodiment shown in Fig. 3, and Fig. 5 shows the configuration of a time switch according to the prior art. The block diagram shown in FIG. 6 is a time chart showing the operating state of the time switch shown in FIG. In the figure, 102.302.402 is a demultiplexer, 104.105.304.305.404.405
is the call path memory, 106.306.406 is the selector,
121, 321, and 421 indicate control memories, respectively.

Claims (2)

[Claims] (1) Has a communication path memory for two frames, and writes time division multiplexed signals including multiple signals multiplexed on the input highway to alternate communication path memories for each frame according to the frame phase of the input signal. , the plurality of input/output time slots to be connected are made to correspond in numerical order from the first time slot of the input side frame on the input side, and in numerical order from the output time slot having the same phase as the first time slot of the input side frame on the output side. , a time division multiplexing system characterized in that a signal is read from a channel memory in which input time division multiplexed signals have not been written in the frame. (2) A time-division multiplexed signal containing multiple signals multiplexed on the input highway with a two-frame communication path memory,
Data is written to alternate communication path memories frame by frame according to the frame phase of the output signal, and between multiple input/output time slots to be connected, the input side starts from the input time slot with the same phase as the first time slot of the output side frame. In numerical order,
A time division multiplexing system characterized in that the output side corresponds in numerical order from the first time slot of the output side frame, and the signals are read from the channel memory to which input time division multiplexed signals have not been written in the frame.