JPH01172998A - Display control circuit - Google Patents

Abstract

PURPOSE:To drive a circuit stably against mixture of noise to a synchronizing signal for control by using the output of the circuit, which takes a pulse synchronized with a vertical synchronizing signal as the input signal and consists of monostable multivibrator and an adder which adds the pulse and the output of this multivibrator, as the clear signal of a frequency dividing circuit. CONSTITUTION:This display control circuit consists of a frequency dividing circuit 11 which takes a pulse synchronized with a horizontal synchronizing signal as the input signal and a timing control signal generating ROM circuit 14 which takes the output of this circuit 11 as the address signal. The output signal of a noise cancel circuit 10 consisting of a monostable multivibrator 6 and an adding circuit 7 is used as the clear signal of the circuit 11. Consequently, the output pulse of the monostable multivibrator 6 to which the vertical synchronizing signal is inputted and the vertical synchronizing signal are added to cancel the noise component in the vertical synchronizing signal, and the signal which is free from noise and synchronized with the vertical synchronizing signal is supplied as the clear signal of the circuit 11. Thus, the output of the frequency dividing circuit is not disturbed by noise mixture.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a display control circuit that uses horizontal and vertical synchronization signals as control signals.

A typical conventional flat display device is a self-emitting type electroluminescent display device (hereinafter abbreviated as a KL display device). This IEL display device is an AC-driven thin film
X. Display devices have been put into practical use. One of the driving methods for an IEL display device is a scene driving method, as disclosed in Japanese Patent Laid-Open No. 68-57191, in which line-sequential scanning is performed in three steps: preliminary charging, modulation, and writing. FIG. 6 shows the basic configuration of the drive circuit. Each electrode of the KL panel 16 has a data side driver 17 and a scanning side odd/even electrode driver 18゜19.
On the other hand, the pulse voltage applied to the IL panel 16 is a pre-charging pulse voltage applied by the pre-charging circuit 2o from the data side, a modulated pulse voltage by the modulating circuit 21 from the scanning side, and further a modulated pulse voltage by the first and second write circuit 22. Line-sequential scanning is performed by these three types of applied voltages, and finally the refresh circuit 24
All KL elements are refreshed by applying a fresh pulse voltage. This refresh method is called simultaneous inversion refresh drive.

Each driver and pulse voltage generation circuit is controlled by data signal (Data), data p-clock signal (D, CI, K)
.

This is performed using a control signal from a timing control circuit 26 that uses a horizontal synchronization signal (HD) and a vertical synchronization signal (VD) as input signals. FIG. 6 shows a voltage waveform applied to the RL element in such a scene driving method. High voltage applied
In the writing step, capacitive coupling due to the KL element capacitance is utilized, and when the selected electrode is an odd-numbered (even-numbered) electrode, a second (first) write pulse voltage on the even-numbered (odd) electrode side is applied. Timing control circuit 26 that controls the entire drive system
As an example, a part of the timing control circuit 26 using horizontal and vertical synchronization signals as input signals is shown in FIG. This is a control circuit for a ROM circuit that mainly generates timing control signals, and includes a D latch circuit 1+2s3, a W frequency divider circuit 11,
It consists of an inverter circuit 12.26, a NAND circuit 4, a counter circuit 13, a ROM circuit 14, and an internal oscillation circuit 6.

FIG. 8 shows the signal waveform at each point. After the vertical synchronization signal VD is inverted by the inverter circuit 26, it is applied to the D input terminal and clear terminal of the D latte circuit 1, and the horizontal synchronization signal HD■ is applied to the clock terminal. D latch circuit 1
The q output ■ becomes a signal latched by the horizontal synchronizing signal HD■, and is applied to the clear terminal of the D latch circuit 2 and the opportunity cycle circuit 11. The internal oscillation circuit 6 has an oscillation frequency of several MHz, and the D latch circuits 2 and 3 and the counter circuit 13
has been added to the clock pin. Horizontal sync signal HD■
is applied to the D input terminal of the D latch circuit 2, and its Q output ■ is latched at the internal oscillation frequency.
The q output becomes a signal delayed by one clock. HAND the Q output of latch circuit 2 and the q output of latch circuit a.
By adding it to circuit 4, its output ■ becomes the horizontal synchronization signal HD
The pulse width becomes a signal equivalent to one clock of the internal oscillation frequency. This is used as a clock signal for the μ frequency divider circuit 11, and is also sent to the counter circuit 13 via the inverter circuit 12.
added as a clear signal. The Q output (■) of the A frequency dividing circuit 11 is a signal of the bar frequency of the horizontal synchronization frequency, and this is used as the line sequential scanning shift signal (8-5F) of the scanning side driver.
T), both K and K are used as address signals for the ROM circuit 14.

Further, the counter circuit 13 divides the oscillation frequency from the internal oscillation circuit 6 and applies each output to the address terminal of the ROM circuit 14 to control the ROM output. The output (2) of the ND circuit is a signal that has the same phase as the horizontal synchronizing signal HD and is latched at the internal oscillation frequency and the vertical synchronizing signal VD. A clear signal is applied to the clear terminal of the counter circuit 13 every scanning period (1H), and the read memory of the ROM circuit 14 is also reset. As an address signal for the ROM circuit 14,
For example, one scanning time (1H
), by setting the M1+1 to M1 terminals for the refresh period, only the address signals of the SIM1 to M1 terminals are input by the clear signal of the counter circuit 13 during line sequential scanning. , ROM output outputs a timing control signal for the line sequential scanning period. On the other hand, during the vertical synchronization period, the q output of the D ratte circuit 2 is cleared, so the clear signal of the counter circuit 13 is in the L state.
An address signal is input to the ROM m terminal, and the ROM output outputs a timing control signal for the refresh period. Furthermore, by using the Q output (■) of the A frequency dividing circuit 11 as an address signal for the ROM, it is used as an identification signal for scanning on the odd electrode side and scanning on the even electrode side in the scanning side driver. The logic control of the even number electrode driver and the timing of the applied pulse voltage are controlled by ROM output. In particular, in the scene drive method, as mentioned above, when the odd-numbered electrode side is selected, the high-voltage write pulse voltage is applied from the even-numbered electrode side.
If this relationship is out of order, the driver becomes conductive and short-circuited when a high-voltage write pulse voltage is applied, causing damage to the driver 9.

Therefore, this odd/even identification signal is very important.

Problems to be Solved by the Invention Let us assume that noise is mixed into vertical and horizontal synchronizing signals that are input signals in the control circuit.

In this case, the vertical and horizontal synchronization signals are mixed at the same timing, but the D latch circuit 2 is cleared by the Q output of the D latch circuit 1 of the vertical synchronization signal mixed with noise, so the horizontal synchronization signal HD The noise of ■ does not appear in the Q output ■. Therefore, the output (2) of the HAND circuit 4 is not affected by noise at all. However, since the A frequency divider circuit 11 uses the Q output (2) of the D latch circuit 1 as a clear signal, it is in a clear state during the period where noise is mixed, so the division output (2) becomes L. Frequency division output just before noise is mixed ■
When is L, the same state continues and the divided output is not affected in any way, but if noise is mixed in when the divided output (2) is H as shown in FIG. 6, a big problem will occur. FIG. 9 shows a detailed signal enlarged waveform diagram when noise is mixed.

During normal operation, the write voltage is applied to the KL element as shown by the dashed arrow on opposite electrode sides as shown by M or B so that the driver ON period and the high voltage pulse application period are not on the same electrode side. It will be done. However, the branch output
When is H and noise is mixed in during the write step, the divided output (2) changes from H to L as shown in the figure, which changes the scanning shift signal (S-8FT) and the address signal (M0) of the ROM circuit 14. . The change in H-L of the scanning shift signal changes the selection of scanning from the odd-numbered electrode side to the even-numbered electrode side. Further, the change in H- and L of the address signal M0 changes the generation of the write pulse voltage by the ROM output from the even-numbered electrode side to the odd-numbered electrode side. Therefore, when the frequency division output ■ changes from ■ to L, the driver is 0N-OFF on the odd numbered electrode side.
, the high voltage pulse goes from oyy to ON, and similarly, on the even numbered voltage side, the driver goes from OFF to ON, and the high voltage pulse goes from ON to
It becomes OFF. During this time, due to mutual response delays, the driver on the same electrode side and the high voltage pulse turn on momentarily, causing an instantaneous short-circuit phenomenon as shown by the solid arrow, and destroying the scanning side driver. . On the other hand, even when the frequency-divided output (2) is in the L state, when the pulse width of the noise continues up to H or is longer than one scanning period (1H), the same phenomenon as described above may lead to destruction of the driver.

In view of this, an object of the present invention is to provide a display control circuit that enables stable driving even when noise is mixed into a control synchronization signal.

Means for Solving the Problems The present invention provides a control system comprising a frequency divider circuit whose input signal is a pulse synchronized with a horizontal synchronizing signal, and a timing control signal generation ROM circuit whose output from the frequency divider circuit is an address signal. A display control circuit characterized in that the output signal of a noise canceling circuit comprising a monostable multivibrator and an adder circuit is used as a clearing signal of the frequency dividing circuit.

Function The present invention cancels the noise component in the vertical synchronization signal by adding the vertical synchronization signal to the output pulse of the monostable multivibrator using the vertical synchronization signal manually, and the clear signal of the frequency divider circuit has the above-described configuration. It is possible to supply a signal synchronized with a vertical synchronization signal that is not affected by noise, and the output of the frequency divider circuit will not be overflowed due to noise contamination.

Embodiment FIG. 1 shows a display control circuit in a first embodiment of the present invention. The difference from the conventional one is the A frequency divider circuit 1.
1 clear signal is passed through the noise canceling circuit 1o without directly supplying the Q output of the D latch circuit 1. Noise canceling circuit 1o is monostable multivibrator 1
It consists of an OR circuit 7 as an adder, an inverter circuit &9, and a bypass capacitor C. The operation of this noise canceling circuit 10 will be explained together with timing chart waveforms at each point in FIG.

The trigger input signal of the monostable multivibrator 6 is supplied with the Q output (2) of the D latch circuit 1. The output pulse T of the monostable multivibrator 6 is set such that τ blade ≦T Ti. (Note that the noise pulse width T is TH≦TB.

) Here, TII is one scanning time, and Ti is the vertical synchronization pulse width. When a vertical synchronizing signal or a noise signal is applied as an input to the monostable multivibrator 6, an output signal with a pulse width τ is generated at the output (2) regardless of the input pulse width length.

The output signal ■ is input to the first gate of the OR circuit 7, and the input signal of the monostable multivibrator 60 (Q output of the D latch circuit 1)
) is added to the second gate. Since the output signal ■ has a positive polarity and the Q output ■ has a negative polarity, the output 0 of the OR circuit 7 by the adder has a pulse width of T (ΔT=
TV-T), /ise portion becomes a residual noise signal corresponding to the monostable multivibrator operation delay time (on the order of 1 second). In this state, A frequency divider circuit 1
If used as the clear signal for No. 1, the residual noise signal will clear the signal and cause malfunctions, as in the conventional case. Therefore, in order to eliminate the residual noise signal, the inverter circuit 8 inverts the signal to make it a positive polarity signal, and the high frequency component on the order of 1 second is grounded via the bypass capacitor G to eliminate the residual noise signal. (Output ■) Then, it is again inverted by the inverter circuit 9 to a negative polarity output signal ■, which is used as a clear signal for the W frequency dividing circuit 11. Furthermore, regardless of single or multiple noises, Tx≦
Since the noise at Tj is corrected by the noise canceling circuit 10, the clear signal of the A frequency dividing circuit 11 is virtually unaffected by the noise. Therefore, the q output (2) of the μ frequency dividing circuit 11 is not affected by noise and can repeat normal division. Generally, the time TH of one scanning period (1H) is several tens of microseconds or more, while most noise is on the order of n seconds to microseconds.
The output pulses T of the monostable multivibrator 6 are slightly equal to T.
It is sufficient if ≧TH. Also, when T≧TV, the vertical synchronization pulse is canceled, so the range of T is TI≦T.
(Becomes Ti.In addition, in FIG. 1, the Q of the D latch circuit 2
The reason why the output (■) is grounded by the capacitor cII is that if there is a response difference between the D input and the clear in the D latch circuit 2 when noise is simultaneously input, a whisker will be output to the Q output (■) and cause a malfunction. This is a bypass capacitor to prevent this from happening. By the way, when considering noise sources, minute pulse noise (TM≦T
i), there is no problem, but the noise pulse width T
, such that TI>Ti, the following new problem arises. However, regarding the clear signal of the A frequency dividing circuit 11, the output pulse T (Tm
There is no fundamental problem since cancellation correction is performed based on ax < Ti). In driving a KL display device, there is a refresh period after the completion of line sequential scanning, as shown in the conventional example in FIG. 5.6, and this refresh period is usually executed within a vertical synchronizing pulse period. If the refresh period is TI, it goes without saying that the condition T, ≦TV is required. On the other hand, the timing control of line sequential scanning and refresh in the control circuit depends on whether or not the address signal from the ROM circuit 14 after Mui+1 is input as described above, and this depends on the application of the clear signal of the counter circuit 13. It depends on the timing. Furthermore, since this clear signal is basically created by the horizontal synchronization signal HD, the stability of the horizontal synchronization signal is important. The disturbance in the horizontal synchronization signal HD will be described below. When one scanning period becomes shorter than the standard (Tit) (even if the divided output of the frequency circuit 11 changes faster than the standard, and the scanning on the odd and even electrode sides is reversed)
Since the address signal of the ROM circuit 14 is reset before common 1, the timing control signal of the ROM output returns to the beginning of one scanning period in line sequential scanning. The same characteristics that occur when high voltage is applied do not occur, so there is no need to worry about damage to the driver. However, if one scanning period is longer than the standard (TI), the clear signal of the counter circuit 13 will also be slower than the standard.
As a result, the address signal is supplied to the terminals after mu i+1 of the ROM circuit 14, and the timing control signal for the refresh period is output from the final part of one scanning period even though line sequential scanning is originally in progress. Then, since the delayed clear signal is input to the counter circuit 13, the ROM output returns to the timing control signal for line sequential scanning.

At this time, refresh driving is performed, so even if the timing control signal suddenly changes to line sequential scanning, the refresh pulse voltage generated by the refresh circuit 24 will not immediately become zero due to the accumulation effect, etc. is directly applied to the scanning side driver, and the driver is short-circuited and destroyed. Therefore, a protection circuit is required when the horizontal synchronization signal HD becomes longer than the standard. FIG. 3 shows a display control circuit in a second embodiment in which these measures have been taken. Further, FIG. 4 is a timing chart waveform at each point for explaining this operation. The pulse width T of the external noise is T
An example of the case where N>TIE will be shown.

In this case, since the horizontal synchronizing signal HD is lost due to noise, it appears that the period is longer than the standard.

The noise canceling circuit 10' applies the Q output ■ of the monostable multivibrator 6 to the first gate of the NOR circuit 28 of the adder, and the Q output ■ of the D latte circuit 1 to the second gate via the buffer circuit 27. It is constructed by supplying the output (2) of the NOR circuit 28 to the clear terminal of the A frequency dividing circuit 11.

The basic operation is similar to the noise canceling circuit 10 in the embodiment shown in FIG. Here, by aligning the delay times of the signals applied to the 1st and 2nd gates of the NOR circuit 28 through the buffer circuit 27, the output of the NOR circuit 28 has a delay time difference as shown in the output ■ in FIG. No residual noise is generated and the bypass capacitor C is eliminated and simplified. This noise canceling circuit 1
The output pulse T of the monostable multivibrator 6 at 0' is TR≦T<Tv ("R: refresh period Tv
: Vertical sync pulse width). Further, the Q output (2) of the monostable multivibrator 6 is connected to the gate of the RABID circuit 4 and used as an inhibit signal.

First, if noise is mixed in, the Q output ■ of the D latch circuit 2 will be cleared by the noise in the vertical synchronization signal VD, so
The output during this period is L. Therefore, the period before and after the horizontal synchronizing signal, /, is longer than the standard TH. Counter circuit 1
Similarly, the clear signal No. 3 has a long period, so the address signal of the ROM circuit 14 is also supplied to the terminals after module +1, and a timing control signal for the refresh period is output. Even if the horizontal synchronization signal becomes normal and the next horizontal synchronization pulse comes, the signal is applied to the gate of the NAND circuit 4 by the Q output of the monostable multivibrator 6, so TR≦T (from the setting of Tv) (to the output of HAND circuit 4)
In this case, the horizontal synchronizing signal is forcibly cut off during the TR period, which is less than the time when noise is mixed. This protective operation allows
The clear signal to the counter circuit 13 is stopped until the refresh operation is completely completed, thereby eliminating the transition to line sequential scanning during the refresh operation and preventing damage to the driver. Although the case where the noise pulse width T)l is Tx)Ta has been described, there is no problem even if T)I≦TIK.

In the embodiment of FIG. 1, if protection against TN>TH is attempted, the refresh period detection circuit 2 as shown by the broken line
This can be realized by newly providing 9, using the address signal after 1+1 of the ROM circuit 14 or a signal generated during refresh as a detection input, and applying the output as an inhibit signal to the gate of the WAND circuit 4. If only the horizontal synchronization signal is disturbed, in the second embodiment, the vertical synchronization signal is normal, so the output of the monostable multivibrator 6 is not generated, and the inhibition signal to the HAND circuit 4 is not supplied. This will lead to the destruction of the driver. For this reason, in order to be completely safe, it is better to provide the refresh period detection circuit 29 and use it as an inhibit signal as described above. Although the embodiments of the present invention have been described using an expletive display device as an example, it goes without saying that any flat display device using an AC drive method is effective.

As described in detail, the present invention can prevent synchronization disturbances caused by electromagnetic induction, electrostatic induction, external noise, etc. mixed into the synchronization system input signal of the display control circuit, or an abnormality in the synchronization system input signal source itself. By canceling the disturbance using the noise canceling circuit device, the timing control signal which is the ROM circuit output is stabilized, and it is possible to prevent driver failure that would occur in the worst case.The practical effect is as follows. big.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a display control circuit according to a first embodiment of the present invention, FIG. 2 is an operation waveform diagram of the same embodiment, and FIG.
The figure is a circuit diagram of the display control circuit in the second embodiment, Figure 4 is an operation waveform diagram of the same embodiment, Figure 6 is a block diagram of the RL display device, and Figure 6 is the KL using the scene drive method.
FIG. 9 is a partially enlarged diagram of the operating waveforms of the display device. 1.2.3...D latch, 4...)f
AND circuit, 6... monostable multivibrator, 7, 28... OR circuit, 1o... noise cancellation circuit, 29... refresh period detection circuit, 14...ROM circuit, 11...
...A frequency dividing circuit, 12...Inverter, 13
...Counter circuit. Name of agent: Patent attorney Toshio Nakao and one other person L'
)＜At the meeting?

Claims (5)

[Claims] (1) A frequency dividing circuit that synchronizes the control circuit of an AC-driven flat panel display device with a horizontal synchronizing signal with a synchronizing pulse width T_H and uses pulse 1 as an input signal, which is output via a multiplier, and uses pulse 1 as a clear signal. A ROM circuit for generating a timing control signal that uses the outputs of the counter circuit and the frequency dividing circuit as an address signal, and uses pulse 2 synchronized with a vertical synchronization signal with a synchronization pulse width T_V as an input signal to generate an output pulse. A display control circuit characterized in that the output of a circuit composed of a monostable multivibrator with a width T and an adder that adds the pulse 2 and the output of the monostable multivibrator is used as a clear signal of the frequency dividing circuit. . (2) Set the output pulse width T of the monostable multivibrator to T
The display control circuit according to claim 1, characterized in that _H≦T<T_V. (3) After completing line sequential scanning, the AC drive type flat display device
2. The display control circuit according to claim 1, wherein the display control circuit is an EL display device using a simultaneous inversion refresh drive method in which a refresh voltage is applied to all picture elements. (4) Refresh period of refresh drive method is T_R
Claim 3, wherein the output pulse width T of the monostable multivibrator is set to T_R≦T<T_V, and the output signal is supplied as an inhibit signal to the gate of the multiplier. Display control circuit as described. (5) A display control circuit according to claim 2, wherein the output of a refresh period detection circuit for detecting a refresh period is supplied as an inhibit signal to the gate of the multiplier.