JPH01169942A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH01169942A JPH01169942A JP62326929A JP32692987A JPH01169942A JP H01169942 A JPH01169942 A JP H01169942A JP 62326929 A JP62326929 A JP 62326929A JP 32692987 A JP32692987 A JP 32692987A JP H01169942 A JPH01169942 A JP H01169942A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- link
- portions
- cutting link
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 239000000758 substrate Substances 0.000 description 11
- 230000001678 irradiating effect Effects 0.000 description 3
- 230000015654 memory Effects 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 210000004907 gland Anatomy 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Landscapes
- Read Only Memory (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に係り、特にレーザを用いた配線切
断によりプログラミングを行なうための配線切断用リン
クを有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a wiring cutting link for programming by cutting the wiring using a laser.
近年、半導体集積回路の高集積化が進むに従って、素子
製作後の回路変更を行なうプログラム素子が組込まれた
ものが増えてきている。特に、大容量メモリでは、欠陥
メモリ素子を予備メモリ素子に切換えて歩留り向上を図
ることが広がりつつある。通常、このプログラミングに
は、レーザによる配線切断が利用されている。この技術
については、例えば「プロシーディング・オブ・ナショ
ナル・エレクトロン・コンファレンス(Proceed
ingof National Electron C
onference)第36巻(1982年発行)第3
85〜389頁」に報告されている。In recent years, as semiconductor integrated circuits have become more highly integrated, an increasing number of semiconductor integrated circuits have built-in programming elements that allow circuit changes after the element is fabricated. Particularly in large-capacity memories, it is becoming increasingly common to replace defective memory elements with spare memory elements to improve yield. Typically, this programming involves cutting wires using a laser. This technology is described in, for example, the ``Proceedings of the National Electron Conference.
ingof National Electron C
onference) Volume 36 (published in 1982) No. 3
85-389''.
すなおち、第2図(a)に示すように、Si基板11上
に5i02膜12を介して形成されたPo1y−8i配
線13を燐ガラス層14で覆って絶縁し、Po1y−8
i配線13の両端をA1配線15に接続した構造のリン
ク部に対して、YAGレーザ(波長1.06μm)また
はその第2高調波(波長0.53μm)のパルス光16
を照射し、Po1y−8i配線13を溶融させて切断す
ることにより、プログラミングを行なうものである。第
2図(b)の平面図に示すように1通常、この配線切断
用リンクを形成するPo1y−8i配線13は、幅Wが
−様となってりる。Specifically, as shown in FIG. 2(a), the Po1y-8i wiring 13 formed on the Si substrate 11 via the 5i02 film 12 is covered with a phosphor glass layer 14 to insulate it, and the Po1y-8i wiring 13 is
Pulsed light 16 of a YAG laser (wavelength: 1.06 μm) or its second harmonic (wavelength: 0.53 μm) is applied to the link portion in which both ends of the i-wiring 13 are connected to the A1 wire 15.
Programming is performed by irradiating the Po1y-8i wiring 13 with melting and cutting it. As shown in the plan view of FIG. 2(b), the width W of the Po1y-8i wiring 13 forming the wiring cutting link is generally negative.
このような配線幅の−様なリンク構造では、照射したレ
ーザ光の熱が配線方向への伝熱により外部に逃げやすい
ので、配線切断にはパワーの高いレーザ光をパルス光と
して照射する方法がとられている。しかし、このリンク
部を十分に覆う第2図(b)の円形領域17に強力なレ
ーザ光を照射すると、Po1y−5i配線13が切断さ
れるだけでなく、下層のSi基板11にまで損傷を与え
、デバイスの信頼性を損なう恐れがあった。In such a link structure with a wiring width like this, the heat of the irradiated laser light tends to escape to the outside due to heat transfer in the direction of the wiring, so it is recommended to cut the wiring by irradiating it with a high-power laser beam as pulsed light. It is taken. However, if the circular area 17 in FIG. 2(b) that sufficiently covers this link part is irradiated with a strong laser beam, not only will the Poly-5i wiring 13 be cut, but the underlying Si substrate 11 will also be damaged. could potentially damage the reliability of the device.
本発明の目的は、このような欠点をなくシ、基板に損傷
を与えることなく配線切断ができる半導体装置を提供す
ることにある。SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and provide a semiconductor device in which wiring can be cut without damaging the substrate.
上記目的は、配線切断用リンクの中に幅が他の部分と不
等の部分を2箇所以上設けることにより達成される。The above object is achieved by providing two or more portions in the wire cutting link with widths that are unequal to other portions.
実施態様としては、配線切断用リンクの中に幅が他の部
分より狭い部分を2箇所以上設けたものと、配線切断用
リンクの中に幅が他の部分より広い部分を2箇所以上設
けたものがある。Examples of implementation include two or more parts in the wire cutting link that are narrower than other parts, and two or more parts in the wiring cutting link that are wider than other parts. There is something.
配線切断用リンクを上記のような構造とすることにより
、リンク部に照射したレーザ光の熱が配線方向への伝熱
によって外部に逃げるのを抑え、照射部位に熱がより多
く保たれるため、下層のSi基板に損傷を与えない低パ
ワーの連続光によってリンク部の溶融切断が容易にでき
るようになる。By configuring the wiring cutting link as described above, the heat of the laser beam irradiated on the link part is suppressed from escaping to the outside due to heat transfer in the wiring direction, and more heat is retained in the irradiated area. The link portion can be easily melted and cut using low-power continuous light that does not damage the underlying Si substrate.
以下、本発明の実施例を図面により説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第1図に本発明の一実施例のプログラム素子の配線パタ
ーンを示す。本実施例では、Si基板上において、外部
配線1から汚染侵入防止のためのガードリング2内に導
かれた配線切断用リンク3の両端に近い2箇所に他の部
分より幅の狭い部分(以下、くびれ部と称す)3a、3
bを設けている。上記リンク3のくびれ部3a、3b間
の通常幅Wの部分を含む円形領域4にArレーザ等の連
続発振のレーザ光を照射すると、照射された部分は、両
端への伝熱がくびれ部3a、3bにより制限されるため
、集中的に加熱されて高温となり、中心部5が溶融切断
する。にもかかわらず、照射するレーザ光は連続光で、
パワーのピーク値が低いため、下層のSi基板には何の
損傷も与えずにすむ。FIG. 1 shows a wiring pattern of a program element according to an embodiment of the present invention. In this embodiment, on the Si substrate, two parts (hereinafter referred to as , called the constriction) 3a, 3
b. When a continuous wave laser beam such as an Ar laser is irradiated onto the circular region 4 including the normal width W between the constrictions 3a and 3b of the link 3, heat transfer to both ends of the irradiated portion is reduced to the constriction 3a. , 3b, it is intensively heated to a high temperature, and the center portion 5 is melted and cut. Despite this, the laser beam irradiated is continuous light,
Since the peak power value is low, no damage is caused to the underlying Si substrate.
第3図は上記実施例中のくびれ部3a、3bの形状が異
なる他の実施例を示し、(a)〜(b)のいずれでも有
効である。FIG. 3 shows another embodiment in which the shapes of the constricted portions 3a and 3b in the above embodiment are different, and any of (a) to (b) is effective.
第4図に示す他の実施例は、配線切断用リンク3に3つ
のくびれ部3a、3b、3cを設けた例で、その中央の
くびれ部3cがレーザ光の照射領域4に入るようにする
。このようにすると、なお低いパワーで配線切断ができ
、下層のSi基板に損傷を与えにくい。Another embodiment shown in FIG. 4 is an example in which the wiring cutting link 3 is provided with three constrictions 3a, 3b, and 3c, with the central constriction 3c entering the laser beam irradiation area 4. . In this way, the wiring can be cut with lower power, and the underlying Si substrate is less likely to be damaged.
第5図は、配線切断用リンク3の両端に近い2箇所に他
の部分より幅の広い部分(以下、広幅部と称す)3d、
3aを設けた他の実施例を示し、配線パターンとしては
(a)〜(d)のいずれでも有効である。本実施例では
、リンク3の広幅部3d、3eを含む広い領域4に連続
発振のレーザ光を照射し、広幅部3d、3eでの吸収熱
を大きくすることにより、中間の通常幅Wの部分から配
線方向に熱が逃げないようにして、中心部5の溶融切断
を容易にする。これにより、パワーのピーク値が低い連
続光での配線切断が可能となり、下層のSi基板に損傷
を与えずにすむ。FIG. 5 shows two parts 3d near both ends of the wiring cutting link 3 that are wider than other parts (hereinafter referred to as wide parts);
3a is shown, and any of (a) to (d) is effective as the wiring pattern. In this embodiment, by irradiating a continuous wave laser beam onto a wide region 4 including the wide width portions 3d and 3e of the link 3, and increasing the absorbed heat at the wide width portions 3d and 3e, By preventing heat from escaping in the direction of the wiring, the center part 5 can be easily melted and cut. This makes it possible to cut the wiring using continuous light with a low peak power value, without damaging the underlying Si substrate.
第6図は広幅部3d、3eの配置が異なる他の実施例を
示し、配線切断用リンク3の中央に通常幅Wの配線を斜
めにとり、その両側に配線幅と同程度のギャップ6.7
を残してSi基板を大きく覆う広幅部3d、3eを配す
ることにより、円形領域4に照射されるレーザ光ができ
るだけSi基板に入らないようにし、しかも伝熱により
リンク中央部から配線方向に熱が逃げにくいようにした
構造をとっている。このようにすることにより。FIG. 6 shows another embodiment in which the wide portions 3d and 3e are arranged differently, in which a wire with a normal width W is diagonally placed in the center of the wire cutting link 3, and a gap 6.7 of the same width as the wire width is provided on both sides of the wire.
By arranging the wide parts 3d and 3e that largely cover the Si substrate while leaving a large area of It has a structure that makes it difficult for people to escape. By doing this.
さらに低パワーで中心部5を溶融切断することができ、
下層のSi基板に損傷を与える可能性は一段と減り、信
頼度の高いデバイスが得られる。Furthermore, the center part 5 can be melted and cut with low power,
The possibility of damaging the underlying Si substrate is further reduced, resulting in a highly reliable device.
本発明によれば、プログラミングのためのレーザによる
配線切断において、配線切断用リンクの中央部から配線
方向に伝熱によって逃げる熱を減らすことができ、より
低パワーのレーザ光でリンクの溶融切断ができるため、
下層のSi基板に損傷を与えることなく、プログラミン
グを行なうことが可能となる。According to the present invention, when cutting wiring using a laser for programming, it is possible to reduce the heat that escapes from the center of the wiring cutting link in the wiring direction, and the link can be melted and cut using a lower power laser beam. Because you can
Programming can be performed without damaging the underlying Si substrate.
第1図は配線切断用リンクの2箇所にくびれ部を設けた
本発明の一実施例の平面図、第2図(a)。
(b)は従来の配線切断用リンクの断面図および平面図
、第3図(a)〜(d)は配線切断用リンクのくびれ部
の形状が異なる本発明に他の実施例の平面図、第4図は
配線切断用リンクの3箇所にくびれ部を設けた本発明の
他の実施例の平面図、第5図(a)〜(d)は配線切断
用リンクの2箇所に広幅部を設けた本発明の他の実施例
の平面図、第6図は広幅部の配置が異なる本発明の他の
実施例の平面図である。
1・・・外部配線、2・・・ガードリング、3・・・配
線切断用リンク、 3 a 、 3 b 、 3 c
” <びれ部、3d。
3e・・・広幅部、4・・・レーザ光照射領域、5・・
・溶融切断部。
第 1 図
3cL、3b<ひ゛れ那
第 2 図
((llL)
C4o)
83 図
(α) (b)
(C)(cL′)
第 4− 区
3 哲己腺切−hrリング 55
客尋1乃析4丁M、3b、3c <ぴ゛に郷
第 6 V
5 〉1融寅ハ咋−eや
6.7 六′で・ソフ′FIG. 1 is a plan view of an embodiment of the present invention in which a wiring cutting link is provided with constricted portions at two locations, and FIG. 2(a) is a plan view of an embodiment of the present invention. 3(b) is a sectional view and a plan view of a conventional wiring cutting link, and FIGS. 3(a) to 3(d) are plan views of other embodiments of the present invention in which the shape of the constriction of the wiring cutting link is different. FIG. 4 is a plan view of another embodiment of the present invention in which the wiring cutting link has narrowed portions at three locations, and FIGS. 5(a) to (d) show wide portions in two locations on the wiring cutting link. FIG. 6 is a plan view of another embodiment of the present invention provided with a different arrangement of the wide portion. DESCRIPTION OF SYMBOLS 1...External wiring, 2...Guard ring, 3...Wiring cutting link, 3a, 3b, 3c
"<Fin part, 3d. 3e...Wide part, 4...Laser beam irradiation area, 5...
- Melted cutting part. Fig. 1 Fig. 3cL, 3b < Hirena Fig. 2 ((llL) C4o) 83 Fig. (α) (b) (C) (cL') Section 4- Section 3 Tetsuki gland incision - hr ring 55
Guest story 1 no analysis 4-cho M, 3b, 3c
Claims (1)
半導体装置において、配線切断用リンクの中に幅が他の
部分と不等の部分を2箇所以上設けたことを特徴とする
半導体装置。 2、配線切断用リンクの中に幅が他の部分より狭い部分
を2箇所以上設けたことを特徴とする特許請求の範囲第
1項記載の半導体装置。 3、配線切断用リンクの中に幅が他の部分より広い部分
を2箇所以上設けたことを特徴とする特許請求の範囲第
1項記載の半導体装置。[Claims] 1. A semiconductor device having a wiring cutting link for programming, characterized in that the wiring cutting link is provided with two or more parts whose widths are unequal to other parts. Semiconductor equipment. 2. The semiconductor device according to claim 1, wherein the wiring cutting link has two or more portions having a width narrower than other portions. 3. The semiconductor device according to claim 1, wherein the wiring cutting link has two or more portions having a width wider than other portions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32692987A JP2728412B2 (en) | 1987-12-25 | 1987-12-25 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32692987A JP2728412B2 (en) | 1987-12-25 | 1987-12-25 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH01169942A true JPH01169942A (en) | 1989-07-05 |
JP2728412B2 JP2728412B2 (en) | 1998-03-18 |
Family
ID=18193342
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32692987A Expired - Fee Related JP2728412B2 (en) | 1987-12-25 | 1987-12-25 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2728412B2 (en) |
Cited By (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0622846A1 (en) * | 1993-04-28 | 1994-11-02 | International Business Machines Corporation | Fabrication and laser deletion of microfuses |
WO1998027595A1 (en) * | 1996-12-18 | 1998-06-25 | Intel Corporation | A silicide agglomeration fuse device with notches to enhance programmability |
US5969404A (en) * | 1995-09-29 | 1999-10-19 | Intel Corporation | Silicide agglomeration device |
EP0957403A1 (en) * | 1998-05-14 | 1999-11-17 | STMicroelectronics S.A. | Fuse in integrated circuit with localized blowing point |
US6323535B1 (en) * | 2000-06-16 | 2001-11-27 | Infineon Technologies North America Corp. | Electrical fuses employing reverse biasing to enhance programming |
WO2002023553A1 (en) * | 2000-09-13 | 2002-03-21 | Siemens Aktiengesellschaft | Organic memory, identification marker (rfid-tag) with organic memory and uses of an organic memory |
EP1401018A2 (en) * | 2002-09-19 | 2004-03-24 | Infineon Technologies North America Corp. | Unpassivated laser fuse with blast barrier to reduce splattering |
US6960489B2 (en) | 2000-09-01 | 2005-11-01 | Siemens Aktiengesellschaft | Method for structuring an OFET |
EP1618609A1 (en) * | 2003-04-11 | 2006-01-25 | International Business Machines Corporation | Programmable semiconductor device |
US7064345B2 (en) | 2001-12-11 | 2006-06-20 | Siemens Aktiengesellschaft | Organic field effect transistor with off-set threshold voltage and the use thereof |
US7223995B2 (en) | 2002-03-21 | 2007-05-29 | Polyic Gmbh & Co. Kg | Logic components comprising organic field effect transistors |
US7229868B2 (en) | 2000-12-08 | 2007-06-12 | Polyic Gmbh & Co. Kg | Organic field-effect transistor, method for structuring an OFET and integrated circuit |
US7238961B2 (en) | 2001-02-09 | 2007-07-03 | Polyic Gmbh & Co. Kg | Organic field effect transistor with a photostructured gate dielectric, method for the production and use thereof in organic electronics |
US7298023B2 (en) | 2001-10-16 | 2007-11-20 | Polyic Gmbh & Co. Kg | Electronic device with organic insulator |
US7329559B2 (en) | 2003-01-21 | 2008-02-12 | Polyic Gmbh & Co. Kg | Use of conductive carbon black/graphite mixtures for the production of low-cost electronics |
US7414513B2 (en) | 2002-08-23 | 2008-08-19 | Polyic Gmbh & Co. Kg | Organic component for overvoltage protection and associated circuit |
US7479670B2 (en) | 2003-08-25 | 2009-01-20 | Polyic Gmbh & Co Kg | Organic electronic component with high resolution structuring, and method of the production thereof |
US7483275B2 (en) | 2001-10-18 | 2009-01-27 | Polyic Gmbh & Co. Kg | Electronic unit, circuit design for the same, and production method |
US7534034B2 (en) | 2000-12-08 | 2009-05-19 | Polyic Gmbh & Co. Kg | Device for detecting at least one environmental influence |
US7576294B2 (en) | 2003-09-03 | 2009-08-18 | Polyic Gmbh & Co. Kg | Mechanical control elements for organic polymer electronic devices |
US7589553B2 (en) | 2005-03-01 | 2009-09-15 | Polyic Gmbh & Co. Kg | Electronic module with organic logic circuit elements |
US7641857B2 (en) | 2002-11-14 | 2010-01-05 | Polyic Gmbh & Co. Kg | Measuring apparatus used for determining an analyte in a liquid sample, comprising polymer electronic components |
US7786818B2 (en) | 2004-12-10 | 2010-08-31 | Polyic Gmbh & Co. Kg | Electronic component comprising a modulator |
US8044517B2 (en) | 2002-07-29 | 2011-10-25 | Polyic Gmbh & Co. Kg | Electronic component comprising predominantly organic functional materials and a method for the production thereof |
US8144495B2 (en) | 2006-03-22 | 2012-03-27 | Polyic Gmbh & Co. Kg | Method for programming an electronic circuit and electronic circuit |
JP2014192477A (en) * | 2013-03-28 | 2014-10-06 | Fujifilm Corp | Organic semiconductor element manufacturing method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5989434A (en) * | 1982-11-15 | 1984-05-23 | Toshiba Corp | Semiconductor device |
JPS6057951A (en) * | 1983-09-09 | 1985-04-03 | Mitsubishi Electric Corp | Semiconductor device |
-
1987
- 1987-12-25 JP JP32692987A patent/JP2728412B2/en not_active Expired - Fee Related
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5989434A (en) * | 1982-11-15 | 1984-05-23 | Toshiba Corp | Semiconductor device |
JPS6057951A (en) * | 1983-09-09 | 1985-04-03 | Mitsubishi Electric Corp | Semiconductor device |
Cited By (40)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0622846A1 (en) * | 1993-04-28 | 1994-11-02 | International Business Machines Corporation | Fabrication and laser deletion of microfuses |
US6258700B1 (en) | 1995-09-29 | 2001-07-10 | Intel Corporation | Silicide agglomeration fuse device |
US6337507B1 (en) * | 1995-09-29 | 2002-01-08 | Intel Corporation | Silicide agglomeration fuse device with notches to enhance programmability |
US5969404A (en) * | 1995-09-29 | 1999-10-19 | Intel Corporation | Silicide agglomeration device |
WO1998027595A1 (en) * | 1996-12-18 | 1998-06-25 | Intel Corporation | A silicide agglomeration fuse device with notches to enhance programmability |
US6271574B1 (en) | 1998-05-14 | 2001-08-07 | Stmicroelectronics S.A. | Integrated circuit fuse with localized fusing point |
FR2778791A1 (en) * | 1998-05-14 | 1999-11-19 | Sgs Thomson Microelectronics | INTEGRATED CIRCUIT FUSE WITH LOCALIZED BLOCKING POINT |
EP0957403A1 (en) * | 1998-05-14 | 1999-11-17 | STMicroelectronics S.A. | Fuse in integrated circuit with localized blowing point |
US6323535B1 (en) * | 2000-06-16 | 2001-11-27 | Infineon Technologies North America Corp. | Electrical fuses employing reverse biasing to enhance programming |
US6960489B2 (en) | 2000-09-01 | 2005-11-01 | Siemens Aktiengesellschaft | Method for structuring an OFET |
US6903958B2 (en) | 2000-09-13 | 2005-06-07 | Siemens Aktiengesellschaft | Method of writing to an organic memory |
WO2002023553A1 (en) * | 2000-09-13 | 2002-03-21 | Siemens Aktiengesellschaft | Organic memory, identification marker (rfid-tag) with organic memory and uses of an organic memory |
US7534034B2 (en) | 2000-12-08 | 2009-05-19 | Polyic Gmbh & Co. Kg | Device for detecting at least one environmental influence |
US7229868B2 (en) | 2000-12-08 | 2007-06-12 | Polyic Gmbh & Co. Kg | Organic field-effect transistor, method for structuring an OFET and integrated circuit |
US7238961B2 (en) | 2001-02-09 | 2007-07-03 | Polyic Gmbh & Co. Kg | Organic field effect transistor with a photostructured gate dielectric, method for the production and use thereof in organic electronics |
US7298023B2 (en) | 2001-10-16 | 2007-11-20 | Polyic Gmbh & Co. Kg | Electronic device with organic insulator |
US7483275B2 (en) | 2001-10-18 | 2009-01-27 | Polyic Gmbh & Co. Kg | Electronic unit, circuit design for the same, and production method |
US7064345B2 (en) | 2001-12-11 | 2006-06-20 | Siemens Aktiengesellschaft | Organic field effect transistor with off-set threshold voltage and the use thereof |
US7223995B2 (en) | 2002-03-21 | 2007-05-29 | Polyic Gmbh & Co. Kg | Logic components comprising organic field effect transistors |
US8044517B2 (en) | 2002-07-29 | 2011-10-25 | Polyic Gmbh & Co. Kg | Electronic component comprising predominantly organic functional materials and a method for the production thereof |
US7414513B2 (en) | 2002-08-23 | 2008-08-19 | Polyic Gmbh & Co. Kg | Organic component for overvoltage protection and associated circuit |
EP1401018A2 (en) * | 2002-09-19 | 2004-03-24 | Infineon Technologies North America Corp. | Unpassivated laser fuse with blast barrier to reduce splattering |
EP1547144A4 (en) * | 2002-09-19 | 2009-01-07 | Ibm | REDUCED SPRAYING IN UNPASSIVATED LASER MELTING COMPOUNDS |
JP2006507668A (en) * | 2002-09-19 | 2006-03-02 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Reduces the scattering of unpassivated laser fuses |
EP1547144A2 (en) * | 2002-09-19 | 2005-06-29 | International Business Machines Corporation | Reduced splattering of unpassivated laser fuses |
US6872648B2 (en) | 2002-09-19 | 2005-03-29 | Infineon Technologies Ag | Reduced splattering of unpassivated laser fuses |
EP1401018A3 (en) * | 2002-09-19 | 2004-09-08 | Infineon Technologies North America Corp. | Unpassivated laser fuse with blast barrier to reduce splattering |
US7641857B2 (en) | 2002-11-14 | 2010-01-05 | Polyic Gmbh & Co. Kg | Measuring apparatus used for determining an analyte in a liquid sample, comprising polymer electronic components |
US7329559B2 (en) | 2003-01-21 | 2008-02-12 | Polyic Gmbh & Co. Kg | Use of conductive carbon black/graphite mixtures for the production of low-cost electronics |
US7872897B2 (en) | 2003-04-11 | 2011-01-18 | International Business Machines Corporation | Programmable semiconductor device |
EP1618609A1 (en) * | 2003-04-11 | 2006-01-25 | International Business Machines Corporation | Programmable semiconductor device |
US8724365B2 (en) | 2003-04-11 | 2014-05-13 | International Business Machines Corporation | Programmable semiconductor device |
US8184465B2 (en) | 2003-04-11 | 2012-05-22 | International Business Machines Corporation | Programmable semiconductor device |
EP1618609A4 (en) * | 2003-04-11 | 2009-10-28 | Ibm | PROGRAMMABLE SEMICONDUCTOR ELEMENT |
US7479670B2 (en) | 2003-08-25 | 2009-01-20 | Polyic Gmbh & Co Kg | Organic electronic component with high resolution structuring, and method of the production thereof |
US7576294B2 (en) | 2003-09-03 | 2009-08-18 | Polyic Gmbh & Co. Kg | Mechanical control elements for organic polymer electronic devices |
US7786818B2 (en) | 2004-12-10 | 2010-08-31 | Polyic Gmbh & Co. Kg | Electronic component comprising a modulator |
US7589553B2 (en) | 2005-03-01 | 2009-09-15 | Polyic Gmbh & Co. Kg | Electronic module with organic logic circuit elements |
US8144495B2 (en) | 2006-03-22 | 2012-03-27 | Polyic Gmbh & Co. Kg | Method for programming an electronic circuit and electronic circuit |
JP2014192477A (en) * | 2013-03-28 | 2014-10-06 | Fujifilm Corp | Organic semiconductor element manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
JP2728412B2 (en) | 1998-03-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPH01169942A (en) | Semiconductor device | |
US6521971B2 (en) | Metal fuse in copper dual damascene | |
US6300232B1 (en) | Semiconductor device having protective films surrounding a fuse and method of manufacturing thereof | |
US6699782B2 (en) | Method of fabricating a wafer level package | |
JPH03123045A (en) | Manufacture of wiring board | |
JP2006108489A (en) | Manufacturing method of semiconductor device | |
JPS6114666B2 (en) | ||
JPS5890769A (en) | Laminated semiconductor device | |
JPH0789567B2 (en) | Semiconductor device | |
JPS61110447A (en) | semiconductor equipment | |
JPH03169049A (en) | Semiconductor integrated circuit | |
JP4399970B2 (en) | Semiconductor device | |
JP2833275B2 (en) | Semiconductor device | |
JPH09120976A (en) | Semiconductor chip mounting method | |
KR100618891B1 (en) | Semiconductor device having a fuse protection pattern portion | |
JPS5989434A (en) | Semiconductor device | |
JPS6091654A (en) | Fuse of laser-trimming in semiconductor device | |
KR100301806B1 (en) | Semiconductor device | |
JP2900452B2 (en) | Semiconductor integrated circuit | |
JPS63260149A (en) | Semiconductor device | |
JPH06244285A (en) | Semiconductor device | |
JPS6015966A (en) | Semiconductor memory device | |
JPH02186660A (en) | Multilayered interconnection semiconductor device | |
JPS599958A (en) | Semiconductor device | |
JPH01149451A (en) | Protective device for cmos input stage gate |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
LAPS | Cancellation because of no payment of annual fees |