JPH01166374A - Digital signal recorder - Google Patents

Abstract

PURPOSE:To obtain excellent reproducing data by recording sink data comprised in each sink block among numerous tracks after being lined up in the widthwise direction of the tracks. CONSTITUTION:A + azimuthal track and a - azimuthal track are alternately arranged, whereas each sink block is disposed among the same azimuthal track to be lined up in the widthwise direction of the tracks. In other words, it is constitutive that the sink data are lined up in the track widthwise direction by setting adequately the data amt. of the sink block, rotating speed of a rotary head, track pitch and trace direction of the rotary head, etc. That is, sink block recording areas SB0-0, SB1-0, SB0-1, SB1-1, SB0-2 and SB0-3 are constituted. For hatched parts, these parts are not recorded with data. By this method, even when a reproducing head traces in the direction of intersecting the track, the reproducing of a digital signal can securely and excellently be performed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal recording device, and particularly to a digital signal recording device that records digital signals while sequentially forming a large number of parallel tracks on a recording medium.

[Conventional technology]

In the following description, a digital video tape recorder (DVTR) will be described as an example of this type of device.

In general, in devices such as DVTRs that record large amounts of digital data on recording media, a predetermined amount of information (video)
Recording and reproduction is performed for each data group (sync block) in which predetermined sync (synchronization) data is added to data. During data playback, data loss and data playback timing shifts occur due to jitter or dropout in the recording and playback system, but data loss can be detected by detecting periodically recorded sync data. This is to minimize the occurrence of such occurrences.

However, data errors occur in the data reproduced through the recording/reproducing system due to lockout, etc., and this often results in erroneous detection in which sync data is detected incorrectly, and synchronization loss in which sync data cannot be detected. If such synchronization loss occurs, serious deterioration will occur in the reproduced information (image).

Therefore, the timing at which sync data will be generated is predicted in advance, and the sync data is configured to be detectable only during the period corresponding to the number of pieces of data that should be played back, thereby avoiding false detection. In this case, so-called synchronization protection processing such as synchronizing with previous sync data and compensating the timing is performed, so that a stable reproduced image can be obtained without problems during normal reproduction.

[Problem that the invention seeks to solve]

However, in the conventional device as described above, when the playback head traces in a direction intersecting the track, for example]
) When performing special playback such as high-speed search playback or slow motion playback in a VTR, playback signals are obtained only intermittently, and the continuity of sync data is lost. Therefore, it is difficult to perform the synchronization protection process as described above, and it becomes impossible to read the data during the above-mentioned special playback, making it impossible to obtain good playback data. The present invention has been made in view of the above-mentioned problems, and provides a digital signal that can be recorded in such a way that synchronization protection is possible and digital signals can be reproduced even when the reproducing head traces in a direction that intersects the track. The purpose is to provide a signal recording device.

[Means for solving problems]

For this purpose, the present invention provides an apparatus for recording digital signals while sequentially forming a large number of parallel tracks on a recording medium, wherein a digital signal is included in each sync block between the large number of tracks. The configuration is such that the sync data is recorded in alignment in the track width direction.

[Effect]

With the configuration described above, even when the playback head traces in a direction intersecting the track, synchronization protection processing is possible because the sync data played back at the time of track jump is continuous. Accordingly, it becomes possible to reproduce digital signals.

〔Example〕

A DVTR as an embodiment of the present invention will be described below.

FIG. 1 is a diagram showing the schematic configuration of the VTR of this embodiment,
A step-by-step explanation will be given below. Terminal 1 receives the luminance signal (Y) and color difference signal (I) of the video signal based on the NTSC signal.
, Q) are input in parallel, and Y is 4 f
sc (fsc is color subcarrier frequency), I, and Q are sampled at a frequency of %, and in this output data, data is thinned out so that sampling points are not lined up vertically between adjacent lines due to interlaced blue. conduct. That is, the analog-to-digital (A/D) converter 2 performs so-called subsampling.

At this time, the sample points of Y are (3) per horizontal scanning period (IH).
, 58M÷15.75K)x%, which is 455 pieces. Actually, only the effective screens are converted into data, and the number is 372 per IH. Regarding I and Q, about 96% of that
become individual.

The output data of the A/D converter 2 is supplied to the memory 3, and E
ECC is added by a cc (error correction code) adding circuit 4.

Here, the video data block, which is the unit to which the FCC is added, has a data amount corresponding to an image of an area obtained by dividing one screen (one field) into 4 vertically by 3 horizontally, as shown by the shaded area in FIG.

In other words, if the number of effective horizontal scanning lines is 240, Y at 60 vertical x 124 horizontal (=372/3) sample points and 6 vertical scanning lines.
I, Q at 0 x horizontal 32 (, = 96/3) sample points
Contains data. These are arranged on the memory 3 as shown in the lower diagram of FIG. 2, and ECC codes C1 and C2 are added as shown, to obtain (192×64) data blocks. Here, the number in the figure represents the number of bytes, and it is assumed that the data of each sample point consists of 8 bits (1 byte).

5 is a circuit that adds 3 bytes of data (X) including 1 byte of sync data (5ync), additional data of each sync block, and a redundancy code for this additional data to each of the 384 bytes of data; Along with this, 392
Get a sink block consisting of bytes. FIG. 3 is a diagram showing one sync block containing video data Vd. The data to which the sync data and data
The converter 7 converts the data into serial data.

The serialized data is then supplied as a digital signal to the recording/reproducing unit 9 via the recording amplifier 8, and is recorded on a magnetic tape (not shown) by a rotating head (not shown).

FIG. 4 is a diagram showing a recording pattern on a magnetic tape by the DVTR of this embodiment. As shown in the figure, the DVT of this embodiment
In R, tracks with +azimuth and tracks with -azimuth are arranged alternately, and between tracks with the same azimuth, each sync block is arranged so as to be aligned in the track width direction. That is, in the VTR of this embodiment, by appropriately setting the data amount of the sync block, the rotational speed of the rotary head, the track pitch, the tracing direction of the rotary head, etc., the sync data can be arranged in the track width direction as shown in FIG. It is configured to line up.

In addition, 5BO-0, 5B1-0, 5BO-1°5 in Fig. 4
BI-t, 5BO-2, 5BO-3, etc. each indicate the recording area of the sync block, and the notching section indicates a portion where no data is recorded.

In FIG. 1, the signal reproduced from the recording/reproducing section 9 is amplified by the reproduction amplifier 10 to a level convenient for signal processing. Reference numeral 11 denotes a clock regeneration circuit, which extracts a clock component included in data from the output of the regeneration amplifier 10 using a technique such as PLL. The data shaping circuit 12 synchronizes the signal distorted in the recording/reproducing system outputted from the reproducing amplifier 10 using a clock of a constant frequency synchronized with the reproduced signal extracted by the clock reproducing circuit 11, and generates a data string with well-timed timing. The O-shaped data string is supplied to a synchronization detection circuit 13, which detects the 8-bit sync pattern contained in the data string. That is, the sync pattern and the data string output from the data shaping circuit 12 are compared bit by bit, and if all bits match, it is assumed to be sync data and a synchronization pulse is output.

However, in this method, if a specific bit pattern that is the same as this tank pattern happens to appear in reproduced data, it may be mistakenly regarded as a sync pattern.

This state is shown in FIG. 5 5y-1. S Y − in FIG.
1 indicates the output of the synchronization detection circuit 13, and the pulse indicated by X in the figure is a pulse associated with the above-mentioned erroneous detection. If the timing of each part of the device is determined by pulses associated with such erroneous detection, all reproduced data thereafter will be erroneous data.

Therefore, based on the clock extracted by the clock regeneration circuit 11, a window pulse (window signal) is created that indicates a period of several to ten clocks before and after the sync data at the cycle in which the sync data is expected to be reproduced. The pulse obtained from the synchronization detection circuit 13 within the period indicated by the pulse is gated by the AND gate 16, and the output of this AND gate 16 is used as a true synchronization pulse to prevent errors in reproduced data due to erroneous detection of sync data. can. This window pulse (shown as w-1 in FIG. 5) is generated by the window signal generation circuit 15 using a pulse generated by the timing signal generation circuit 14 and obtained in synchronization with the reproduction of sync data.

If this window pulse and the detection timing of sync data deviate from each other, or if there is a dropout in the sync data being played, synchronization loss detection will be detected, indicating that no synchronization pulse was detected within the period of the window pulse. Circuit 17 detects. The loss detection circuit 17 counts up the counter 18 every time a synchronization loss is detected. The count value M of the counter 8 indicates the number of consecutive synchronization failures, and this count value M is supplied to the window signal generation circuit 15 to determine the pulse width of the window pulse. That is, the pulse width of the window pulse is configured to become wider as the count value M of the counter 18 becomes larger.

FIG. 5 5Y-2 is the sync data that is missing (the dotted line is the missing part), W-2 is the window pulse, and M is the counter 18.
shows the count value. The counter 18 is reset by a synchronization pulse gated by the AND gate 16, and the count value M is always O in a steady state.

During normal playback, the count value M of the counter 18 becomes 1 only when a data error happens to occur in the sync data during most of the period O. Therefore, synchronization disturbance does not occur, and the data string output from the data shaping circuit 12 is serial-parallel (S/P') by the timing pulse from the timing signal generation circuit 14.
After being converted into parallel data by the conversion circuit 20, the modulation circuit 6
After being demodulated by a demodulation circuit 20 that performs the opposite process, the memory 2
1. The data stored in the memory 21 is BC
After error correction is performed by the C decoding circuit 22, the signal is returned to the original analog signal via a digital-to-analog (D/A) converter 23 and output from the rear terminal 24.

On the other hand, during special playback 1, for example during high-speed playback.

Since the tape is conveyed by a tape drive system (not shown) at several times the recording speed, the envelope waveform of the reproduced signal becomes as shown by e in FIG. 6. The dotted line Th in FIG. 6 indicates the lowest possible level of data detection. Therefore, during high-speed reproduction, there are intermittent periods during which data cannot be reproduced. Naturally, it is impossible to detect sync data during this period.

In the DVTR of the above embodiment, the recording positions of the sync data are aligned in the track width direction between adjacent azimuth tracks, and the width of the window pulse is expanded according to the synchronization loss, so the position between the tracks is Even if the accuracy is slightly degraded, the synchronization pulse can be reliably obtained from the sync data immediately after the track jab.

Therefore, as long as the envelope reaches a level sufficient for data detection, it is possible to restore the recorded data, and the image quality during high-speed playback can be improved compared to the prior art.

FIG. 7 is a diagram showing another example of a recording pattern on a recording medium, and in this example, the sync data is set to be aligned in the track width direction for all tracks. It goes without saying that the same effects as in the above-mentioned embodiments can be obtained even if the DVT, R records according to the recording pattern shown in FIG.

In this specification, a DVTR is taken as an example, and high-speed playback is taken as an example of playback accompanied by track jumps. However, the scope of application of the present invention is not limited to this, and for example, it is possible to A similar effect can be obtained when only information is reproduced by running a tape at high speed.

〔Effect of the invention〕

As explained above, the present invention provides a digital signal recording device that can record a digital signal in a manner that more reliably and effectively reproduces the digital signal even when the reproducing head traces in a direction that intersects the track. Obtainable.

[Brief explanation of the drawing]

FIG. 1 shows a DVTR as an embodiment of the present invention. FIG. 2 is a diagram for explaining video data to be recorded. FIG. 3 is a diagram showing the configuration of a video sync block. Fig. 4 is a diagram showing the recording pattern by the DVTR shown in Fig. 1, Fig. 5 is a timing chart showing the operation of the DVTR shown in Fig. 1, and Fig. 6 is an envelope waveform during high-speed playback of the Il'TR shown in Fig. 1. FIG. 7 is a diagram showing another example of the recording pattern. In the figure, 5 is a sync data addition circuit, 9 is a recording/reproducing section, and 13
14 is a synchronization detection circuit, 14 is a timing signal generation circuit, and 15 is a synchronization detection circuit.
1 is a window signal generation circuit, 16 is an AND gate, 17 is a synchronization loss detection circuit, and 18 is a counter. 47th 5th concave

Claims (2)

[Claims] (1) A device that records digital signals while sequentially forming a large number of parallel tracks on a recording medium, which aligns sync data included in each sync block between the large number of tracks in the track width direction. A digital signal recording device characterized by recording. (2) The plurality of tracks have a first magnetization direction, and recording is performed while forming tracks with a second magnetization direction different from the first magnetization direction between the tracks with the first magnetization direction. A digital signal recording device according to claim (1).