JPH01162032A - Pseudo-error generating device - Google Patents

Abstract

PURPOSE:To automatically generate a logical line error and to improve testing accuracy by providing a first means to count the clock signal of on-line data to a digital on-line communicating line and a means to logic-invert the on-line data when the counting value of the first means goes to be a prescribed value. CONSTITUTION:A reception clock signal 32 is a binary digital signal to be outputted from a data termination device 2 with being corresponded to reception data 31 and the signal 32 is counted per bit by a counter 33 all the time. A register 34 stores the constant of a frequency, with which the line error is desired to be generated, in advance. When the output values of the counter 33 and the register 34 are collated by a comparator 35 and the output value of the counter 33 and the output value of the register 34 are coincident, a data inversion instructing signal 36 is outputted. This data inversion instructing signal 36 is outputted for one bit when the error for one bit part of the receiving data 31 is generated and outputted for the plural bits when the error for the part of the plural bits is generated. Only when the data inversion instructing signal 36 is inputted, an inverting circuit 37 logic-inverts the receiving data 31 and error data 38 are generated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention generates pseudo errors in online data transmitted over a digital online communication line, and prevents online communication equipment from line errors such as communication line disturbances. The present invention relates to a pseudo-error generating device that executes abnormality processing determined by

[Conventional technology]

Conventionally, in abnormality processing tests for line errors such as communication line disturbances in online communication equipment, the tester repeatedly disconnects and connects the digital online communication line, causing problems as if a communication line failure had occurred. The test was conducted based on this assumption.

[Problem that the invention seeks to solve]

In such conventional abnormality processing testing methods, communication line failures are caused manually and intuitively, so the frequency of occurrence and the content of errors are not logical, and the meaning of the actual result test itself is diminished. I can't escape it.

[Means for solving problems]

The pseudo-error generating device of the present invention includes a first means for counting clock signals of online data for a digital online communication line, and a logical inversion of the online data when the count value of the first means reaches a predetermined value. and a second means for generating a pseudo error in the online data.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

Referring to the figure illustrating an embodiment of the invention, data terminal device l is an online communication device. The data termination device 2 is an interface with an online communication line 4. The data terminal device 1 and the data termination device 2 are connected by a digital interface 9, and a general example is VLL as shown in the CCITT recommendation.

V24. This applies to interface formats such as V2O and V35. A pseudo error generating device 3 is provided between the data terminal device 1 and the data termination device 2.

In this pseudo-error generating device 3, how errors are added to the modified received data (pseudo-error data) 38 for the received data 31 and the received clock signal 32 will be explained as an example. Reception clock signal 32 is reception data 3
2 which is associated with 1 and output from the data terminal device 2
It is a value digital signal, and is constantly counted bit by bit by the counter 33. The register 34 stores in advance a constant of the frequency at which line errors are desired to occur. counter 33
A comparison circuit 35 compares the output values of the counter 33 and the register 34, and outputs a data inversion instruction signal 36 when the output value of the counter 33 and the output value of the register 34 match. This data inversion instruction signal 36 is output for one bit when an error of one bit in the received data 31 occurs, and for a plurality of bits when an error of multiple bits is generated.

The inversion circuit 37 is constituted by an exclusive OR circuit, and inverts the logic of the received data 31 to generate error data 38 only when the data inversion instruction signal 36 is input. The data terminal device 1 receives the erroneous data 38 as if it were normal received data. Note that the constants to be stored in the register 34 can be set manually prior to the start of the test, or can be set remotely by program control.

In the above embodiment, a case has been described in which the received data 31 is taken from the data terminal device 2 to the data terminal device 1, but it can be implemented in the same way even if the received data 31 is taken in from the data terminal device 2 to the data terminal device 1.

〔Effect of the invention〕

As described above, according to the present invention, communication line errors can be accurately simulated by automatically generating logical line errors instead of manually generating non-logical errors. As a result, test accuracy can be improved.

[Brief explanation of the drawing]

The figure is a configuration diagram showing one embodiment of the present invention. 1... Data terminal device, 2... Data termination device, 3... Pseudo error generating device, 4...
...online communication line, 31...received data, 32...received clock signal, 33...
...Counter, 34...-Register, 35...
... Comparison circuit, 36 ... Data inversion instruction signal, 37 ... Inversion circuit, 38 ... Modified received data (pseudo error data). Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] a first means for counting clock signals of online data for a digital online communication line; and a second means for logically inverting the online data when the count value of the first means reaches a predetermined value; A pseudo-error generating device characterized by pseudo-generating errors in online data.