JPH01161564A - Information processor - Google Patents

Abstract

PURPOSE:To improve the security level of an information processor formed in the shape of a card while its universal applicability is maintained by providing an address producing circuit which gives address data to a memory at the time of writing data, etc. CONSTITUTION:When writing is made in a memory 3 in an information processor 1, the data in a memory 12B are transferred to the processor 1 side synchronously to the address data updating timing of an address producing circuit 9. On the processor 1 side, the data transferred from a writing circuit 10 are written in the memory 3 by using the address data from the circuit 9. Therefore, the data of the memory 12B on the circuit 10 side are transferred to and written in the memory 3 in the processor 1 at a high speed similarly to the case of direct memory access. By making such an arrangement that only data are given from the outside and addresses are supplied from the circuit 9 at the time of data writing, optional data can be written from the outside and the data stored in the memory 3 cannot be read out from the outside. Thus the universal applicability of this information processor is maintained and at the same time, the security level is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is applicable to information processing devices, and furthermore, to integrated microcomputer systems incorporating a microcircuited CPU (Central Processing Unit) and memory. The present invention relates to techniques that are effective for use in, for example, card-type small information processing devices.

[Prior Art] Information processing devices that incorporate a microcircuit CPU and memory can be configured very compactly, and recently,
For example, published by Nikkei McGraw-Hill, “Nikkei Electronics December 2, 1985 issue no. 3834275-29.
As described on page 5, card-type information processing devices called 1 so-called IC cards are being put into practical use.

This card-type information processing device is expected to be applied to credit cards, deposit cards, game machines, and the like.

Figure 2 shows an overview of a conventional information processing device of this type. Indicates completion.

The information processing device 1 shown in the figure has a CPU (MP
U)2. Writable memory 3, control circuit 4, bus gate 5. An address bus 6, a data bus 7, a control bus 8, etc. are integrally formed and housed in the card.

This card-shaped information processing device has the function of a microcomputer system, and by opening the address bus 6 and data bus 7 to the outside, a dedicated write circuit 10 can be used to read information from the outside to the inside. Data such as programs can be written into the memory 3.

This makes it possible to have any function depending on the customer's purpose of use.

The write circuit 10 includes a CPU 1. Memory 12, control circuit 13, and interface circuit (PIO)
14.15, etc., and is configured so that data such as programs stored in advance in the memory 12 can be written to the memory 3 in the information processing device 1 via the address bus 6 and the data bus 5. There is.

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

That is, as described above, in the conventional information processing apparatus of this type, in order to be able to write data such as a program into the internal memory 1 from the outside,
Address bus 6 and data bus 7 are open to the outside. For this reason, the address bus 6 that is open to the outside
Data such as programs stored in the memory 1 can be easily read using the data bus 7.

Therefore, this type of conventional information processing apparatus has a problem in that the function to prevent confidential leakage and unauthorized copying of data such as programs is low in the so-called security level.

Note that in order to increase the security level of this type of information processing device, it is effective to confine the address bus 6 or the data bus 7 within the device 1 without opening it to the outside. However, if you do this, it will not be possible to write data such as programs from outside, so
The functions of the system are fixed in advance to one type, and it is not possible to add any functions according to the purpose of use by the customer, in other words, the system lacks versatility.

An object of the present invention is to increase the security level of an information processing device formed, for example, in the form of a card, while ensuring its versatility. Our goal is to provide this technology.

The above and other objects and novel features of the present invention will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in this application will be summarized as follows.

In other words, the address bus within the integrated information processing device is divided into an internal address bus and an external address bus, and the flow of address data from the external address bus to the internal address bus is unilaterally regulated. In this method, a pass gate for providing address data for writing to the memory and an address generation circuit for providing address data for writing to the memory are built into the device.

[Operation] According to the above-mentioned means, when writing data such as a program to the memory in the information processing device, only the data is given from the outside and the address is given from the built-in address generation circuit, so that any arbitrary data can be written from the outside. Data can be written. On the other hand, data stored in the memory cannot be easily read from the outside because address data is unilaterally restricted from being given from the outside to the inside. This achieves the objective of increasing the security level of an information processing device formed in the form of a card, for example, while ensuring its versatility.

[Examples] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

In each figure, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows a schematic configuration of an information processing device according to an embodiment of the present invention.

The information processing device 1 shown in the figure has a CPU (or an MP
U) 2. A microcomputer system consisting of a writable memory 3, a control circuit 4, bus gates 5, 51, an address bus 6゜61, a data bus 7, a control bus 8, an address generation circuit 8, etc. is a hybrid type. It is integrally formed in the form of an integrated circuit and housed on a card.

The CPU 2 is a general-purpose processing unit formed into a microcircuit, and has, in addition to an address port A and a data port D, a clock terminal CLK, a bus request signal terminal BRQ, a read signal terminal RD, and the like.

Although detailed illustrations are omitted, the memory 3 is a static type RAM which is a volatile memory, and is backed up by an independent power supply made of a lithium battery, for example, to make it appear non-volatile. ing.

Note that W/R and C8 are write/read and chip selection signal terminals, and OE is a signal terminal indicating validity of memory read.

In the information processing device 1 of the embodiment, the address bus within the device 1 is divided into an internal address bus 6 and an external address bus 61, which are isolated from the outside.

Along with this, a bus gate 51 that unilaterally regulates the flow of address data from the external address bus 61 to the internal address bus 6, and an address generation circuit 9 that provides address data for writing to the memory 3 are provided. ing.

The address generation circuit 9 is configured using a counter, and when writing data such as a program to the memory 3, the CPU
The address data updated in synchronization with the clock from 2 is provided to the memory 3 via the internal address bus 6.

Both bus gates 5 and 51 are bidirectional gates,
Bus gate 5 interposed between address buses 6 and 61
1 is always open in only one direction under the control of the control circuit 4. On the other hand, the bus gate 5 interposed in the data bus 7 is opened in either direction depending on the direction of data flow. It is designed to open.

The write circuit 10 has CPUI 1. Memory 12A.

12B, a control circuit 13, and the like. The memory is provided separately into a memory 12A in which a system program for writing operations is stored, and a memory 12B in which data to be written to the memory 3 in the information processing device 1 is stored.

This write circuit 10 outputs only write data and necessary control signals, but does not output write address data.When writing to the memory 3 in the information processing device 1, the memory 12B data is transferred to the information processing device 1 side in synchronization with the update timing of the address data by the address generation circuit 9. On the information processing device 1 side, data transferred from the write circuit 10 is processed.

The address data given from the address generation circuit 9 is used to write into the memory 3. As a result, the information processing device 1
The data in the memory 12B on the write circuit 10 side is transferred and written to the memory 3 in the memory 3 at a very high speed, just as if DMA (direct memory access) was performed. There is.

As described above, when writing data such as a program to the memory 3 in the information processing device 1, only the data is given from the outside, and the address is given from the built-in address generation circuit 9, so that arbitrary data can be written from the outside. be able to.

On the other hand, data once stored in the memory 3 cannot be read from the outside because address data is unilaterally restricted from being given from the outside to the inside.

Thereby, for example, the security level of the information processing device formed in the form of a card can be increased while ensuring its versatility.

Furthermore, in the embodiment, the memory 3 in the information processing device 1 is a volatile memo backed up by a built-in independent power supply;
By being a
Even if it were to be taken out, the contents of memory 3 would lose their backup and self-destruct.
Its confidentiality is ensured.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the bus gate 51 interposed on the address bus 6.61 may be unidirectional from the beginning. Alternatively, the gate 61 of the address bus may be opened from the outside to the inside only in special cases such as inputting password data.
Further, the memory 3 in the information processing device 1 may be configured to use an EP-ROM.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to a card-type information processing device configured as a hybrid integrated circuit, which is the background field of application, but the invention is not limited to this. It can also be applied to information processing devices that have become monolithic, such as one-chip microcomputers.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

That is, an effect can be obtained that, for example, the security level of an information processing device formed in a card shape can be increased while ensuring the versatility of the information processing device.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram of an information processing device according to the present invention, and FIG. 2 is a schematic configuration diagram of an information processing device studied prior to the present invention. 1...Cardized information processing device, 2...C
PU, 3...Memory, 4...Control circuit, 5.51...Bus gate, 6...Internal address bus, 61...External address bus, 7... Data bus, 8...control bus, 9...address generation circuit, 1o...write circuit. Figure 1 Figure □ Figure 2

Claims (2)

[Claims] (1) An integrated information device having a central processing unit, a writable memory, an address bus, and a data bus, in which the address bus is divided into an internal address bus and an external address bus, and an external An information processing device that includes a bus gate that unilaterally regulates the flow of address data from an address bus to an internal address bus, and an address generation circuit that provides write address data to the memory. (2) The information processing device according to claim 1, comprising a volatile memory backed up by a built-in independent power supply.