JPH01159161A - Data memorizing unit for article discriminating device - Google Patents

Abstract

PURPOSE:To avoid the need of taking care of number of times of rewriting by installing an EE.PROM and a SRAM back-up-operated by a battery as memory and installing a means for discriminating the data which shall be protected or other data by the address of a command. CONSTITUTION:A command transmitted from a controller is received by a receiving part 1, and taken into a control part 4, and the data is memorized into a SRAM 6 back-up-operated by an EE.PROM 5 or a battery 7 under the control of the control part 4. At this time, the position for memorization is selected according to the address contained in the command. The address for the data which shall not be deleted, for example the data such as the discrimination No. of a data carrier and replacement date of battery is assigned into the EE.PROM, and the address for the data which can be reproduced on the upper rank machine side if the discrimination No. of the data carrier can be recognized, even if said data is deleted in ordinary case, is assigned into the SRAM 6.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application This invention relates to a data storage unit of an article identification device used for identifying tools of machine tools and articles conveyed on a conveyor line.

(b) Conventional technology In recent years, in order to identify machine tool tools and conveyed articles, a data storage unit called a data carrier is attached to machine tool tools and conveyed articles, and a controller (read・A write control device) is fixedly installed, and commands are sent from this controller to the data carrier without contact, allowing write access to the data carrier for identification data, or read access to already stored identification data. Many such article identification devices have already been proposed and put into practice.

This type of article identification device uses EE/PR as a data carrier memory that does not require battery backup.
OM or SRAM, which requires battery backup but can provide a relatively long transmission distance, is used.

(c) Problems to be solved by the invention Among the conventional data carriers mentioned above, EE/FROM
For the type that uses EE-PROM, there is a limit to the number of times the EE-PROM can be rewritten (approximately 10,000 times). Although there is a limit to the number of rewrites, the count value is rewritten only once, so it is difficult to self-memorize information on the number of rewrites. The transmission distance between the controller and the controller cannot be long.

There are problems such as smaller capacity than SRAM.

On the other hand, the type of SRAM that uses SRAM has the problem that the retention time of stored information is affected by the battery life, and when the battery life reaches the end, all stored information is lost, making it impossible to identify the data carrier. was there.

This invention was made by focusing on the above-mentioned problems, and normally allows a long transmission distance, without worrying about the number of rewrites, and even when the battery life reaches the end, the data carrier itself remains intact. The aim is to provide a data carrier, ie a data storage unit, in which the information necessary for identification is not lost.

(d) Means and operation for solving the problem The data storage unit of the present invention has a built-in memory, and identification data is write-accessed to the memory or stored in the memory in response to a command sent from a controller. In the case where the identification data to be read is read-accessed, an EE-PROM and a SRAM backed up by a battery are installed in parallel as the memory, and whether the data requires protection or other data depending on the address of the command. If the data to be accessed requires protection, the EE-PROM is accessed; if the data does not require protection, the SRAM is accessed. ing.

In this data storage unit, under normal conditions, that is, when the battery life has not yet expired, irremovable data such as the identification number of the data storage unit itself, the date and time of battery replacement, etc. is stored in the EE-PROM, and other data is stored in the EE-PROM. The data of S
Stored in RAM. Therefore, during normal transmission, S
Read/write access is made to the RAM, making it possible to extend the transmission distance, and also allowing the number of rewrites of the EE/PROM to be stored in the SRAM. When the SRAM backup battery reaches the end of its life, it is stored in the SRAM. Data will be lost. However, identification data that identifies a data storage unit is classified as data that requires protection.
The data storage unit is stored in the E-PROM, and the data storage unit can be identified even after the battery life has expired.

(e) Examples The present invention will be explained in more detail with reference to Examples below.

FIG. 1 is a schematic block diagram of a data carrier showing an embodiment of the present invention. This data carrier receives a command transmitted from a controller (read/write control device) not shown in the figure at a receiving section 1, passes through a demodulation circuit 2 and a decoder 3, and takes it into a control section 4, and controls the control section 4. Data is stored in the EE/FROM 5 or the SRAM 6 backed up by the battery 7. In other words, it is configured for write access and is already configured for EE.
When reading data stored in the PROM 5 or SRAM 6, upon receiving a read command, the control unit 4
Under the control of EE-PROM 5 or SRAM 6, data at a predetermined address is read, and encoder 8,
The signal is transmitted from the transmitting section 10 to the controller via the modulating circuit 9.

Communication between a controller (not shown) and a data carrier is performed by electromagnetic coupling, optical communication, electromagnetic waves, or the like.

Which memory, EE-PROM 5 or SRAM 6, is to store the data transmitted from the controller is selected by the address included in the command. EE-PROM5 may be harmed by data that is likely to be lost, such as the data carrier identification number or the address to access data indicating the date and time of battery replacement]
If the identification number of the data carrier is determined, the address to be accessed for the data that is assigned to S and can be reproduced on the upper device side is S, even if it is normally lost.
It is allocated to RAM6.

The 'MI Jll section 4 is a circuit having an I10 control function, a command decoding function, and a memory control function, and its specific configuration is as shown in FIG. This control unit 4 includes a shift register, and converts the serial data from the decoder 3 into parallel data, and conversely converts the signal output to the encoder 8 from parallel to serial and outputs the serial/parallel/parallel/serial (S). /P/P/S) conversion unit 21, buffer register 2
2. A command register 23 that stores commands among input data, a byte counter 24 that stores the number of data, an address register 25, and a state control circuit 2
6. Memory control circuit 27 that outputs a memory control signal according to the decoded contents of the command, I10 control circuit 2nd, command error, address error,
Error check circuit 2 that checks parity errors, etc.
9. It is composed of a status register 30 for storing memory type, capacity, command information, error information, etc., and a parity register 31 for creating parity at the time of reading and performing a parity check at the time of writing.

Next, the operation of the data carrier of the above embodiment is shown in FIG. 3(A).
, will be explained with reference to flowcharts shown in FIGS. 3(B) and 3(C).

First, a data carrier attached to an article approaches the controller, and when the data carrier enters the communication range,
In other words, when it enters the operating range, the reset of the control unit 4 is released and the synchronization character is first transferred from the data carrier to S/S.
The status is input into the shift register of the P-P/S converter 21 and output to the controller side [step ST (hereinafter referred to as ST) 1], and the status stored in the status register 30 is input to the shift register and output (ST2).
). When the synchronization character and status are transmitted, the controller receives them and learns that the data carrier is within the communicable range, and then transmits a signal such as a write command or read command. These write commands and read commands further consist of data, parity code, etc. in the case of a synchronization character, write code, read code, or write code. Determine whether When a synchronization character is detected, it means that the command will be transmitted from now on.
Therefore, the command input is stored in the command register 23 (ST4). Here, the state control 26 decodes the transmitted command, and if the command is a read command, for example, it moves to ST6 and stores the byte number input transmitted next to the command in the byte counter 24 ( At the same time as ST6), the address input is stored in the address register 25 (ST7).

Then, in the state control circuit 26, the address is set to SR.
5T to determine whether it is assigned to AM6 or not.
8) When reading data stored in the SRAM 6, the memory control circuit 27 reads the data stored in the SRAM 6.
A signal for energizing is output (ST9). On the other hand, if the address is not assigned to SRAM6, E
Outputs a signal to energize E-PROM5 (STIO)
.

Subsequently, the synchronization character is put into the shift register and outputted (STII), and the status is put into the shift register and outputted (ST12).

Based on the address signal from the address register 25, the address is accessed and data is input to the buffer 22 (5T13), and the access data of the buffer register 22 is outputted via the shift register and stored in the parity register 31 (ST14). ). Next, the byte counter 24 is set to -IL (ST 15), and it is determined whether the byte counter 24 is 0 (STI 6). If the byte man terminal 24 is not 0, it indicates that there are still addresses to be read, and the judgment of 5T16 is NO.
Then, the process moves to 5T17, the address is incremented by 1, and the processes from 5T13 to 5T16 are repeated for the next address, and the data in the memory is read out. When the byte counter 24 reaches O, it indicates that there is no remaining data to be read. In this case, the determination in ST13 becomes YES, and the contents of the parity register 31 are input to the shift register and output (ST18). This completes the return of the lead response. Then, the process returns to ST3 and waits for the next command.

On the other hand, if the command decoding result in ST5 is a write command, the byte number input is stored in the byte counter 24 and the address input is stored in the address register 25 in the same way as for the read command (ST19.2
0). Then, it is determined whether the address is assigned to the SRAM 6 (5T21), and when writing data to the SRAM 6, the memory control circuit 27 outputs a signal to energize the SRAM 6 (ST
22). On the other hand, if the address is not assigned to the SRAM 6, a signal for energizing the EE-PROM 5 is output (ST23). Next, data is input to the shift register (ST24), and the contents of the shift register are transferred to the buffer register 22 and parity register 3.
1 (ST25). Then, the memory corresponding to the address data of the designated address register 25 is accessed, and the data of the buffer register 22 is stored in the memory (ST26). Then, the byte counter 24 is decremented by 1 (ST27), and it is determined whether the byte counter 24 is 0 or not (5T2B), and the byte counter 24 is 0.
If not, it indicates that there is still data to be accessed for write, and in this case, the address is +1 processed in 5T29, and the process returns to 5T24, and the processes from 5T24 to 5T28 are performed on the +1 address. conduct,
New next data will be written.

When the byte counter 24 becomes 0, the judgment of 5T28 is Y.
ES, indicating that there is no data left to write. In this case, the process moves to 5T30, where parity is input to the shift register, and the contents of the shift register are transferred to the parity register 31 (5T31).
If the content of the parity register 31 is not O, an error is set in the status (ST32), and if it is O, the process returns to ST3 and waits for the next command to be transmitted.

(f) Effects of the invention According to this invention, an EE-PROM and a battery-backed SRAM are installed side by side as memories, and non-erasable data is stored in the EE-PROM and other data is stored in the SRAM, depending on the address. Therefore, in normal times, S
By operating the RAM as a memory, the transmission distance can be extended, and there is no need to worry about the number of rewrites. Moreover, even when the battery life reaches the end, the identification number of the data storage unit is stored in the EE-PROM and will not be erased, so the data storage unit can be identified even after the battery life has expired.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data carrier showing an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration of a control section of the data carrier, FIG. 3(A), FIG. (
B) and FIG. 3C are flowcharts for explaining the normal operation of the data carrier of the above embodiment. 4: Control unit, 5: EE-PROM, 6: S
RAM, 7: Battery, Patent applicant: Tateishi Electric Co., Ltd. Agent, Patent attorney: Shigenobu Nakamura

Claims (1)

[Claims] (1) In a data storage unit of an article identification device that has a built-in memory and in which identification data is write-accessed to the memory or identification data stored in the memory is read-accessed by a command sent from a controller, As the memory, an EE-PROM and an SRAM backed up by a battery are arranged in parallel, and a means is provided to identify whether data requires protection or other data based on the address of the command, and the data to be accessed is A storage unit of an article identification device, wherein the EE-PROM is accessed when the data requires protection, and the SRAM is accessed when the data does not require protection. .