JPH01152704A - Composite electronic component - Google Patents
Composite electronic componentInfo
- Publication number
- JPH01152704A JPH01152704A JP62313689A JP31368987A JPH01152704A JP H01152704 A JPH01152704 A JP H01152704A JP 62313689 A JP62313689 A JP 62313689A JP 31368987 A JP31368987 A JP 31368987A JP H01152704 A JPH01152704 A JP H01152704A
- Authority
- JP
- Japan
- Prior art keywords
- temperature coefficient
- electrode
- positive temperature
- coefficient thermistor
- electronic component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000002131 composite material Substances 0.000 title claims description 8
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 238000009434 installation Methods 0.000 abstract description 5
- 230000001681 protective effect Effects 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 229910052709 silver Inorganic materials 0.000 description 3
- 239000004332 silver Substances 0.000 description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
Landscapes
- Thermistors And Varistors (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、単一の部品で過電流に対する保護機能とサー
ジ電圧に対する保護機能とを有する複合電子部品に関す
る。DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a composite electronic component having a protection function against overcurrent and a protection function against surge voltage in a single component.
〈従来の技術〉
従来、各種電気機器に対する過電流保護には正特性サー
ミスタが用いられ、また、サージ電圧の保護にはバリス
タが用いられている。<Prior Art> Conventionally, positive characteristic thermistors have been used for overcurrent protection for various electrical devices, and varistors have been used for surge voltage protection.
〈発明が解決しようとする問題点〉
ところで、保護すべき電気機器においては、過電流およ
びサージ電圧の両方に対する保護が必要である場合が多
く、このような場合は、ディスクリート部品である正特
性サーミスタとバリスタとを電気機器に各別に接続して
いる。<Problems to be Solved by the Invention> Incidentally, electrical equipment to be protected often requires protection against both overcurrent and surge voltage, and in such cases, a positive temperature coefficient thermistor, which is a discrete component, is required. and the varistor are connected to electrical equipment separately.
しかしながら、このように2種の電子部品を各別に接続
していたのでは、その接続作業に手数がかかり、また、
取付のためのスペースら大きくなる。However, if two types of electronic components were connected separately in this way, the connection work would be troublesome, and
The space for installation becomes larger.
本発明は、上述の問題点に鑑みてなされjsものであっ
て、過電流の保護機能を有する素子とサージ電圧の保護
機能を有する素子とを一体化して単一の電子部品とし、
電気機器への接続作業を容易化するとともに、取付スペ
ースを削減することを目的とする。The present invention was made in view of the above-mentioned problems, and includes an element having an overcurrent protection function and an element having a surge voltage protection function, which are integrated into a single electronic component.
The purpose is to simplify the connection work to electrical equipment and reduce the installation space.
く問題点を解決するための手段〉
本発明は、上記の目的を達成するために、正特性サーミ
スタ素子およびバリスタ素子を備え、これら2種の素子
を絶縁スペーサを介して積層一体化し、各素子の一方の
電極を、該2種の素子と絶縁スペーサとからなる積層体
の同一の側面部に導出して第1の外部端子に共通に接続
し、各素子の他方の電極をそれぞれ積層体の互いに異な
る側面部に導出して第2もしくは第3の外部端子に接続
して複合電子部品を構成した。Means for Solving the Problems> In order to achieve the above object, the present invention includes a positive temperature coefficient thermistor element and a varistor element, and integrates these two types of elements by laminating them via an insulating spacer. One electrode of each element is led out to the same side surface of the laminate made of the two types of elements and an insulating spacer and commonly connected to the first external terminal, and the other electrode of each element is connected to the same side of the laminate made of the two types of elements and an insulating spacer. A composite electronic component was constructed by leading out to different side surfaces and connecting to a second or third external terminal.
〈作用〉
上記の構成において、第1の外部端子を入力側に接続し
、第2の外部端子を負荷としての保護すべき電気機器に
接続し、第3の外部端子を接地すると、負荷に対して正
特性サーミスタ素子が直列に、またバリスタ素子が並列
に接続されることになる。このように接続されることで
、正特性サーミスタ素子は負荷に対して過電流の保護機
能を発揮し、また、バリスタ素子はサージ電圧の保護機
能の発揮する。<Function> In the above configuration, if the first external terminal is connected to the input side, the second external terminal is connected to the electrical equipment to be protected as a load, and the third external terminal is grounded, the The positive temperature coefficient thermistor elements are connected in series, and the varistor elements are connected in parallel. By being connected in this manner, the positive temperature coefficient thermistor element exhibits an overcurrent protection function for the load, and the varistor element exhibits a surge voltage protection function.
〈実施例〉
以下、本発明を図面に示す実施例に基づいて詳細に説明
する。<Example> Hereinafter, the present invention will be described in detail based on an example shown in the drawings.
第1図は本発明の一実施例に係る複合電子部品の外観斜
視図、第2図はその本体部分の分解斜視図である。FIG. 1 is an external perspective view of a composite electronic component according to an embodiment of the present invention, and FIG. 2 is an exploded perspective view of its main body.
この実施例の複合電子部品は、正特性サーミスタ素子1
と、バリスタ素子2と、絶縁スペーサ3とを備える。こ
の実施例では、これら2種の素子1.2と絶縁スペーサ
3とは、いずれも同じ大きさの角板状で、また、2種の
素子1.2はいずれも複数である。そして、これら2種
の素子1.2と絶縁スペーサ3とは、2種の素子!、2
の間に絶縁スペーサ3を挟んだ状態で積層一体化されて
積層体チップに形成されている。この積層体の最外層に
は、それぞれカバ一体4.5が積層されている。The composite electronic component of this embodiment includes a positive temperature coefficient thermistor element 1
, a varistor element 2 , and an insulating spacer 3 . In this embodiment, the two types of elements 1.2 and the insulating spacer 3 are both square plate-shaped with the same size, and each of the two types of elements 1.2 is plural. And these two types of elements 1.2 and insulating spacer 3 are two types of elements! ,2
They are integrally laminated with an insulating spacer 3 sandwiched between them to form a laminated chip. A cover unit 4.5 is laminated on the outermost layer of this laminate.
図中、6は入力側に接続すべき第1の外部電極、7は負
荷側に接続すべき第2の外部電極、8は接地すべき第3
の外部端子で、これらの外部電極6゜7.8は、積層体
の互いに異なる側面部に形成されている。すなわち、第
1の外部電極6は、積層体の長手方向の一側面部に形成
され、第2の外部電極7は、積層体の長手方向の他方の
側面部に形成され、第3の外部電極8は、積層体の短手
方向の両側面部にそれぞれ形成されている。これら外部
電極6.7.8と各素子1.2との接続状態は後述する
。In the figure, 6 is the first external electrode to be connected to the input side, 7 is the second external electrode to be connected to the load side, and 8 is the third external electrode to be grounded.
These external terminals 6°7.8 are formed on different side surfaces of the laminate. That is, the first external electrode 6 is formed on one longitudinal side of the laminate, the second external electrode 7 is formed on the other longitudinal side of the laminate, and the third external electrode 7 is formed on the other longitudinal side of the laminate. 8 are formed on both side surfaces of the laminate in the transverse direction. The connection state between these external electrodes 6.7.8 and each element 1.2 will be described later.
正特性サーミスタ素子lは、第3図に示すように、角板
状のサーミスタ素体1aの両生表面にそれぞれ電極1b
、lcを形成したものであって、画電極1b 、Ic
は互いにサーミスタ素体1aの長手方向両端面に導出さ
れている。この実施例ではサーミスタ素体1aに、
(B ao、5ssY o、oos)T i+、ooa
o 3+ 0.5モル%MnOを材料とする、縦横7
mmX 10 +nm、厚さ0.4+nmの焼成済みの
角板を使用した。また、画電極1b。As shown in FIG. 3, the positive temperature coefficient thermistor element l has electrodes 1b on each of the amphibian surfaces of a rectangular plate-shaped thermistor body 1a.
, lc are formed, and the picture electrode 1b , Ic
are mutually led out to both end faces in the longitudinal direction of the thermistor body 1a. In this embodiment, in the thermistor element 1a, (B ao, 5ssY o, oos)T i+, ooa
o 3+ Made of 0.5 mol% MnO, vertical and horizontal 7
A fired square plate having dimensions of mmX 10 +nm and thickness of 0.4+nm was used. Moreover, the picture electrode 1b.
lcのうち、入力側の電極1bは一般的な電極で、銀を
主成分とする導電性ペーストを約800℃で焼き付けて
形成した。負荷側の電極1cはオーミック電極で、銀お
よび亜鉛を主成分とする導電性ペーストを約600℃で
焼き付けて形成した。The electrode 1b on the input side of the lc is a general electrode, and is formed by baking a conductive paste containing silver as a main component at about 800°C. The electrode 1c on the load side is an ohmic electrode, and is formed by baking a conductive paste containing silver and zinc as main components at about 600°C.
バリスタ素子2は、第4図に示すように、角板状のバリ
スタ素体2aの両生表面にそれぞれ電極2b 、2cを
形成したものであって、一方の電極2bは、正特性サー
ミスタ素子lの一方の電極lbと同一側であるバリスタ
素体2aの長手方向−端面に導出され、他方の電極2c
は、正特性サーミスタ素子!の画電極1b 、Icとは
異なる側の端面、すなわちバリスタ素体2aの短手方向
の両端面に導出されている。この実施例では、バリスタ
素体2aとして、
0.98Z no + 0.0Q5B two 3+
Q、005M n。As shown in FIG. 4, the varistor element 2 has electrodes 2b and 2c formed on the amphiboid surfaces of a square plate-shaped varistor element 2a, and one electrode 2b is connected to the positive temperature coefficient thermistor element l. It is led out to the end face in the longitudinal direction of the varistor body 2a on the same side as one electrode lb, and the other electrode 2c
is a positive characteristic thermistor element! The picture electrode 1b is led out to the end face on the side different from Ic, that is, to both end faces in the transverse direction of the varistor element body 2a. In this embodiment, as the varistor body 2a, 0.98Z no + 0.0Q5B two 3+
Q, 005M n.
+Q、Q05Cot03+0.005Sb20s(モル
比)を材料とし、正特性サーミスタ素体1aと同じ大き
さ、すなわち7mmX 10mmx O,4mmの焼成
済みの角板を使用した。また、各電極2b。+Q, Q05Cot03+0.005Sb20s (molar ratio) was used as the material, and a fired square plate of the same size as the positive temperature coefficient thermistor element 1a, that is, 7 mm x 10 mm x O, 4 mm, was used. Moreover, each electrode 2b.
2cは一般的な電極で、銀を主成分とする導電性ペース
トを約800℃で焼き付けて形成した。2c is a general electrode, which was formed by baking a conductive paste containing silver as a main component at about 800°C.
そして、正特性サーミスタ素子lとバリスタ素子2とは
、積層体内において第2図に明示するように、−枚毎に
反転して、互いに重なり合う素子l(または2)の間で
同一の端面に導出されている電極1b(またはlc 、
2b 、2c )どうしが対面するようにして、各電極
1b 、tc 、2b 、2cに半田ペーストを塗布し
、熱風処理により接合されている。Then, the positive temperature coefficient thermistor element l and the varistor element 2 are reversed one by one in the stacked body, as shown in FIG. electrode 1b (or lc,
Solder paste is applied to each electrode 1b, tc, 2b, 2c so that the electrodes 2b, 2c) face each other, and they are joined by hot air treatment.
カバ一体4.5としては、この実施例では、電極1b
、lc 、2b 、2cが形成されていないサーミスタ
素体1aもしくはバリスタ素体2aを用いているが、こ
のようなカバ一体を用いずに、正特性サーミスタ素子1
もしくはバリスタ素子2を積層体の最外層に位置させて
もよい。In this embodiment, the cover integral 4.5 includes the electrode 1b
, lc , 2b , 2c are not formed, but the positive temperature coefficient thermistor element 1 is used without using such an integrated cover.
Alternatively, the varistor element 2 may be located at the outermost layer of the laminate.
上記のように2種の素子1.2を向きを揃えて積層する
ことで、積層体の各側面部には各素子1゜2の電極1b
、Ic 、2b 、2cが上下に揃った状態で露出す
る。前記した外部電極6.7.8は、こh ラ(7)
ili極1b 、1c 、2b 、2c (1)N山部
を覆う形で積層体の各側面部に形成されて、対応する素
子1.2の電極1b 、lc 、2b 、2cに接続さ
れている。すなわち、第1外部電極6は、積層体の長手
方向の一方の側面部に形成されて、正特性サーミスタ素
子lの一方の電極1aとバリスタ素子2の一方の電極2
aとに共通に接続されている。第2の外部電極7は、積
層体の長手方向の他方の側面部に形成されて、正特性サ
ーミスタ素子lの他方の電極1cに接続されている。第
3の外部電極8は、積層体の短手方向両側面部に形成さ
れて、バリスタ素子2の他方の電極2Cに接続されてい
る。By stacking the two types of elements 1.2 in the same direction as described above, each element has an electrode 1b of 1°2 on each side of the stack.
, Ic, 2b, and 2c are exposed vertically aligned. The external electrode 6.7.8 described above is
ili electrodes 1b, 1c, 2b, 2c (1) Formed on each side surface of the laminate to cover the N peaks and connected to the electrodes 1b, lc, 2b, 2c of the corresponding element 1.2. . That is, the first external electrode 6 is formed on one side surface in the longitudinal direction of the laminate, and is connected to one electrode 1a of the positive temperature coefficient thermistor element l and one electrode 2 of the varistor element 2.
It is commonly connected to a. The second external electrode 7 is formed on the other longitudinal side surface of the laminate and is connected to the other electrode 1c of the positive temperature coefficient thermistor element l. The third external electrode 8 is formed on both side surfaces of the laminate in the transverse direction and is connected to the other electrode 2C of the varistor element 2.
以上のように接続することにより、第5図に示すような
等価回路の積層チップ型複合電子部品が得られる。By connecting as described above, a laminated chip type composite electronic component having an equivalent circuit as shown in FIG. 5 can be obtained.
上記の構成において、第1の外部電極6を入力側に接続
し、第2の外部電極7を負荷としての保護すべき電気機
器に接続し、第3の外部電極8を接地すると、負荷に対
して正特性サーミスタ素子lが直列に、またバリスタ素
子2が並列に接続されることになる。このように接続さ
れろことで、正特性サーミスタ素子lは負荷に対して過
電流保護機能を発揮し、またバリスタ素子2はサージ電
圧保護機能の発揮する。In the above configuration, when the first external electrode 6 is connected to the input side, the second external electrode 7 is connected to the electrical equipment to be protected as a load, and the third external electrode 8 is grounded, the Thus, the positive temperature coefficient thermistor element 1 is connected in series, and the varistor element 2 is connected in parallel. By connecting in this manner, the positive temperature coefficient thermistor element 1 exhibits an overcurrent protection function for the load, and the varistor element 2 exhibits a surge voltage protection function.
上記実施例の複合電子部品について、第1の外′部電極
6を+側として、正特性サーミスタ素子lとバリスタ素
子2の特性の測定を行ったところ、正特性サーミスタ素
子lについては、第6図に示すような電圧電流特性が得
られた。この特性図からも明らかなように、0.3Aま
での電流制限効果が認められる。また、バリスタ素子2
については、V (1mA)= 70V、α=15の値
が得られた。Regarding the composite electronic component of the above example, when the characteristics of the positive temperature coefficient thermistor element l and the varistor element 2 were measured with the first external electrode 6 on the + side, it was found that the positive temperature coefficient thermistor element l had the sixth The voltage-current characteristics shown in the figure were obtained. As is clear from this characteristic diagram, a current limiting effect up to 0.3 A is observed. In addition, varistor element 2
For V (1 mA) = 70 V, α = 15 values were obtained.
なお、実施例では、正特性サーミスタ素子lの負荷側の
電極1cのみをオーミック電極としたが、正特性サーミ
スタ素子1の他方の電極1bや、バリスタ素子2の画電
極2b 、2cをオーミック電極としてもよい。また、
正特性サーミスタ素子lにP bT io、系やv、0
3系の材料、バリスタ素子2にS rT to、系やT
ies系の材料を用いてもよい。In the embodiment, only the electrode 1c on the load side of the positive temperature coefficient thermistor element 1 was used as an ohmic electrode, but the other electrode 1b of the positive temperature coefficient thermistor element 1 and the picture electrodes 2b and 2c of the varistor element 2 could be used as ohmic electrodes. Good too. Also,
Positive characteristic thermistor element l has P bT io, system and v, 0
3-based materials, S rT to, varistor element 2, and T
ies-based materials may also be used.
〈発明の効果〉
以上のように、本発明によれば、単一の電子部品で過電
流の保護機能とサージ電圧の保護機能とを発揮するから
、従来のように2種のディスクリート部品で過電流とサ
ージ電圧との保護を行う場合に比べ、接続作業が容易で
、また、取付スペースも少なくて済む。<Effects of the Invention> As described above, according to the present invention, a single electronic component provides an overcurrent protection function and a surge voltage protection function. Compared to protection against current and surge voltage, the connection work is easier and requires less installation space.
第1図は本発明の一実施例の外観斜視図、第2図はその
本体部分の分解斜視図、第3図は正特性サーミスタ素子
の斜視図、第4図はバリスタ素子の斜視図、第5図は等
価回路図、第6因は正特性サーミスタ素子部分の電圧電
流特性図である。
■・・・正特性サーミスタ素子、2・・・バリスタ素子
、3・・・絶縁スペーサ、6・・・第1の外部電極、7
・・・第2の外部電極、8・・・第3の外部電極。Fig. 1 is an external perspective view of an embodiment of the present invention, Fig. 2 is an exploded perspective view of its main body, Fig. 3 is a perspective view of a positive temperature coefficient thermistor element, Fig. 4 is a perspective view of a varistor element, and Fig. 4 is a perspective view of a varistor element. FIG. 5 is an equivalent circuit diagram, and the sixth factor is a voltage-current characteristic diagram of the positive temperature coefficient thermistor element portion. ■... Positive temperature coefficient thermistor element, 2... Varistor element, 3... Insulating spacer, 6... First external electrode, 7
. . . second external electrode, 8 . . . third external electrode.
Claims (1)
、これら2種の素子を絶縁スペーサを介して積層一体化
し、各素子の一方の電極を、該2種の素子と絶縁スペー
サとからなる積層体の同一の側面部に導出して第1の外
部端子に共通に接続し、各素子の他方の電極をそれぞれ
積層体の互いに異なる側面部に導出して第2もしくは第
3の外部端子に接続したことを特徴とする複合電子部品
。(1) A positive temperature coefficient thermistor element and a varistor element are provided, these two types of elements are laminated together via an insulating spacer, and one electrode of each element is connected to a laminate consisting of the two types of elements and the insulating spacer. The electrodes are led out to the same side surface and commonly connected to the first external terminal, and the other electrodes of each element are led out to mutually different side surfaces of the laminate and connected to the second or third external terminal. A composite electronic component featuring:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62313689A JPH01152704A (en) | 1987-12-10 | 1987-12-10 | Composite electronic component |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62313689A JPH01152704A (en) | 1987-12-10 | 1987-12-10 | Composite electronic component |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01152704A true JPH01152704A (en) | 1989-06-15 |
Family
ID=18044330
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62313689A Pending JPH01152704A (en) | 1987-12-10 | 1987-12-10 | Composite electronic component |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01152704A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH058906U (en) * | 1991-07-18 | 1993-02-05 | 株式会社村田製作所 | Surge absorber with built-in resistor |
EP0548606A2 (en) * | 1991-12-21 | 1993-06-30 | Asea Brown Boveri Ag | Resistance with PTC-behaviour |
EP0576836A2 (en) * | 1992-06-29 | 1994-01-05 | Abb Research Ltd. | Current limiting element |
WO2020149034A1 (en) * | 2019-01-16 | 2020-07-23 | パナソニックIpマネジメント株式会社 | Varistor assembly |
-
1987
- 1987-12-10 JP JP62313689A patent/JPH01152704A/en active Pending
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH058906U (en) * | 1991-07-18 | 1993-02-05 | 株式会社村田製作所 | Surge absorber with built-in resistor |
EP0548606A2 (en) * | 1991-12-21 | 1993-06-30 | Asea Brown Boveri Ag | Resistance with PTC-behaviour |
EP0548606A3 (en) * | 1991-12-21 | 1994-04-06 | Asea Brown Boveri | |
EP0576836A2 (en) * | 1992-06-29 | 1994-01-05 | Abb Research Ltd. | Current limiting element |
EP0576836A3 (en) * | 1992-06-29 | 1994-07-13 | Abb Research Ltd | Current limiting element |
WO2020149034A1 (en) * | 2019-01-16 | 2020-07-23 | パナソニックIpマネジメント株式会社 | Varistor assembly |
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