JPH01151805A - Delay element - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a delay element, in order to determine the delay time at the mounting stage after manufacturing and to achieve low mounting, a delay line pattern is formed on the surface of the substrate main body, and its end is connected to the substrate. A delay line pattern board formed facing the side of the main body,
a board assembly formed by alternately stacking earth pattern boards each having a ground pattern formed on the surface of the board body; and connecting the ends of each of the delay line patterns to the side surface of the board assembly; and a wiring pattern formed of a pattern that can exclude delay line patterns other than the desired delay line pattern from between the input and output by cutting at a predetermined location,
The above-mentioned wiring pattern is configured to be used by cutting it at a predetermined location as appropriate.

[Industrial application field]

The present invention relates to delayed aggregators.

[Conventional technology]

In conventional delay elements, the delay time is determined at the manufacturing stage.
The structure is such that the delay time cannot be determined after manufacturing.

Furthermore, conventional delay collectors are of II4 construction, in which the leads are inserted into holes in the printed circuit board and mounted standing up on the printed circuit board.

[Problem that the invention seeks to solve]

For this reason, manufacturers need to manufacture many types of delay collectors to match the required delay times, and users also need to prepare many types of delay elements to match the required delay times. There was a cost problem.

Furthermore, the mounting height of the delay element becomes high, which hinders miniaturization of the module in which the delay A element is mounted.

The present invention has 1! It is an object of the present invention to provide a delay element I that can determine the delay time at the stage of implementation after construction and can be implemented at a low value.

[Means for solving problems]

The present invention provides a delay line pattern board in which a delay line pattern is formed on the surface of a board main body with its end facing the side surface of the board main body, and an earth pattern board in which a ground pattern is formed on the surface of the board main body. A board assembly formed by alternately stacking 1 and 1, and a desired delay line between input and output by connecting the ends of each of the above delay line patterns to the side surface of the board assembly and cutting at predetermined locations. It consists of a wiring pattern formed of a pattern that can exclude delay line patterns other than the pattern, and is configured to be used by appropriately cutting the wiring pattern at a predetermined location.

[Effect]

By cutting the above wiring pattern at a predetermined location, it is possible to leave a predetermined delay line pattern among the plurality of delay line patterns between the input terminal and the output terminal, and when mounting the delay element on a printed circuit board. It becomes possible to determine the delay time of

As a result, each person manufacturing the delay A element only needs to manufacture one type of delay collector, and the user of the delay element only needs to prepare one type of delay element.

In a configuration in which the main body is a substrate assembly, the delay element r is chip-shaped, and the mounting height can be reduced.

〔Example〕

FIG. 2 shows the delay element f1 of the first embodiment of the present invention, and the first
The figure shows the delayed A element 1 in an exploded manner.

The delay element 1 is of a distributed constant type, and as shown in FIG. The main body is a stacked board assembly 1o, and a plurality of leads 11, 12, 13 are provided around the main body.

This delay collector 1 has a substrate assembly 10 in the form of a chip with a small height, and is configured to be surface-mountable using leads 11.about.12.13.

The delay element 1 is mounted on a circuit board (not shown) by soldering the leads 11, 12, and 13 to corresponding electrode pads (not shown), and the mounting height is lower than that of conventional devices, resulting in low mounting. It has become.

Furthermore, as will be described later, the delay line pattern is three-dimensional, and the planar size of the delay concentrator 1 is also small.

The delay line pattern board 2 has a ceramic board body 20.
Upper surface 20a1. : This is a configuration in which a delay line pattern 21 is formed. The end portions 21a and 21b of the delay line pattern 21 are located on the side surfaces 20bl, :fl)a of the substrate body 20.

On the side surface 20b, as shown in FIG.
3, 24. 25a-28a are formed in a comb-teeth shape. The intersection between the end portion 21a and the wiring portion 22.23°26a is electrically connected, and the intersection between the end portion 21b and the wiring portion 24.278 is electrically connected.

The delay line pattern board 3.4 is also the same as the delay line pattern board 2.
It has a similar configuration.

The delay line pattern board 3 has a delay line pattern 31 on the top surface 30a of the ceramic substrate main body 30, and an end portion 31a of the delay line pattern 31 on the side surface 30b.

31b and the wiring portions 32, 33, 34° 35
This is a configuration in which a to 38a are formed.

The delay line pattern board 4 has a delay line pattern 41 on the top surface 40a of the ceramic substrate main body 40, and an end portion 41a of the delay line pattern 41 on the side surface 40b.

41b and the wiring part 42, 43, 44° 45
a, 46a are formed.

The delay line patterns 21, 31, and 41 have different lengths.

The earth pattern board 6 has a ground pattern 51 on substantially the other side of the upper surface 50a of the ceramic substrate main body 50, and wiring portions 25b to 28b on the side surface 50b crossing this.

The earth pattern board 7 also has a ground pattern 53 on the top surface 52a of the ceramic substrate main body 52, and arrangement portions 35b to 38b on the side surface 52b.

The ground pattern board 8 has a ground pattern 55 on the top surface 54a of the ceramic board main body 54, and a wiring section 4 on the side surface 54b.
5b and 46b.

Wiring portions 25b to 28b, 35b to 38b, 45b.

46b corresponds to the wiring portions indicated by the same reference numerals with the suffix 1'a''.

The ground pattern board 5 has a ground pattern 57 on the top surface of a ceramic board body 56.

Delay line pattern substrates 2 to 4 above. When the ground pattern boards 5-8 are stacked, the delay line pattern 41 and the ground patterns 53 and 55 sandwiching it from above and below constitute a distributed constant type first delay line element section 61, and the delay line pattern 31
and ground patterns 51 and 53 that sandwich this from above and below constitute a distributed constant type second delay line element section 62, and a ground pattern 57 that sandwiches this from the delay line pattern 21 and this from above)
51 constitutes the distributed constant type third delay line element section 63.

The delay time of each delay line element section 61, 62, 63 is TI,
T2 and T3, which are different from each other.

In the wiring part, the parts indicated by the same numerals of subscript "a-1" and subscript "b" are aligned, and the side surface 10a of the board assembly 10 has a first
A lattice-like wiring pattern 64 as shown in the enlarged view in the figure and FIG. 4 is formed. Note that the aligned wiring portions are denoted by symbols without subscripts.

The input lead 11. is connected to the wiring section 45. The output lead 12 is connected to the wiring section 46 .

Moreover, each 7-spattern 51.53, 55.57 is the second
As shown in the figure, the wiring patterns 65 are connected at a plurality of locations on the side surface of the board assembly 10. The 7-thread 13 is connected to the lower end of the wiring pattern 65.

Manufacturers of delay elements produce only one of the above types. Therefore, it is easier to manufacture than when manufacturing multiple types.

Next, a description will be given of how to determine the delay time when mounting the delay element after manufacturing it.

The delay time is adjusted by cutting a predetermined portion of the wiring pattern 64 using a laser or the like.

Note that the cut points are indicated by "x" marks. Add hatching to the conductive parts.

■ When trying to set the delay time to TI +T2 +T3 As shown in FIG. 5, the wiring portions 23.33.34.35.
Cut 36.43.44.

As a result, the input lead 11 includes the wiring portion 45° 42, the delay line pattern 21, the wiring portion 38, the delay line pattern 31, the wiring portion 26, the delay line pattern 21, the wiring portion 24, 27, . ．．
37. Conducts with the output lead 12 through 46.

There are delay line patterns 41.31.21 in the middle, and the delay time becomes T1→T2-1T3.

■ When the delay time is set to T++-rz As shown in FIG. 6, the wiring portions 26, 27.28° 32.34°.
43 and 44 so that the delay line pattern 21 is not used.

Delay line patterns 41 and 31 are provided between the input lead 11 and the output lead 12, and the delay time is TI''T2.

■ When trying to set the delay time to TI + T3 As shown in FIG. 7, the wiring sections 22, 24. ．． 33°34.35
．． 36, 43, and 44 so that the delay line pattern 31 is not used.

There are delay line patterns 41 and 21 between the input lead 11 and the output lead 12, and the delay time is T++-r3.

■ When trying to set the delay time to T2+T3, as shown in FIG.
6.38.42 is cut and the delay line pattern 41 is not used.

There are delay line patterns 31 and 21 between the input lead 11 and the output lead 12, and the delay time becomes T2→-T3.

(2) When trying to limit the delay time to TI As shown in FIG. 9, the wiring portions 35, 36, 37, 38, 43 are cut so that the delay line patterns 21, 31 are not used.

Only the delay line pattern 41 is provided between the input lead 11 and the output lead 12, and the delay time is "1".

■ When trying to set the delay time to ■ 2, as shown in FIG.
38.42.43゜Cut 44, delay line pattern 21
．． Avoid using 41.

Only the delay line pattern 31 is provided between the input lead 11 and the output lead 12, and the delay time is [2].

■ When the delay time is set to T3 As shown in FIG.
Cut 42.43.44 and delay line pattern 31.41
Avoid using.

Only the delay line pattern 21 is provided between the input lead 11 and the output lead 12, and the delay time is 1-3.

After the delay element 1 is cut as described above and the delay time is set to the required delay time, it is mounted on a circuit board and used as described above.

Next, FIG. 12 shows a second embodiment of the present invention.

This will be explained with reference to FIGS. 13 and 14.

FIG. 13 shows the delay element 70, and FIG. 12t shows it exploded. FIG. 14 shows wiring patterns 71A and 71B. In FIG. 12, components that are substantially the same as those shown in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted.

72, 73, and 74 are delay line pattern substrates, and delay line patterns 78, 79, and 80 are formed on ceramic substrate bodies 75, 76, and 77, respectively.

One end 78a, 79a of delay line patterns 78-80.

80a faces the same position on the same side of the ceramic substrate body 75, 76, 77, and the other ends 78b, 79b.

80b faces the same position on the opposite side to the above-mentioned side.

The delay line patterns 78, 79, and 80 have different lengths,
The first delay line element section 81, the second delay line element section 82, and the third delay line element section 83 each have different delay times T+-+,
Ding 2-1. Turn T3-+ to the right.

The wiring pattern 71A is connected to the - side surface 84 of the board assembly 84.
a, and the wiring pattern 71B is formed on the side surface 84.
It is formed on the side surface 84b opposite to the side surface 84b.

The wiring pattern 71A has a roughly comb-like shape, and the wiring portion 85
．． 86, 87.88. Wiring section 85.86.8
The tip of 7 is a large delay line pattern 78.79.80 17
8a, 79a, and 80a. The input lead 11 is connected to the wiring portion 88 .

The wiring pattern 71B has a substantially single-character shape and includes a wiring portion 89. Here is the edge 7 of the delay line pattern 78°79.80
8b, 79b, and 80b are connected, and the output lead 12 is attached.

In the above-mentioned delay element 70, when attempting to close the delay time to T+-+, the wiring portions 86 and 87 are cut with a laser or the like.

As a result, only the delay line pattern 78 remains between the input and output leads 11 and 12, and the delay time becomes T1-1.

When trying to set the delay time to T2-1, the wiring section 8
Cut 5.87.

As a result, only the delay line pattern 79 remains between the input and output leads 11 and 12, and the delay time becomes T2-1.

When trying to set the delay time to T3-1, the wiring section 8
Cut 5.86.

As a result, only the delay line pattern 80 remains between the input and output leads 11 and 12, and the delay time becomes T3-1.

Next, a third embodiment of the present invention will be described with reference to FIGS. 15 and 16.

FIG. 16 shows the delay element 90, and FIG. 17 shows it exploded. In FIG. 17, the same components as those shown in FIG. 12 are designated by the same reference numerals, and their explanations will be omitted.

The delay element 90 (board assembly 84A) has the delay line pattern board 73 in FIG. 12 rotated 90 degrees to change its orientation, and has wiring patterns 91° 92 for the delay line patterns 78 and 80 on the side surface 84Aa. This configuration has separate wiring patterns 93 and 94 for the delay line pattern 79.

11.118 is an input lead, and 12.12a is an output lead.

By appropriately cutting the wiring pattern 91, this delay element 90 can be configured to have a delay time T+ between the input and output leads 11 and 12.
4 or 34, and has a delay time T2 (between the input and output ports 11a and 12a. That is, the delay element 9
According to 0, two types of delay times can be handled by one delay element.

Note that the direction of the delay line pattern board 73 may be changed by rotating it by 180 degrees.

Further, in each of the above embodiments, the leads 11, 12, 13 may be omitted, and the lower edge of the wiring pattern may be soldered to the electrode pad on the circuit board.

〔Effect of the invention〕

As explained above, according to the present invention, the delay time can be determined after manufacturing, so that the manufacturer only needs to manufacture one type of delay element, and the user only needs to use one type of delay element. It is also more economical than manufacturing or preparing multiple types.

In addition, the shape is convex, making it compact and reducing the mounting height.

[Brief explanation of the drawing]

Fig. 1 is an exploded perspective view of the first embodiment of the delay element of the present invention, Fig. 2 is a perspective view of the first embodiment of the delay element of the present invention, and Fig. 3 corresponds to the wiring portions on the sides of each board. FIG. 4 is a diagram showing the wiring pattern on the side surface of the delay element together with the delay line pattern; FIGS. 5 to 11 are diagrams showing cutting points when determining the delay time, and FIG. The figure is an exploded perspective view of the second embodiment of the delay element of the present invention, Figure 13 is a perspective view of the second embodiment of the delay element of the present invention, and Figure 14 is a diagram showing the wiring pattern together with the delay line pattern. , FIG. 15 is an exploded perspective view of a third embodiment of the delay element of the present invention, and FIG. 16 is a perspective view of a third embodiment of the delay element of the present invention. In the figure, 1.70.90 is a delay element, 2.3.4.72, 73.74 are delay line pattern boards, 5 to 8 are ground pattern boards, 10.84.84A is a board assembly, 10a, 84a , 84Aa is the side surface, 11.11a, 11b are input leads, 12.12a, 12bG are output leads, 13 is ground lead, 20.30.40.50, 52.54.56°72.7
6.77 is the board body, 21.31, 41, 78.79.80 is the delay line pattern, 21a, 21b, 31a, 31b, 41a, 41b. 78a, 78b, 79a, 79b, 80a, 80b are the ends, 22~28.32・~38.42~46.85~8 are the wiring parts, 51.53.55.57 are the ground patterns, 61.81
62.82 is a second delay line element portion; 63.83 is a third delay element portion; 64.65.71A, 71B, and 91 to 94 are wiring patterns. 1 孜runner Shimo (Shout out 10 groups) Happy i Nu 帛 3 fig.
)! Near 7 qm T map 'A 7- Sui k1 map tribute story 2-n [Bakuo map 414 diagram 16 Z

Claims (1)

[Claims] Delay line patterns (21, 31, 41, 78, 79,
80) has its ends (21a, 31a, 41a, 78a,
79a, 80a) on the sides (20b, 30b) of the substrate body.
, 40b) formed so as to face the delay line pattern substrate (
2, 3, 4, 72, 73, 74) and the board body (50,
Earth pattern (51, 53, 5) on the surface of
5) on which the earth pattern board (5, 6, 7, 8
) are alternately stacked (10, 84, 8).
4A) and the side surfaces (10a, 84A) of the substrate assembly (10, 84, 84A).
84a, 84Aa), a pattern is formed in which delay line patterns other than the desired delay line pattern can be excluded from between the input and output by connecting the ends of each of the delay line patterns and cutting at a predetermined location. Wiring pattern (64,
71A, 91), and is used by appropriately cutting a predetermined portion of the wiring pattern.