JPH01149153A - Address converting index mechanism invalidating device - Google Patents

Abstract

PURPOSE:To attain a high speed by invalidating only the virtual address and the real address stored by an address converting index mechanism corresponding to an entry coinciding with the one part of the virtual address. CONSTITUTION:Initially, the number of an ATR in which a value is changed (section number) is transferred to a register VAR 202 through a VA bus 201. The section number temporarily stored in the VAR 202 is transferred to an associative memory RM 208 through a bus 203. Then, the RM 208 compares the section number fed from the bus 203 with the section number stored in the respective entries of the RM 208, when they coincide, a coincidence number 209 is made active, fed to the reset terminal of the propriety bit of an associative memory AM 211 and the propriety bit of the entry corresponding to the AM 211 is reset.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a central processing unit in an information processing apparatus, and more particularly to an address conversion indexing mechanism for a central processing unit that employs a multiple virtual memory system.

Conventional technology Traditionally, in central processing units that employ multiple virtual memory systems, exceptions and interrupts occur during instruction execution, and tasks are switched.
When the virtual address space was also switched at the same time, it was necessary to erase the address translation lookaside mechanism (hereinafter abbreviated as TLB).

The following two methods can be considered for erasing.

1st: Erase all TLB entries.

2nd = A method of providing a deletion function for 1 entry, checking whether it belongs to the virtual space to be switched using a MyAlo program, and deleting it if it belongs.

FIG. 6 is a block diagram of the first method described above. Figure 6 shows the TL of the 16-count full associative system.
We assume B. In FIG. 6, when the virtual space is switched, the reset signal 608 is activated by a microinstruction, the reset terminal of all validity bits 609 of the associative memory is activated, and the reset terminal of all validity bits 609 of the associative memory is activated.
is cleared.

FIG. 7 is a block diagram of the second method. This diagram assumes a 16-count full associative type TLB. In FIG. 7, validity bit 7 of the associative memory
11 can be reset independently by each microinstruction. When the virtual space is switched, the microprogram reads the virtual address of each entry in the TLB, and if the virtual address is different from the new virtual space, a clear microinstruction corresponding to that entry is issued and the microinstruction decoder 709 issues a clear microinstruction corresponding to the entry. The decoding is performed and one of the reset signals 710 of the corresponding validity bit 711 is activated to clear the corresponding validity bit 711.

Repeat the above for all IJs of TLB.

Problems to be Solved by the Invention In method l mentioned above, the TL is changed every time the virtual space is switched.
Since all entries in B are erased, the performance (bit rate) of the TLB decreases. On the other hand, switching between virtual spaces does not take much time.

On the other hand, in the method 2 mentioned above, since it is controlled by a microprogram, erasing takes time. That is, it takes time to switch virtual spaces. However, the bit rate of the TLB does not decrease much with method 1.

In this way, in the past, TLB only had the function to clear all entries or clear one entry.
Clearing the entire TLB reduces the bit rate of the TLB, and selectively clearing one entry at a time using a microprogram of the central processing unit takes time.

Therefore, it is an object of the present invention to provide an address translation index mechanism invalidation device that can quickly clear unnecessary entries in the TLB.

Means for Solving the Problems According to the present invention, in an information processing device that employs a multiple virtual memory system and is equipped with an address translation indexing mechanism, a virtual address match comparison function at the time of address translation allows a virtual address to be matched with a matching entry. In addition to the means to read the address,
a part of virtual address matching comparison means, and the part of virtual address matching comparing means selects only the virtual address and real address stored in the address translation indexing mechanism corresponding to the entry that matches the part of the virtual address. An address translation indexing mechanism invalidating device is provided.

Function The present invention is equipped with dedicated hardware that selectively clears unnecessary TLB entries, so the TLB can be cleared at high speed.
Unnecessary entries in B can be cleared.

Embodiments Hereinafter, embodiments of an address translation indexing mechanism disabling device according to the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a diagram showing the process of address translation in an embodiment of the present invention.

In FIG. 1, reference number 101 is a register (VAR) for storing a virtual address.
IOI has four registers (ATRO-3) 102 for storing the base address and length of the area table.
is included. VARIOI is A of VARIOI
Field Y103 specifying TRO-3 and VARIO
A field 104 specifying the area number of I, VA
”Field 105 for specifying the RIOI page number
and a field 106 indicating the offset within the page of VARIOI.

Furthermore, the area table register 102, ATRO-3 has a field 10 indicating the area table base address.
7.

The area table 109 of JR University 1024 entries has a configuration of area table entries as indicated by reference number 108.

The page table 111 with a maximum of 256 entries has a configuration of page table entries as indicated by reference number 110.

Reference number 112 is a field indicating the page table base of the area table entry, and reference number 113 is a field indicating the actual page number of the page table entry. Furthermore, a main storage device 114 is provided.

FIG. 2 shows an address conversion indexing machine in an embodiment of the present invention!
(TLB) is a block diagram.

In FIG. 2, a bus 201 for transferring virtual addresses to the TLB is coupled to registers VA and R 202 for storing virtual addresses.

The V A R 202 has a field 203 for specifying the section number of the virtual address, a field 204 for specifying the offset within the page of the virtual address, and others.

On the other hand, the bus 205 that specifies the register address for reading/writing each en) IJ in the TLB is
It is coupled to a decoder 206 that decodes register addresses, and information 207 decoded by the address decoder 206 is coupled to a content addressable memory (hereinafter abbreviated as RM) 208 that clears sections.

RM2O3 outputs a reset signal 209 for the validity bit of the associative memory AM211, which will be described later. This AM21
1 has a beep) 210 indicating the validity of the contents of each en) +7 of AM211.

When it is “1”, the entry is valid, 0'', the entry is invalid.

A bus 212 that includes a portion of the V A R 202 other than the intra-page offset is coupled to the AM 211 . This AM2
11 stores the portion of the virtual address other than the intra-page offset, and when converting the address, compares it with the portion other than the intra-page offset of the virtual address stored in the V A R 202, and if they match, sends a match signal 213 to the 9M 214. This is an associative memo 'J (abbreviated as AM).

The 9M214 is a memory for storing real addresses corresponding to virtual addresses stored in the AM211. 9M214 contains the register RARO value.
A bus 215 for transferring to 14 is coupled. The bus 215 is coupled to a register (hereinafter abbreviated as RAR) 216 for storing a real address at the time of address conversion/reading/writing of the DM 214. The RA R 216 is coupled to the in-page offset field 204 of the MAR 202 and is further coupled to a bus 218 for transferring real addresses to the RAR.

FIG. 3 is a block diagram of content addressable memories RM and AM in the embodiment of the present invention.

As shown in FIG. 3, a bus 30 specifies the register address when reading/writing each end IJ of the TLB.
1 is a decoder 302 that decodes register addresses;
is connected to the input of The information 303 decoded by the decoder 302 is an associative memo for clearing each section! They are connected to JRMO to RMI5304, respectively.

The reset signal 305 output by each RM3O4 is
Validity Pip indicating the validity of the content of each entry in the associative memo IJAM) V. −v , , 306 is manually operated.

When the validity bit 306 is "l", the entry is valid, and when it is "0", the entry is invalid.

A bus 307 for transferring parts other than the intra-page offset of the virtual address from the M A R 202 is an associative memory A M3O for reading/writing/comparing numbers.
It is connected to 8. This AM3O8 is in AM.

Stores the part of the virtual address other than the in-page offset,
During address conversion, the virtual address stored in the VAR is compared with the part other than the intra-page offset, and if they match, a match signal 309 is sent to the 9M214. Those matching signals 3
09 is connected to a gate 310 that ORs the decoded information of the address decoder and the AM coincidence signal, and the OR output signal is outputted to the DM via the bus 311.

FIG. 4 is a diagram showing the configuration of the validity bit and other bits of the associative memory in the embodiment of the present invention.

In FIG. 4(a), the validity bit includes a word line 401 that specifies IJ when reading/writing AM, a match signal line 402 that is output during address conversion, and /Write/- A data line 403 for comparing numbers and a validity bit reset signal 404 are connected.

Figures 4 and 4) show the validity bits of the associative memory, including the word line 40 which specifies the entry of the AM when reading/writing the AM.
5 and a match signal line 406 output during address conversion.
and a data line 407 for reading/writing/comparing numbers are connected to AM.

FIG. 5 is a detailed diagram of the bit shown in FIG. 4(b),
As shown in the figure, MOSFETs are connected and configured. The illustrated bits are a data line 501 when reading/writing/-number comparison to AM, and a word line 501 specifying an entry of AM when reading/writing AM.
02 and a match signal line 503 output during address conversion.
Furthermore, the match signal line 503 is connected to the bit via a comparator (exclusive OR) 504 that performs a match comparison during address conversion.

FIG. 10 is a diagram showing an example of multiple virtual address spaces in an embodiment of the present invention.

In FIG. 10(a), reference number 1001 indicates a virtual space. One virtual space is 4 gigabytes.

Reference number 1002 indicates a section, and one section is 1 gigabyte.

Reference number 1003 indicates an area, and one area is 1 megabyte.

Reference number 1004 indicates a page, and one page is 4 kilobytes.

In FIG. 11(5), reference number 1005 is a field that specifies the section number of the virtual address.

Reference number 1006 is a field that specifies the area number of the virtual address, and reference number 1007 is a field that specifies the page number of the virtual address.

Reference number 1008 is a field that specifies the intra-page offset of the virtual address.

First, the configuration of the virtual space and the process of address translation will be explained with reference to FIGS. 1 and 10.

In this embodiment, one virtual space consists of four sections as shown in FIG. 10(a). One virtual space is 4
It has a size of gigabytes, and one section has a size of 1 gigabyte. One section consists of 1024 areas. The area has a size of 1 megabyte. One area consists of 256 pages. A page has a size of 4 kilobytes.

FIG. 10 et al.) shows the structure of each field of the virtual address. Field 1005 specifying the section number is 2
A field 100 that is a bit and specifies the area number.
6 is 8 bits. Further, the field 1007 for specifying the page number is 10 bits, and the field 1008 for specifying the intra-page offset is 12 bits.

In this embodiment, a paging-based virtual memory method is adopted,
Inside the central processing unit is a virtual address register VAR101,
Built-in area table register ATRO-3102,
An area table 109 and an R-table 111 are set in the main memory. Area table 109 is composed of area table entries 108, and page table 1
11 is composed of a page table entry 110.

In normal address translation, a virtual address is latched into V A R 202 through bus 201 .

In the virtual address, bits 31 to 30 (hereinafter abbreviated as section number) are a field 103 that specifies one of ATRO-3, and ATRO-3 is selected.

The specified ATRO-3 indicates the base address and length of the area table and bits 29-20 of the right VAR.
(hereinafter abbreviated as area number) is within the specified length range. If it is within the range, the area table entry 108 specified by the area number of the area table 109 is read.

The read area table entry indicates the base address and length of the page table, and it is checked whether dots 19-12 (hereinafter abbreviated as page number) of the VAR 202 are within the specified range. If it is within the range, the page table entry 110 specified by the page number of the page table 111 is read.

Read page table entry, real page number 1
13, and this real page number and bits 1l-0 of VAR (hereinafter abbreviated as intra-page offset) 106 constitute a real address, and the host device! 114 data is accessed.

At this point, an interrupt, exception, etc. occurs and the task is switched.
At the same time, when the virtual address space is switched, the value of ATRO-3 is changed, and the area table and page table referred to during address translation are switched.

The above is the process of address conversion, but if the above table is referred to every time the main memory is accessed, the performance of the central processing unit will deteriorate. For this purpose, a translation address lookaside (TLB) is typically used.

TLB is AM211, DM214 as shown in Figure 2.
16 recently referenced virtual address, real address pairs
It is now possible to store even pairs, and frequently referenced virtual addresses can be translated at high speed using the TLB.

Next, the operation of the TLB will be explained with reference to FIG.

In normal address translation, the virtual address 201 is transferred to the V A R 202 via the bus. VAR20
Of the virtual address stored in the DM 2, the portion other than the intra-page offset is transferred to the AM 211 via the bus 212, and compared with the virtual address and real address pair stored in the AM 211, and a match signal 213 is sent to the DM 214. sent to. The DM 214 reads out the real address of the entry corresponding to the match signal 213, outputs it to the bus 215, and stores it in the RAR 216.

And the in-page offset 204 of M A R 202
Together with this, the real address is configured and output to the bus 218.

The details of the timing are shown in FIG. As can be seen from the timing diagram of FIG. 8, address translation using this TLB is performed in two clocks. If the TLB is not hit, the microprogram of the central processing unit reads the area table and page table, replaces the TLB,
Perform address translation. The address conversion time at this time is T
This requires more than 10 times the time required for biting LB.

By storing pairs of virtual addresses and real addresses in the TLB in this way, address translation can be greatly speeded up.

Although this TLB has a small capacity (16 entries in this embodiment), it stores recently referenced virtual addresses and real address pairs (LRU algorithm), and the bits in the TLB are 97-99% due to the local referentiality of the program. .

However, tasks are switched due to interrupts, exceptions, etc.
When the virtual address space is also switched, the value of ATRO-3 is also changed, and the area table and page table referred to during address translation are also switched. The information stored in the TLB at this time is from the previous virtual address space,
It is necessary to clear the contents of TLB. Conventionally, all TLB entries were cleared, but in the present invention, ATRO-3
Only the TLB entries belonging to the ATR whose value has changed are cleared. TLB clear is 1
Approximately 1% if all entries are cleared every 0000 references
It is known that the bit rate of TLB decreases. In order to prevent this bit rate from decreasing, in the present invention, rather than clearing all entries, the TLB belonging to the ATR whose value has changed is
En) It is designed to clear only IJ (hereinafter abbreviated as section clear).

This TLB section clearing operation will be explained with reference to FIGS. 2 and 8.

In Figure 2, RM2O3 is AT of V A R202
Field specifying one of RO-3, bit 3l-3
It is an associative memory that stores 0 (section number) and has the function of comparing it with the section number of the V A R 202. The match signal 209 of this RM2O3 is connected to the reset/top terminal of the validity bit 210 of AM211.

Here, RM2O3 is the same as bits 31-30 (section number) of the virtual address stored in AM211,
The copy is memorized.

When switching the virtual address space, the microprogram of the central processing unit switches the old virtual address space ATRO-
The value of 3 is compared with the value of ATPO-3 in the new virtual address space, and an ATR whose value has changed is detected. This clears the TLB entry belonging to the ATR whose value has changed.

First, enter the ATR number (section number) whose value has changed by
The data is transferred to the MAR 202 through the AB bus 01. V
The section number stored in AR202 is transferred to RM2O3 via bus 203. RM208 is the section number sent from bus 203 and RM20
Compare the section numbers stored in each entry of 3 and if they match, activate the match signal 209 and
AM2 is sent to the reset terminal of the validity bit of M211.
The validity bits of the 11 corresponding entries are reset.

Details of the timing are shown in FIG. As shown in this figure, two clocks are required to clear the TLB entry belonging to one section. This is much faster than clearing each entry one by one using the microprogram of the central processing unit, and at this time, it is faster than clearing the entire TLB.
Clearing only the TLB entries belonging to the ATR whose value has changed in RO-3 improves TLB performance (bit rate).
Needless to say, it's good.

Example 2 Next, a second embodiment of the present invention will be described.

FIG. 11 is a block diagram showing the configuration of a TLB using the second embodiment of the present invention.

In the first embodiment, an example of invalidating the TLB en) +7 that matches the VAR section number is shown, but this may also be an area number. In the second embodiment, the TLB is cleared using this area number.

Bus 1101i for transferring virtual addresses to TLB
, Jl sale? :V A R1102 (7) B I T2
The field specifying 9-20 (area number) is RM
1108, and the RM 1108 stores the area number.

When clearing the TLB, the area number in the VAR 1102 and the air area number in the RM 1108 are compared, and if they match, the match signal 1109 is activated and the corresponding AM
The validity bit 1110 of III is reset, and the virtual address/real address pair stored in the corresponding TLB is cleared. This second embodiment also makes it possible to speed up TLB clearing in area units.

As described in detail, according to the present invention, when switching virtual address spaces, it is better to clear only the TLB entries belonging to the ATR whose value has changed in ATRO-3 than to clear the entire TLB. Since the probability that valid entries remain is high, T
LB performance (bit rate) improves.

Furthermore, by providing hardware dedicated to section clearing in the TLB, the speed is faster than clearing by a microprogram of the central processing unit, and the time required for virtual address space switching is shortened.

In this way, it is possible to speed up the invalidation of the address translation indexing mechanism without causing a decrease in TLB performance (bit rate).

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the process of address translation in an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of the TLB in the embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of the associative memory of the TLB in the embodiment of the present invention. FIG. 4 is a diagram showing the configuration of the validity bit and other bits of the associative memory of the TLB in the embodiment of the present invention. FIG. 5 is a transistor level diagram showing the structure of one bit of the associative memory of the TLB in the embodiment of the present invention. FIG. 6 is a block diagram showing the configuration of a TLB in one conventional example. FIG. 7 is a block diagram showing the configuration of a TLB in another conventional example. FIG. 8 is a timing chart showing the timing of TLB address translation in the embodiment of the present invention. FIG. 9 is a timing chart showing the timing of TLB section clear in the embodiment of the present invention. FIG. 10 is a diagram showing the configuration of a multiple virtual address space in an embodiment of the present invention. FIG. 11 is a block diagram showing the configuration of the TLB in the second embodiment of the present invention. [Main reference numbers] 202...Register VAR for storing a virtual address 203...Field 203 that specifies the section number of the virtual address 204...Field 205 that specifies the in-page oraset of the virtual address 205...Register Address decoder 208 ・
- Content addressable memory (RM) that clears sections
- 210...Each en) Bit 211 indicating the validity of the contents of IJ...Associative memory AM 214...Memory for storing the real address corresponding to the virtual address stored in AM (DM)

Claims (1)

[Claims] In an information processing device that adopts a multiple virtual memory system and is equipped with an address translation index mechanism, in addition to a means for reading out a real address corresponding to a matching entry using a virtual address match comparison function during address translation, a match comparison function for a part of the virtual address is also provided. and a means for comparing a portion of the virtual address to invalidate only the virtual address and real address stored in the address translation indexing mechanism that correspond to the entry that matches the portion of the virtual address. Address translation index mechanism disabling device.