JPH01149133A - Microcomputer - Google Patents

Abstract

PURPOSE:To process an undefined instruction to the instruction of >=3 bytes by providing a trap code generating means for converting an undefined instruction code to a trap code and a code selecting means. CONSTITUTION:When the instruction code of the undefined instruction is outputted from an instruction cue 101 to a data bus 106, a code select signal generation ROM 102 inputs the instruction code as address information and outputs a code select signal 110. Therefore, a code to a bus 108. Thus, the operation code of one byte defined instruction is decoded by an instruction decoder 105. Then, the instruction code of the undefined instruction is outputted from the instruction cue 101, the signal generation ROM 102 inputs the instruction code as the address information, outputs a signal meaning the undefined instruction and the instruction code is decoded by the decoder 105.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer that performs a trap operation for undefined instruction codes.

[Conventional technology]

The microcomputer decodes the instruction code using an instruction decoder.

FIG. 5 shows a block diagram of a conventional microcomputer.

The microcomputer 500 is composed of an instruction queue 501 that outputs instruction codes, an internal data bus A303 to which the instruction codes output from the instruction queue 501 are output, and an instruction decoder 502 that decodes the instruction codes output to the internal data bus A303. has been done.

In a conventional microcomputer, the instruction decoder 502 does not have a decoding circuit for undefined instructions due to circuit reduction, or it decodes decoding circuits for the number of instruction code patterns of undefined instructions in order to decode undefined instructions. The decoder 502 was used to perform a trap operation for undefined instructions.

[Problem that the invention seeks to solve]

In conventional microcomputers that do not have a decoding circuit for undefined instructions as described above, when an undefined instruction is input to an instruction decoder, the microcomputer runs blankly.

On the other hand, in a microcomputer that decodes undefined instructions with an instruction decoder and performs a trap operation, it is necessary to have decoding circuits for the number of instruction code patterns of undefined instructions. However, there was a problem in that the decoding circuit was inevitably large, requiring a large amount of circuitry.

[Differences between the invention and the prior art]

In contrast to the conventional microcomputer described above, the microcomputer of the present invention has trap code generation means and food selection means for selecting an instruction code or a trap code.

The difference is that the instruction decoder only has a single trap code decoding circuit because the trap code generator and instruction code selection means convert multiple undefined instruction codes into a single trap hood. be.

[Means to solve the problem]

The microcomputer of the present invention has trap code generation means for converting and outputting an undefined instruction code into a trap code, and code selection means for selecting an instruction code or a trap code.

[Example 1] A first example of the present invention will be described using FIGS. 1 and 2.

A block diagram of a microcomputer according to the present invention is shown in FIG. The microcomputer 100 has an internal data bus A106 through which instruction codes are output from the instruction queue 101.
．． A code select signal generation ROM 102 inputs the instruction code outputted from the instruction queue 101 to the internal data bus A106 as address information and outputs the data at that address as the food select signal 110, and always outputs the trap code rFFHJ to the internal data bus B107. The trap code generator 103, which is a constant generating circuit, generates the instruction code on the internal data bus A106 when the code select signal 110 is "0", and the trap code on the internal data bus B107 when the code select signal 110 is rlJ. Select each internal data bus C
It consists of a code selector 104 that outputs to the internal data bus ClO3, and an instruction decoder 105 that decodes the instruction code or trap code that is output to the internal data bus ClO3.

The instruction decoder 105 has a trap code rFFHJ decoding circuit in addition to a definition instruction code decoding circuit.

FIG. 2 shows the entire data structure of the food select signal generation ROMI 02. In the figure, 1 word 1 bit 2
Consists of 56 words, code select signal generation RO
When the address information of M102, that is, the instruction code, is an undefined instruction code, the data at that address is set to "1," and when it is a defined instruction code, the data at that address is set to rOJ. This value is output as the code select signal 110.

Hereinafter, a microcomputer according to the present invention will be described in the case where a 1-byte long instruction code whose first byte determines the operation of the instruction is output from the instruction queue.

In this case, one of the instruction hoods of the defined 1-byte instruction is rolHJ, and two of the undefined instruction codes are rolHJ.
84HJ and rA6HJ, and from the instruction queue 101, defined instructions roIHJ, undefined instructions r84HJ, rA6
It is assumed that the output is in the order of HJ.

First, from the instruction queue 101, the instruction code roI of the defined instruction is
When HJ is output to internal data bus A106, code select signal generation ROMI 02 becomes instruction code r01H.
J is input as address information, and with data at address r01HJ, "0", which means a definition command, is output as the code select signal 110. Therefore, code selector 104 selects operation code r01HJ on internal data bus A106 and outputs it to internal data bus ClO3. Therefore, the opcode roI of the 1-byte instruction defined as
HJ is decoded by instruction decoder 105.

Next, the instruction code r8 of the undefined instruction from the instruction queue 101
4HJ is output, but code select signal 1 generation ROM
102 inputs the instruction code r84HJ as address information, and outputs "1" as the code select signal 110, which is the data of address r84HJ and means that it is an undefined instruction. Therefore, code selector 104 selects trap code rFFHJ on internal data bus B107 and outputs it to internal data bus ClO3. Therefore, as a result of the decoding by the instruction decoder 105, the microcomputer of this embodiment executes the trap processing.

Furthermore, the instruction code r of the undefined instruction is sent from the instruction queue 101.
When A6HJ is output, trap code rFFHJ is output to internal data bus 0108 to execute trap processing, as in the case of r84HJ.

[Embodiment 2] As a second embodiment of the present invention, in addition to the 1-byte length instruction as in Embodiment 1, a microcomputer has an instruction consisting of 2 bytes and the operation of the instruction is determined by the 2nd byte. This will be explained using FIGS. 3 and 4.

FIG. 3 shows a block diagram of the microcomputer in this embodiment. The microcomputer 300 shown in FIG. 1 differs from the microcomputer 100 shown in FIG. is input to the code select signal generation ROM 301 as the most significant bit of address information.

Note that 0PC310 becomes "0" when the first byte of a 1-byte instruction and a 2-byte instruction is decoded by the instruction decoder 302, and rlJ becomes "0" when the second byte of a 2-byte instruction is decoded by the instruction decoder 302. becomes.

FIG. 4 shows the code select signal generation RO in this embodiment.
The entire data configuration diagram of M301 is shown.

In the figure, each word consists of 512 words, 1 bit, and the code select signal generation ROM 301 contains 0PC31.
Since 0 is input as the most significant bit of address information, 1 of the 1-byte long instruction code and 2-byte instruction
When the instruction code for the byte is decoded by the instruction decoder 302, data from address 000H to QFFH of the code select signal generation ROM 301 is output, and when the second byte of a 2-byte instruction is decoded by the instruction decoder 302. Data from address 100H to IFFH of code select signal generation ROM 301 is output as code select signal 110.

Therefore, "0" is set to the address data of the defined 1-byte length instruction code, and "1" is set to the address data of the undefined 1-byte length instruction code. Also, the data at the 1st byte address of a 2-byte instruction is always "0", the data at the 2nd byte address of a defined instruction among 2-byte instructions is always "0", and the 2-byte address of an undefined instruction. "1" is set for each address.

Next, the operation in this embodiment will be explained.

roI one of the defined 1-byte length instruction codes
HJ, r84 one of the undefined 1-byte length instruction codes
HJ, one of the defined 2-byte instruction codes r
30HJ, rl CHJ, r30HJ one of the instruction codes of the undefined 2-byte instruction.

Suppose it is r95HJ. Then, from the instruction queue 101, ro IHJ, r84HJ, r30HJ, r
It is assumed that instruction codes are output in the order of 95HJ, r30HJ, and rlCHJ.

First, when the instruction code roIHJ of a 1-byte long defined instruction and the 1-byte long undefined instruction code r84HJ are output from the instruction queue 101 to the internal data bus A106, as described above, 0PC310 is always "0" and the code select Since the addresses of the signal generation ROM 301 are 0OIH and 084H, respectively, the same processing as in the microcomputer 100 of the first embodiment is performed.

Next, the first byte r30HJ of the instruction code of the 2-byte long undefined instruction from the instruction queue 101 is transferred to the internal data bus A1.
When decoded by the instruction decoder 302 outputted to 06,
As described above, 0PC310 becomes "0", code select signal generation ROM 301 inputs r030HJ as address information, and outputs "0", which is the data of address r030HJ, as food select signal 110. Therefore, the code selector 104 outputs the instruction code r30HJ on the internal data bus A106 to the internal data bus ClO3. Therefore, the first byte r of the instruction code of the undefined instruction
30HJ is decoded by the instruction decoder 105.

Next, the second byte of the instruction code r95HJ is output to the internal data bus A106, but when the second byte of the 2-byte instruction is decoded by the instruction decoder 302, 0PC31
0 becomes “1” and code select signal generation ROM301
inputs r195HJ as address information and outputs "1", which is the data of address r195HJ, as code select signal 110, so code selector 104 selects trap hood rFFHJ on internal data bus B107.
is output to internal data bus 0108. Therefore, the trap code rFFHJ is decoded by the instruction decoder 302 and trap processing is performed.

The 1st byte r of the 2-byte long instruction code defined next
30HJ is output to the internal data bus A106, but in this case, r30HJ is the first byte of the 2-byte undefined instruction.
The behavior is exactly the same as in the case of . Next, the second byte of the instruction code defined “ICIE (J is internal data bus A10
6, the code select signal generation ROM3
01 outputs rOJ, which is the data at address rllcHJ, as the code select signal 110, so the code selector 104 selects the instruction code rlcHJ on the internal data bus AlO3 and outputs it to the internal data bus ClO3, so the trap code rFFH is Internal data bus C
Since the instruction code rlcHJ is input to the instruction decoder 302 without being output to lO3, no trap processing occurs.
The defined 2-byte instruction is executed.

〔Effect of the invention〕

As described above, the microcomputer of the present invention converts a plurality of undefined instruction codes into a single code by means of a trap code generation means and a code selection means for selecting an instruction code or a trap code.

Further, the undefined instruction decoding circuit required in the instruction decoder is only a single trap code decoding circuit.

Therefore, unlike conventional microcomputers that do not have a means for decoding undefined instructions, even if an undefined instruction code is input to the instruction decoder, the instruction decoder does not run out of control.

Furthermore, when compared with a microcomputer in which the instruction decoder has decoding circuits for the number of undefined instruction patterns and executes a trap operation, the microcomputer of the present invention requires only one undefined instruction decoding circuit in the instruction decoder.
Since the number of patterns of undefined instructions is only one, it is constant regardless of the number of patterns of undefined instructions, and when the number of patterns of undefined instructions increases to a certain extent, the amount of hardware required by the present invention is smaller.

Also, when changing the instruction set, if a code select signal generation 'ROM' is used as shown in the embodiment, the ROM can be changed.
This can be easily addressed by changing the contents of

By applying the present invention, it becomes possible to process undefined instructions even for instructions of 3 bytes or more by increasing the number of bits of the code select signal generation ROM and changing the control signal output by the instruction decoder. The application effects of the present invention are significant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microcomputer according to the present invention.
FIG. 2 is an overall data configuration diagram of the code select signal generation ROM in the first embodiment, FIG. 3 is a diagram of the microcomputer in the second embodiment, and FIG. 4 is a diagram of the microcomputer in the second embodiment. FIG. 5, which is a diagram showing the overall data structure of the code select signal generation ROM, is a block diagram of a conventional microcomputer. 100...Microcomputer, 101...
...Instruction queue, 102...Code selection signal generation ROM, 103...Trap code generation section, 104...Code selector, 105.
...Instruction decoder, 106...Internal data bus A, 107...Internal data bus B, 10
8...Internal data bus C1110...
Code select signal, 300...Microcomputer, 301...Code select signal generation ROM, 302...Instruction decoder, 310...
...OPC, 500...Microcomputer, 501...Instruction queue, 502...
...Instruction decoder, 503...Internal data bus A. Agent Patent Attorney Uchihara Onde / Figure 2 Figure $4I! I $5 Figure

Claims (1)

[Claims] A microcontroller characterized in that it has a playing card code generation means for converting and outputting an undefined instruction code into a single trap code, and a code selection means for selecting an instruction code or a trap code, and performs trap processing on the undefined instruction code. Computer