JPH01147440U

JPH01147440U -

Info

Publication number: JPH01147440U
Application number: JP4209788U
Authority: JP
Priority date: 1988-03-31
Filing date: 1988-03-31
Publication date: 1989-10-12

Description

[Brief explanation of the drawing]

第１図は本考案の原理図、第２図は本考案のＤ
ＳＰの第１の実施例におけるビツト置換回路を表
わす図、第３図は第２図はビツト置換回路の動作
を説明するための図、第４図は本考案のＤＳＰの
第２の実施例におけるビツト置換回路を表わす図
、第５図は複数個のＤＳＰの直列接続を表わす図
、第６図はＤＳＰの１例を表わすブロツク図、第
７図は従来のＤＳＰにおける入力レジスタから内
部レジスタへの転送の形式を表わす図である。図において、１０……ビツト置換回路、１１…
…転送手段、１２……符号ビツト、１３……中間
ビツト領域、１４……データビツト領域。 Figure 1 is the principle diagram of the present invention, Figure 2 is the D of the present invention.
FIG. 3 is a diagram showing the bit replacement circuit in the first embodiment of the SP, FIG. 2 is a diagram for explaining the operation of the bit replacement circuit, and FIG. 4 is a diagram showing the bit replacement circuit in the second embodiment of the DSP of the present invention. FIG. 5 is a diagram showing a series connection of multiple DSPs, FIG. 6 is a block diagram showing an example of a DSP, and FIG. 7 is a diagram showing a conventional DSP from an input register to an internal register. FIG. 3 is a diagram showing a transfer format. In the figure, 10... bit replacement circuit, 11...
...transfer means, 12... code bit, 13... intermediate bit area, 14... data bit area.

Claims

[Claims for Utility Model Registration] 1. A digital signal processing processor having a fixed-point format input mode and a floating-point format input mode, comprising a sequence control unit 16 for managing the execution of instructions, and having the fixed-point format input mode. The input data in the floating point format input mode includes an intermediate bit area 13 between the sign bit 12 and the data bit area 14, and the intermediate bit area 13 corresponds to the exponent bit area in the floating point format input mode.Digital signal processing The processor includes a bit replacement circuit 10 having a transfer means 11 for replacing all bits in the intermediate bit area 13 with the same bits as the code bits 12 when the operation command P is output from the sequence control section 16. A digital signal processing processor comprising: 2. A mode register 15 is provided that indicates whether the mode is the fixed-point format input mode or the floating-point format input mode, and the operation command P is transmitted from an input register for storing serially input data for arithmetic processing. The bit substitution circuit 10 outputs the bit replacement circuit 10 at the same time when the transfer command for transferring the data to the internal register of the bit is output, and when the operation command P is output and the mode register 15 indicates that it is in the fixed-point input mode. 2. A digital signal processing processor according to claim 1, which performs said replacement. 3. Claim 1, wherein the operation command P is output immediately before a command for converting the contents of the internal register from a fixed-point format to a floating-point format is output.
The digital signal processing processor described.