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JPH01145869A - Manufacture of uveprom with redundant circuit - Google Patents

Manufacture of uveprom with redundant circuit

Info

Publication number
JPH01145869A
JPH01145869A JP62305210A JP30521087A JPH01145869A JP H01145869 A JPH01145869 A JP H01145869A JP 62305210 A JP62305210 A JP 62305210A JP 30521087 A JP30521087 A JP 30521087A JP H01145869 A JPH01145869 A JP H01145869A
Authority
JP
Japan
Prior art keywords
uveprom
cell
redundant circuit
memory cell
shielding film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62305210A
Other languages
Japanese (ja)
Inventor
Junichi Sekine
関根 順一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP62305210A priority Critical patent/JPH01145869A/en
Publication of JPH01145869A publication Critical patent/JPH01145869A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/68Floating-gate IGFETs
    • H10D30/681Floating-gate IGFETs having only two programming levels

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

PURPOSE:To reduce the area of a redundant circuit and to make it possible to perform the operation tests of a UVEPROM cell, by performing a step for covering the UVEPROM cell for programs in the redundant circuit with an ultroviolet ray shielding film, other than a circuit wiring pattern. CONSTITUTION:Operation tests are conducted by using a wafer prover. Thereafter, a polyimide film having a thickness of about 1mum is selectively formed. Heat treatment is performed at 400 deg.C. A UVEPROM element and its peripheral part are covered with an ultraviolet ray shielding film 4. Then the device is sealed into a package in an assembling step. Operation tests after assembling is performed in conformity with an ordinary method. The ultraviolet ray shielding film 4 comprising polyimide is provided at a layer other than that of an aluminum electrode 6. Therefore, the area of the UVEPROM can be made small and can be provided over a wide area other than a memory cell 1 and a spare memory cell 2. The sufficient shielding effect can be provided. The operation test of the UVEPROM cell 3 can be performed under the wafer state, and the steps can be rationalized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は冗長回路付きUVEPROMの製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a UVEPROM with a redundant circuit.

〔従来の技術〕[Conventional technology]

UVEPROMはデータを消去するためメモリセルに紫
外線を照射する。従って、プログラム用のUVEPRO
Mセルにより切り換える冗長回路を内蔵したUVEPR
OMにおいては、消去時にプログラム用のUVEPRO
Mセルにも紫外線が当たりこのデータが消えると不良の
メモリセルが選ばれてしまい、リダンダンシーの機能が
無くなる。そこで従来の冗長回路付きUVEPROMの
製造方法には、プログラム用のUVEPROMセルには
紫外線が当たらないようにアルミニウム膜で被覆する工
程があるが、この工程は電極配線形成と同時に行われて
いた。
UVEPROM irradiates memory cells with ultraviolet light to erase data. Therefore, the UVEPRO for the program
UVEPR with built-in redundant circuit switched by M cell
In OM, UVEPRO for programming during erasing
If the M cell is also exposed to ultraviolet light and this data is erased, a defective memory cell will be selected and the redundancy function will be lost. Therefore, the conventional manufacturing method of UVEPROM with redundant circuit includes a step of coating the programming UVEPROM cell with an aluminum film to prevent it from being exposed to ultraviolet rays, but this step was performed at the same time as electrode wiring formation.

第4図は従来例を説明するためのUVEPROMセルの
パターン図、第5図は第4図のχ−X′線相当部で切断
した半導体チップの断面図である。
FIG. 4 is a pattern diagram of a UVEPROM cell for explaining a conventional example, and FIG. 5 is a cross-sectional view of the semiconductor chip taken along the line χ-X' in FIG.

浮遊ゲート10.制御ゲート11.N+拡散層8−7.
8−8をソース・ドレイン領域大とするUVEPROM
セルをアルミニウム電極6−1で被覆し、紫外線を遮蔽
する。紫外線遮蔽膜は、電極配線を兼ねているので、こ
の部分には他の素子を配置できない。又、遮蔽効果を良
くするため、広い面積をアルミニウム膜が覆っている。
Floating gate 10. Control gate 11. N+ diffusion layer 8-7.
UVEPROM with 8-8 as the large source/drain region
The cell is covered with an aluminum electrode 6-1 to block ultraviolet rays. Since the ultraviolet shielding film also serves as electrode wiring, no other elements can be placed in this portion. Further, in order to improve the shielding effect, the aluminum film covers a wide area.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の冗長回路付きUVEPROMの製造方法
は、プログラム用のUVEPROMセルを電極配線を兼
ねたアルミニウム膜で被覆して紫外線遮蔽膜を形成する
ので、紫外線遮蔽膜の下に他の素子を配置することがで
きず、冗長回路が占有する面積が大きくなるという欠点
がある。
In the conventional manufacturing method of UVEPROM with a redundant circuit described above, a UVEPROM cell for programming is covered with an aluminum film that also serves as electrode wiring to form an ultraviolet shielding film, so other elements are placed under the ultraviolet shielding film. This has the disadvantage that the area occupied by the redundant circuit increases.

また動作試験を行なうときはすでにアルミニウム膜で被
覆されていて消去できないためプログラム用のUVEP
ROMセルの試験はできないという欠点もある。
Also, when performing an operation test, the UVEP for programming is already covered with an aluminum film and cannot be erased.
Another drawback is that ROM cells cannot be tested.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の冗長回路付きUVEPROMの製造方法は、デ
ータを記憶するメモリセルと、メモリセルの一部に不良
が発生した場合該不良メモリセルと置き換えるための予
備のメモリセルと、プログラム用のUVEPROMセル
を有し、不良のメモリセルと予備のメモリセルを切り換
えて使用する冗長回路を具備した冗長回路付きUVEP
ROMを製造する際に、動作試験後前記UVEPROM
セルを紫外線遮蔽膜で被覆する工程を有するというもの
である。
The method of manufacturing a UVEPROM with a redundant circuit according to the present invention includes a memory cell for storing data, a spare memory cell for replacing the defective memory cell when a defect occurs in a part of the memory cell, and a UVEPROM cell for programming. UVEP with a redundant circuit, which has a redundant circuit that switches between defective memory cells and spare memory cells.
When manufacturing a ROM, the UVEPROM is
The method involves a step of coating the cell with an ultraviolet shielding film.

紫外線遮蔽膜は配線用アルミニウム膜とは別の暦になる
ので、メモリセルや予備のメモリセルにかからない範囲
でまわりの素子とは無関係に大きくすることができ、冗
長回路の面積を小さくすることができる。また動作試験
のときは紫外線遮蔽膜がなく、プログラム用のUVEP
ROMセルの消去ができるためこの試験を行なうことが
できる。
Since the ultraviolet shielding film is separate from the aluminum film for wiring, it can be made large independently of surrounding elements as long as it does not cover memory cells or spare memory cells, and the area of redundant circuits can be reduced. can. Also, during the operation test, there was no ultraviolet shielding film, and the UVEP for programming
This test can be performed because the ROM cells can be erased.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例を説明するためのブロック図
、第2図はUVEPROMセルとその周辺部を示す半導
体チップの断面図、第3図は本発明の一実施例の流れ図
である。
FIG. 1 is a block diagram for explaining an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor chip showing a UVEPROM cell and its surrounding area, and FIG. 3 is a flowchart of an embodiment of the present invention. .

浮遊ゲート10.制御ゲート11.N+拡散層8−3.
8−4をソース・ドレイン領域とするUVEPROM素
子、その周辺回路(N+拡散層8−1.8−2を含むM
OSトランジスタ、N+拡散層8−5.8−6を含むM
oSトランジスタ、アルミニウム電極6を含む構成を有
している)、カバー絶縁膜5で被覆する。ここまでは、
アルミニウム膜で浮遊ゲート10の上方を広く被覆しな
いようにする以外は従来と同様の工程で製造できる。こ
のようなウェーハ製造工程21の後、ウェーハ・プロー
バを用いて動作試験22を行なったのち、厚さ約1μm
のポリイミド膜を選択的に成膜し、400℃の熱処理を
行ない紫外線遮蔽膜4でUVEPROM素子とその周辺
部を被覆する(23)。次いで組立工程24でパッケー
ジに封入し、組立後の動作試験25を通常の方法に準じ
て行なう。
Floating gate 10. Control gate 11. N+ diffusion layer 8-3.
UVEPROM element whose source/drain region is 8-4, its peripheral circuit (M including N+ diffusion layer 8-1, 8-2)
OS transistor, M including N+ diffusion layer 8-5, 8-6
(having a configuration including an oS transistor and an aluminum electrode 6) is covered with a cover insulating film 5. So far,
It can be manufactured using the same process as the conventional method except that the upper part of the floating gate 10 is not widely covered with the aluminum film. After such a wafer manufacturing process 21, an operation test 22 was performed using a wafer prober, and the wafer was found to have a thickness of about 1 μm.
A polyimide film is selectively formed and heat-treated at 400° C. to cover the UVEPROM element and its surrounding area with the ultraviolet shielding film 4 (23). Next, in an assembly step 24, the product is sealed in a package, and a post-assembly operation test 25 is conducted according to a conventional method.

ポリイミドからなる紫外線遮蔽膜4は、アルミニウム電
極6とは別の層に設けられるので、UVEPROMの面
積は小さくでき、又、メモリセル1や予備のメモリセル
2の部分にかからない範囲で広い面積に亘って設けるこ
とができ、遮蔽効果を十分にもたせることができる。又
、ウェーハ状態でUVEPROMセルの動作試験が可能
となり、工程の合理化ができる。
Since the ultraviolet shielding film 4 made of polyimide is provided on a layer different from the aluminum electrode 6, the area of the UVEPROM can be reduced, and it can be applied over a wide area without covering the memory cell 1 or the spare memory cell 2. It is possible to provide a sufficient shielding effect. Furthermore, it is possible to test the operation of UVEPROM cells in the wafer state, thereby streamlining the process.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は冗長回路内のプログラム用
のUVEPROMセルを回路配線パターンとは別層の紫
外線遮蔽膜で被覆するという工程を動作試験後に行なう
ことにより、冗長回路の面積を小さくすることができ、
UVEPROMセルの動作試験も可能となり冗長回路付
きUVEPROMの製造工程の合理化ができるという効
果がある。
As explained above, the present invention reduces the area of the redundant circuit by performing a step of covering the programming UVEPROM cell in the redundant circuit with an ultraviolet shielding film separate from the circuit wiring pattern after the operation test. is possible,
It is also possible to test the operation of UVEPROM cells, which has the effect of streamlining the manufacturing process of UVEPROMs with redundant circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を説明するためのブロック図
、第2図はUVEPROMセルとその周辺部を示す半導
体チップの断面図、第3図は木発明の一実施例の流れ図
、第4図は従来例を説明するためのパターン図、第5図
は第4図のx−x’線相当部で切断した半導体チップの
断面図である。 1・・・メモリセル、2・・・予備のメモリセル、3・
・・UVEPROMセル、4・・・紫外線遮蔽膜、5・
・・カバー絶縁膜、6.6−1.6−1・・・アルミニ
ウム電極、7・・・ゲート、8−1〜8−8・・・N+
拡散層、9・・・ウェル、10・・・浮遊ゲート、11
・・・制御ゲート、12・・・P−シリコン基板、13
・・・フィールド酸化膜、14・・・層間絶縁膜、21
・・・ウェーハ製造工程、22・・・動作試験工程、2
3・・・UVE PROMセル被覆工程、24・・・組
立工程、25・・・動作試験工程。
FIG. 1 is a block diagram for explaining an embodiment of the present invention, FIG. 2 is a cross-sectional view of a semiconductor chip showing a UVEPROM cell and its surrounding area, and FIG. 3 is a flowchart of an embodiment of the invention. FIG. 4 is a pattern diagram for explaining a conventional example, and FIG. 5 is a cross-sectional view of the semiconductor chip taken along the line xx' in FIG. 4. 1...Memory cell, 2...Spare memory cell, 3.
・・UVEPROM cell, 4・・UV shielding film, 5・
...Cover insulating film, 6.6-1.6-1...Aluminum electrode, 7...Gate, 8-1 to 8-8...N+
Diffusion layer, 9... Well, 10... Floating gate, 11
...Control gate, 12...P-silicon substrate, 13
...Field oxide film, 14...Interlayer insulating film, 21
...Wafer manufacturing process, 22...Operation test process, 2
3... UVE PROM cell coating process, 24... Assembly process, 25... Operation test process.

Claims (1)

【特許請求の範囲】[Claims] データを記憶するメモリセルと、メモリセルの一部に不
良が発生した場合該不良メモリセルと置き換えるための
予備のメモリセルと、プログラム用のUVEPROMセ
ルを有し、不良のメモリセルと予備のメモリセルを切り
換えて使用する冗長回路を具備した冗長回路付きUVE
PROMを製造する際に、動作試験後前記UVEPRO
Mセルを紫外線遮蔽膜で被覆する工程を有することを特
徴とする冗長回路付きUVEPROMの製造方法
It has a memory cell for storing data, a spare memory cell to replace the defective memory cell when a part of the memory cell becomes defective, and a UVEPROM cell for programming. UVE with redundant circuit equipped with redundant circuit that can be used by switching cells
When manufacturing PROM, after operation test, the UVEPRO
A method for manufacturing a UVEPROM with a redundant circuit, comprising the step of coating an M cell with an ultraviolet shielding film.
JP62305210A 1987-12-01 1987-12-01 Manufacture of uveprom with redundant circuit Pending JPH01145869A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62305210A JPH01145869A (en) 1987-12-01 1987-12-01 Manufacture of uveprom with redundant circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62305210A JPH01145869A (en) 1987-12-01 1987-12-01 Manufacture of uveprom with redundant circuit

Publications (1)

Publication Number Publication Date
JPH01145869A true JPH01145869A (en) 1989-06-07

Family

ID=17942377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62305210A Pending JPH01145869A (en) 1987-12-01 1987-12-01 Manufacture of uveprom with redundant circuit

Country Status (1)

Country Link
JP (1) JPH01145869A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH045847A (en) * 1990-04-23 1992-01-09 Toshiba Corp Semiconductor storage device and its manufacturing method
JPH04291759A (en) * 1991-03-20 1992-10-15 Nec Corp Semiconductor device
JPH05211317A (en) * 1991-11-29 1993-08-20 Nec Corp Semiconductor device
US5519246A (en) * 1992-02-28 1996-05-21 Mitsubishi Denki Kabushiki Kaisha Nonvolatile memory apparatus using an ultraviolet impermeable resin film

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148485A (en) * 1978-05-15 1979-11-20 Nec Corp Test method for semiconductor device
JPS5521158A (en) * 1978-08-01 1980-02-15 Nec Corp Checking method for semiconductor device
JPS6245075A (en) * 1985-08-22 1987-02-27 Nec Corp Non-volatile memory
JPS62241358A (en) * 1986-04-14 1987-10-22 Hitachi Ltd One-time program type semiconductor device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54148485A (en) * 1978-05-15 1979-11-20 Nec Corp Test method for semiconductor device
JPS5521158A (en) * 1978-08-01 1980-02-15 Nec Corp Checking method for semiconductor device
JPS6245075A (en) * 1985-08-22 1987-02-27 Nec Corp Non-volatile memory
JPS62241358A (en) * 1986-04-14 1987-10-22 Hitachi Ltd One-time program type semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH045847A (en) * 1990-04-23 1992-01-09 Toshiba Corp Semiconductor storage device and its manufacturing method
JPH04291759A (en) * 1991-03-20 1992-10-15 Nec Corp Semiconductor device
JPH05211317A (en) * 1991-11-29 1993-08-20 Nec Corp Semiconductor device
US5519246A (en) * 1992-02-28 1996-05-21 Mitsubishi Denki Kabushiki Kaisha Nonvolatile memory apparatus using an ultraviolet impermeable resin film

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