JPH01145755A - Data transfer system - Google Patents

Abstract

PURPOSE:To simplify processing procedure, to curtail a data length required for a transfer and to improve a transfer speed by executing a data transfer in a period in which a controller sets a control signal line to a one-way level. CONSTITUTION:In case of executing a transfer of data between a controller 11 and a data processor 10, the controller 11 sets a control signal line 30 to a one-way level in a necessary period. In this period of the one-way level, the transfer of the data is executed between the controller 11 and the data processor 10. In such a way, with regard to the data to be transferred, it will suffice to only designate a head address at the time of read-out/write of the data, and irrespective of whether the data to be transferred is the quantity of one unit data quantity or the quantity of plural unit data, the transfer can be executed by the same processing procedure, the data length required for the transfer can be curtailed, and the transfer speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for transferring data between a data processing device and a control device included in, for example, an in-vehicle Kawano 9Y1 device.

BACKGROUND ART Conventionally, for example, in-vehicle Kawano9 devices have included a digital signal processing device (DSP, hereinafter abbreviated as a processing device) and a control device such as a microcomputer, which process various signals and Serial data is transferred between these devices.

FIG. 4 is a block diagram showing the configuration of a typical prior art.1 This prior art example includes a control device 1 and a processing device 2, and transfer lines 3 to which serial data is transferred in one direction. .4 and a control line 5 to which the synchronization signal SC is transferred.

5 to 7 are time charts showing the data transfer procedure in the configuration shown in FIG. 4. FIG. The operation of the configuration shown in FIG. 4 will be explained with reference to these drawings. 5 and 6 show the case where data is transferred in units of pairs of address data and data specified by the address data. FIG. 5 shows the process of writing data from the control device 1 to the processing device 2, in which the address of the processing device 2 and the data written to the address are paired during the falling period of the synchronization signal SC. , the raw coal is transferred.

FIG. 6 shows a read operation from the processing device 2 by the control device 1. During the period when the synchronization signal SC is falling, the control device 1 sends desired address data to the processing device 2, and 2 transfers the data specified by the address. 'On the other hand, FIG. 7 shows a system in which a start address and an end address are specified when data is transferred, and data between them is transferred continuously. When the control device 1 writes data to the processing device 2, as shown in FIG. Send the corresponding data. Even when reading, the control device 1 sends the start address and end address to the processing device 2, and the processing bag! 2 continuously returns corresponding data.

Problems to be Solved by the Invention In the prior art transfer method shown in FIGS. 5 and 6 above, for example, when attempting to transfer a large amount of data with consecutive addresses, it is difficult to attach an address to each piece of data. However, there is a problem in that data transfer takes an unnecessarily long time. Furthermore, although the prior art transfer method shown in FIG. 7 is advantageous when transferring a large amount of data with consecutive addresses, it is difficult to use when transferring a large amount of data with non-consecutive and dispersed addresses. When transferring data for each address, there is a problem that the end address is unnecessary and the data length for transfer becomes unnecessarily long.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer method that solves the above-mentioned problems, improves data transfer speed, and simplifies data transfer processing procedures.

Means for Solving the Problems The present invention provides a system in which serial data is transferred for each unit data amount between a data processing device and a control device.A serial data transfer line is provided between the data processing device and the control device. and a control signal line for switching and controlling the data processing device between a transfer operating state and a transfer non-operating state, so that the data transfer is performed during a period in which the control device sets the control signal line to one level. This data transfer method is characterized by:

Function The present invention is a system in which serial data is transferred between a data processing device and a control device for each unit data amount. When transferring data between a control device and a data processing device,
The control device holds the control signal line at one level for the required period of time. During this one-level period, data is transferred between the control device and the data processing device. That is, the end timing of data transfer is realized by switching the control signal on the control signal line from one level to the other level by the control device.

As a result, it is only necessary to specify the start address when reading/writing data regarding the data to be transferred, and regardless of whether the data to be transferred is one unit of data or multiple units of data, the same Transfer can be performed using the following processing procedure. In addition, when transferring data at consecutive addresses, there is no need to attach a corresponding address to each of the five data units, and when transferring a 14i data amount, the end address to be accessed can be used. There is no need to add .This makes it possible to reduce the data length required for transfer and improve the transfer speed. Furthermore, regardless of whether the data to be transferred is one unit of data or multiple units of data, it can be transferred in a single procedure, so the transfer procedure can be greatly simplified.

Embodiment FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. This embodiment will be described with reference to FIG. This embodiment is suitably implemented for serial data transfer between a digital signal processing device (DSP) and a microcomputer in, for example, in-vehicle audio equipment. In this embodiment, data is transferred between a processing device 10 such as a DSP and a control device 11 such as a microcomputer. The processing device 10 is provided with an arithmetic processing circuit 12 such as a microprocessor, a storage section 13 implemented by, for example, a random access memory, and an address counter 14, which are connected to an internal bus 15.

This internal bus 15 also includes a buffer register 16.1.
7 is connected to the buffer register 16.17, and a transfer register 18.19 is connected to the buffer register 16.17. Buffer register 16 and transfer register 18 are involved in the reception operation of processing device 10, and buffer register 17 and transfer register 19 are involved in transmission operation.

On the other hand, the control device 11 has a similar configuration to the processing bag W10, and includes an arithmetic processing circuit 20, a storage section 21, and a word counter 22, which are connected to an internal bus 23. This internal bus 23 has buffer registers 24 and 25.
and transfer registers 26 and 27 are provided. The buffer register 24 and the transfer register 26 are involved in the transmission operation to the processing device 10, and the buffer register 25 and the transfer register 27 are involved in the reception operation 1Y from the processing device 10. Transfer registers 18, 26; 19, 27 are provided with data transfer lines 28, 29, and as described later, a control signal (synchronization signal) is provided to switch the processing device 10 between a transfer operating state and a transfer non-operating state. A control signal line 30 is provided which outputs a signal (SC).

FIG. 2 is a timing chart illustrating the operation of the configuration shown in FIG. 1, and FIG. 3 is a flowchart illustrating the operation. Seeing Figure 2 and Figure 3I12I together,
The operation of this embodiment will be explained.

The control device 11 controls the processing device 1 in the 311J step a1.
It is determined whether to perform read processing or write processing for 0. When performing a write process, a write start address (start address) of the storage unit 13 of the processing device 10 is set in step a2. The data to be written is transferred as unit data 1, for example 8 bits as one unit (hereinafter referred to as 1 word). In step a3, the number of words to be transferred is set.

In step a4, the control device 11
At time t1 in FIG. 2, the synchronizing signal SC output to the synchronizing signal SC is lowered to a low level, for example. In step a5, after the time t1, the control device 11 outputs the start address and write command set in step a2 to the transfer line 28. Subsequently, in step a6, data DO stored at the start address in the storage section 13 of the processing device 10 is output.

Next, in step a7, the word number counter 22 of the control device 11 decrements the number of words set in step a3 by one. In step a8, it is determined whether the number of words, which is the count value of the word number counter at this time, is 0, and if negative, the process moves to step a6.
Repeat steps a6 to a8. When it is determined in step a8 that the number of words is O, the synchronizing signal SC is raised at time t2 in FIG. 2 in step a9.

In this way, as shown in FIG. 2(2), the data writing process from the control device 11 to the processing device 10 is completed.

When the read command is selected in step a1, the start address of the storage unit 13 of the processing device 10 to be read is set in step alo.The number of words to be read next is set in step all, and in step a12, the number of words to be read next is set. At time t1 in FIG. 2, the synchronizing signal SC falls.

In step a13, the start address and read command are output to the processing device 10 as shown in FIG. 2(3).

In step a14, the processing bag r1110 that has received the read command outputs the data DO from the corresponding address of the storage unit 13 to the control device 11. At step a15, the word counter 22 of the control device 11 decrements by - each time one word of the data is input.

In step a16, it is determined whether the number of words, which is the count value of the word number counter 22, is O. If this judgment is negative, the process returns to step a14, and the processes of steps a14 to a16 are repeated. If the judgment of step a16 is affirmative, step a
17, at time t2 in FIG. 2, the control device 11 raises the synchronization signal SC. In this way, as shown in FIG. 2(3) and FIG. 2(4), the process of reading data from the processing device 10 to the control device 11 is completed.

According to this embodiment, it is not necessary to add an address for each word of data each time the data is transferred, and the amount of transmitted data is reduced. Furthermore, in this embodiment, the start address is simply supplied, and there is no need to add end address data as described in the prior art, which also reduces the data length involved in transfer. By reducing the data length in this way, the transfer time is shortened, and there is no need to change the transfer procedure between transferring one word and transferring multiple words. This greatly simplifies the software and configuration for performing data transfer.

Effects As described above, according to the present invention, with respect to the data to be transferred, it is only necessary to specify the start address when reading/sending data, and whether the data to be transferred is one unit of data or multiple units of data. Transfer can be performed using the same processing procedure regardless of the unit data amount. In addition, when transferring data at consecutive addresses, there is no need to attach a corresponding address to each unit data amount, and even when transferring one unit data amount, the end address to be accessed is not required. There is no need to attach it. This makes it possible to reduce the data length required for transfer and improve the transfer speed. Furthermore, regardless of whether the data to be transferred is one unit of data or multiple units of data, it can be transferred in a single procedure, so the transfer procedure can be greatly simplified.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a timing chart explaining the operation of this embodiment,
FIG. 3 is a flowchart explaining the operation of this embodiment, FIG. 4 is a block diagram showing the configuration of a typical prior art, and FIG.
7 to 7 are timing charts illustrating the operation of the prior art. 10...-processing device, 11... control device, 12...
Arithmetic processing circuit, 13... Storage unit, 14... Address counter, 22... Word number counter, 28.29.
...Transfer line, 30...Control signal line Agent Patent attorney Number of strokes Keiichi Figure 3

Claims (1)

[Claims] In a system in which serial data is transferred for each unit data amount between a data processing device and a control device, a serial data transfer line and a data processing line are provided between the data processing device and the control device. A control signal line is provided for switching and controlling the device between a transfer operating state and a transfer non-operating state, and the control device performs data transfer during a period when the control signal line is at one level. data transfer method.