JPH01143096A - Memory device - Google Patents

Abstract

PURPOSE:To reduce dispersion in manufacture and to make stable control possible by composing a current mirror circuit with a variable resistance means connected to a bit line and each MIS trangister Tr of its control circuit. CONSTITUTION:At each trailing end part of bit lines BL1 and BL2, PMOSTr1 and 2 used for a variable resistance means are formed. The gate electrode of these Tr1 and 2 are connected to a control circuit 3. The circuit 3 is formed with PMOSTr4 and a constant current source 5. And Tr4 connects Tr1 and 2 each other and composes these and a current mirror circuit. By this, an electric current I1 to flow or Tr1 is fixed by an electric current I4 to flow on Tr4, and the electric current I1 becomes a proportional relation with the electric current I4. Consequently, by fixing the electric current I4 with the constant current source 5 and so on, the electric current of a direct current action on writing indicates an approximately fixed value. Besides, even when the variance on manufacturing are generated by forming each MISTr composing the current mirror circuit at the same process, the proportional relation of each electric current of the circuit are maintained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device such as an SRAM (static RAM), and more particularly to a memory device in which a variable resistance means is provided at the end of a bit line.

[Summary of the invention]

The present invention provides a memory device having variable resistance means connected to a bit line and a control circuit for the variable resistance means.
By configuring a current mirror circuit with the variable resistance means and each MIS transistor of the control circuit, stable control is realized that is resistant to manufacturing variations.

[Conventional technology]

A technique is known in which a memory device uses a variable impedance bit (data) line load circuit that changes the impedance of a bit line load resistance during reading and writing. Further, as those disclosing such a technique, there are a technique described in Japanese Patent Publication No. 44747/1982 and a technique described in Japanese Patent Application Laid-open No. 200595/1989.

FIG. 4 is a circuit diagram of a main part of an example of a memory device having the variable impedance bit line load circuit. A memory cell 40 is formed between a pair of bit lines BL, BL. Although not shown, the memory cells 4o are arranged in a matrix to form a memory cell array. PMO3 transistors 41 and 42 as variable resistance means are connected to the terminal ends of the bits 4'11BLI and BL2. Each source of these PMO3 transistors 41 and 42 is connected to the power supply voltage Vdd, and each gate is connected to the control circuit 43. The control circuit 43 has a power supply voltage Vd
d and the ground voltage GND, diodes 44, 45 and an NMO3 transistor 46 are connected in series. A read/write signal R/W is input to the gate of the NMO3I-transistor 46 to control on/off.

In a memory device having such a main part configuration, the gate voltage of the PMOS transistors 41 and 42 is set to the ground voltage during reading by the operation of the control circuit 43, and the gate voltage is set to the voltage drop of the diode 44 and 45 during B writing. It is considered to be an intermediate voltage using Therefore, there are advantages such as low power consumption during writing in a range that does not involve sudden changes in impedance.

[Problems to be Solved by the Invention] However, memory devices having such a structure are susceptible to the adverse effects of manufacturing variations.

That is, the DC operating current during writing (current flowing from the PMOS transistors 41 and 42 to the memory cell 40)
is determined by the current capability of the PMOS transistors 41 and 42. However, the control circuit 4 that supplies the gate voltage
3 is a diode 44 made of an NMO3 transistor.
For example, variations in the threshold voltages VLh of these diodes 44 and 45 cause the output gate voltage to vary, and as a result, the DC operating current during writing also varies.

SUMMARY OF THE INVENTION In view of the above-mentioned problems, the present invention aims to provide a memory device that is resistant to manufacturing variations and realizes stable control.

[Means for solving problems]

The present invention provides a memory device having a memory cell, a bit line connected to the memory cell, a variable resistance means connected to the bit line, and a control circuit for the variable resistance means. The above problem is solved by a memory device characterized in that a MIS transistor used in the control circuit and a MIS transistor used in the control circuit constitute a current mirror circuit.

Here, the memory cell may be of any type, such as a resistance load type, a depletion load type, or an 0MO3 type. In addition, each M■S transistor constituting the current mirror circuit is
They can be formed through the same process.

[Effect]

As mentioned above, the DC operating current during writing is determined from the current capacity of the MIS transistor used in the variable resistance means, and the MIS transistor is connected to the MIS transistor of the control circuit.
By connecting the S transistor and the current mirror circuit to form a current mirror circuit, its current capacity can be strongly adjusted even against manufacturing variations.

That is, by configuring a current mirror circuit with each of the above Mis) resistors, the MI used in the variable resistance means can be
Current flowing through S transistor! V is determined by Mr used in the control circuit and the current 1c flowing through the transistor, and the current 1v is proportional to the current 1c. Therefore, by keeping the current flowing through the MIS transistor used in the control circuit constant using a constant current source or the like of the control circuit, the DC operating current at the time of four-stroke will also exhibit a substantially constant value.

In particular, by forming each MIS transistor constituting the current mirror circuit in the same process, the tendency of variations in the elements becomes uniform, and even if manufacturing variations occur, each current in the current mirror circuit The proportional relationship will also remain maintained.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment The memory device of this embodiment is an SRAM and has a basic configuration as shown in FIG.

The circuit configuration first consists of a pair of pins [BL,.

It has a memory cell 10 connected to BL. Although not shown, the memory cells/L; 10 are arranged in a matrix to form a memory cell array.

Paired bit lines are also formed in a plurality of columns corresponding to the memory cells.

At the terminal ends of the bit lines BL, BL, 2MO3 transistors 1 and 2 are formed as MIS transistors used as variable resistance means. A power supply voltage Vdd is supplied to the sources of these PMOS transistors 1 and 2. The drain sides of the PMO3 transistors 1 and 2 become the respective bit lines BL+, BL, and t. The gate electrodes of these 2MO3 transistors 1.2 are connected to the control circuit 3.

Although not shown, 2MO3 transistors as variable resistance means are similarly connected to other bit lines.
The gate electrodes are respectively connected to the control circuit 3.

The control circuit 3 is composed of a 2MO3 transistor 4 and a constant current source (2MO3 transistor) 5.
The gate and drain of the PMO3 transistor 4 are commonly connected. The PM'O3) transistor 4 has its gates connected to the PMO3 transistors 1 and 2, and forms a current mirror circuit with them.

The constant current source 5 is a 2MO3 transistor whose drain and gate are at the ground GND level. This constant current source 5 is connected in series to the drain of the PMO3 transistor 4, and determines the current flowing through the PMO3 transistor 4.

Here, for example, let the current flowing through PMOS transistor 1 be 11, and the current flowing through 2MO3 transistor 4 be 14.
shall be. Considering the current in the control circuit 3, the current flows from the power supply voltage Vdd to the ground voltage GND, but the current is regulated by the constant current source 5, and the PMO3 transistor 4 is regulated by the constant current source 5. The flowing current I4 has the current value determined by the constant current source 5. Since the 2MO3 transistor 1 and the PMO3I transistor 4 constitute a current mirror circuit, the above current 1 is equal to the above current 4. It is determined by the ratio of the current capacity of In the end, the DC operating current during writing is determined by the current value of the PMOS transistor 4 constituting the current mirror circuit, which in turn is determined by the current value of the constant current source 5. Therefore, by determining the ratio between the constant current value of the constant current source 5 and the current capacity of the transistors forming the current mirror circuit, the DC operating current during writing can be easily adjusted.

Further, in a configuration using such a current mirror circuit, for example, the size of the gate of the constant current source 5 is increased. Then, the rate of parameter variation due to manufacturing variations in the constant current source 5 becomes low. For this reason, even if the size of the PMOS transistor 1.2 as the variable resistance means is small, due to the above proportional relationship,
Fluctuations in the current value of the PMOS transistor 1.2 are suppressed, and the circuit operation of the memory device of this embodiment becomes stable.

Furthermore, PMO3+- transistors 1, 2 and 2MO3
Transistor 4 is the same I'MO3 transistor and is formed by the same manufacturing process. Variations in the gate size, such as gate length and gate width, and in the adjustment process of V, show a -like tendency. Therefore, the DC operating current has a structure that is resistant to manufacturing variations.

Second Embodiment The memory device of this embodiment is a more specific example of the first embodiment.

As shown in FIG. 2, its circuit configuration first includes a memory cell 28 connected to a pair of bit lines BL, BLt. The memory cells 27 are arranged in a matrix like the memory cells 10 of the first embodiment to form a memory cell array. The bit line BL5. At the end of BLt,
PMOS transistors 21 and 22 are formed as MISI transistors used in the variable resistance means. The source side of these 2MO3 transistors 21 and 22 is supplied with the power supply voltage Vdd, and the 2MO3 transistors 21 and 22 are supplied with a power supply voltage Vdd.
The drain side of each bit line BL is connected to the drain side of the bit line BL.

It becomes BLR.

Next, on the control circuit 23 side, from the power supply voltage Vdd side, 2
MO3 transistor 24. PMO3I-ransistor 25
and 2MO3 transistor 26 are connected in series with ground voltage GND, and an NMO3 transistor 27 is formed in parallel with the PMOS transistor 26.

The PMO3 transistor 24 is a transistor forming a current mirror circuit with the PMOS transistors 21 and 22, and its source side is connected to the power supply voltage Vdd, and its drain and gate are connected. The drain of the 2MO3 transistor 24 is connected to the source of the PMOS transistor 25.

The PMO5 transistor 25 is an element that functions as a switch, and has a read/write signal R at its gate.
/W is supplied. The drain of this PMOS transistor 25 is connected to the gates of the PMO3 transistors 21 and 22, and the drain of the PMOS transistor 25 is connected to the gates of the PMO3 transistors 21 and 22.
．． Connected to the NMOS transistor 27 mentioned above.

The PMOS transistor 26 is an element that functions as a constant current source, and the source is the PMOS transistor 2.
5 and the PMOS transistor 21.2.
Connect to gate 2. This 2MO3 transistor 26
The ground voltage GND is applied to the gate as well as the drain.

NM connected in parallel with the PMOS transistor 26
The read/write signal R/W is supplied to the gate of the O3 transistor 27. The source of this NMO3 transistor 27 is connected to the ground voltage GND, and its drain is connected to the gates of the PMOS transistors 21 and 22.

The memory device of this embodiment having such a connection relationship is
Perform the following actions.

First, at the time of reading, the level of the read/write signal R/W is set to □"H" level (high level), the P'MO3 transistor 25 is in the off state, and the NMO
3 transistor 27 is turned on. Then, 2M
The gate voltage of the O3 transistors 21 and 22 becomes approximately the ground voltage GND, and the PMOS transistors 21 and 22 which serve as a load.
22 becomes a high impedance state.

Next, at the time of writing, the above read/write signal R/W
The level of PM is considered to be the "L" level (low level), and the
'O3 transistor 25 is on.

When the NMO5 transistor 27 is turned off, from the power supply voltage Vdd to the ground voltage GND,
1 through PMOS transistors 24, 25, and 26! The flow flows. The current flow causes the 2MO3 transistors 21 and 22 to transition to a low impedance state, and at this time, the value of the current flowing through the 2MO3 transistor 24 is determined by the 2MO3 transistor 26, which functions as a constant current source. Further, the current flowing through the 2MO3 transistors 21 and 22 is also determined by the 31PMOs transistor 24, since the PMO3 transistor 1.2 and the PMO3 transistor 24 constitute a current mirror circuit. Therefore, the impedance value of the 2MO3 transistors 21 and 22 depends on the PMOS transistor 26 as a constant current source and becomes stable.

Further, as in the first embodiment, in the memory device of this embodiment as well, the DC operating current during writing is determined by the current capacity of the 2MO3 transistor 26, which is the constant current source, and the current mirror circuit. It is determined by the ratio of current capabilities of transistors, and can be easily adjusted.

Similarly, by making the size of the PMOS transistor 26 larger than other elements, the rate of parameter variation due to manufacturing variations can be reduced, and the circuit operation of the memory device can be stabilized.

Furthermore, PMO3 transistor 21.22 and PMO
The 3I transistor 24 exhibits a similar tendency to manufacturing variations. Therefore, fluctuations in the DC operating current can be suppressed.

Third Embodiment The third embodiment is a modification of the second embodiment.
This is an example in which the dependence of the OS transistor is increased.

Its circuit configuration is shown in FIG. When compared with the circuit configuration of the second embodiment (see FIG. 2), the PMOS transistor 26 functioning as a constant current source is replaced with an NMo5 transistor 30 in this embodiment. Note that the same reference numerals as in FIG. 2 are used for other circuit parts, and similar explanations will be omitted.

In this way, in the memory device of this embodiment, the transistor functioning as a constant current source of the control circuit 33 is connected to the memory cell 2.
It is said to be an NMOS transistor that is often used in 8 etc.

Therefore, it is possible to reflect the manufacturing parameters of the NMOS transistor in the current value of the constant current source.
The structure is said to be resistant to manufacturing variations in MOS transistors.

Further, in the memory device of this embodiment, as well as the memory devices of the first and second embodiments described above, current control of the transistor of the variable resistance means can be performed stably, and N
By increasing the size of the MOS transistor 30, it becomes resistant to manufacturing variations.

Note that the memory device of the present invention is not limited to the first to third embodiments described above, and various changes can be made without departing from the gist thereof.

〔Effect of the invention〕

In the memory device of the present invention, since the variable resistance means and the MIS transistor used in the control circuit constitute a current mirror circuit, the current capability of the variable resistance means can be made stable, and the DC operating current during writing can be made stable. can be made into a predetermined value regardless of manufacturing variations.

[Brief explanation of the drawing]

FIG. 1 is a main circuit diagram showing a basic circuit configuration of an example of a memory device according to the present invention, FIG. 2 is a main circuit diagram showing a specific circuit configuration of an example of a memory device according to the present invention, and FIG. The figure is a main part circuit diagram showing the circuit configuration of another example of the memory device of the present invention,
FIG. 4 is a circuit diagram of a main part of an example of a prior art memory device. 1.2.21.22...PMO3 transistor 10.
28...Memory cell 3.23.33...Control circuit 4.24...PMO3 transistor 5...Constant current source 26...PMO3 transistor 30...NMO3I-Randjisk patent applicant Sony Corporation Representative Patent Attorney Mi Kobe (and 2 others) The first issue of this issue is that of the first issue of the issue.

Claims (1)

[Scope of Claims] A memory device comprising a memory cell, a bit line connected to the memory cell, a variable resistance means connected to the bit line, and a control circuit for the variable resistance means, the variable resistance means MIS transistors used in
A memory device characterized in that a MIS transistor used in the control circuit constitutes a current mirror circuit.