JPH01138749A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPH01138749A JPH01138749A JP29808487A JP29808487A JPH01138749A JP H01138749 A JPH01138749 A JP H01138749A JP 29808487 A JP29808487 A JP 29808487A JP 29808487 A JP29808487 A JP 29808487A JP H01138749 A JPH01138749 A JP H01138749A
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- film
- silicon layer
- isolation band
- forming
- element isolation
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
[概要コ
半導体装置の製造方法のうち、特に、SOt構造シリコ
ン基板の素子分離帯形成方法に関し、微少な幅の素子分
離帯を形成して、ICデバイスを高集積化することを目
的とし、
絶縁基板上に設けたシリコン層の素子分離帯形成方法に
おいて、遮蔽マスクを設けて前記シリコン層の露出部の
ほぼ半分の膜厚をエツチング除去して溝部を形成し、次
いで、前記遮蔽マスクをそのままにして該溝部に酸素イ
オンを注入して熱処理し、該処理によって生成された酸
化シリコン膜からなる素子分離帯を形成するようにした
ことを特徴とする。[Detailed Description of the Invention] [Summary] Among the methods for manufacturing semiconductor devices, in particular, the method for forming element isolation bands on SOt structure silicon substrates is concerned with forming element isolation bands with minute widths to achieve high integration of IC devices. In a method for forming an isolation band of a silicon layer provided on an insulating substrate, a shielding mask is provided, and approximately half the film thickness of the exposed portion of the silicon layer is etched away to form a groove, and then a trench is formed. , the method is characterized in that oxygen ions are implanted into the groove portion while the shielding mask is left as is, and a heat treatment is performed to form an element isolation band made of a silicon oxide film produced by the treatment.
[産業上の利用分野]
本発明は半導体装置の製造方法のうち、特に、Sol構
造シリコン基板の素子分離帯形成方法に関する。[Industrial Application Field] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an isolation band on a Sol structure silicon substrate.
最近、S OI (Silicon On In5u
lator)技術が開発されており、ビームを照射して
非単結晶性半導体層を再結晶化する結晶基板の形成方法
が知られている。これは従来の平面的なデバイスを三次
元デバイスに配置して高集積化、高性能化することを企
図しているものである。Recently, S OI (Silicon On In5u
A method for forming a crystal substrate in which a non-single crystal semiconductor layer is recrystallized by irradiating a beam is known. This is intended to increase the integration and performance of conventional planar devices by arranging them into three-dimensional devices.
しかし、このようなSol技術によって作成されるSo
l基板に、出来るだけ狭い幅の素子分離帯を設けること
が高集積化のために極めて重要なことである。However, the SoL created by such Sol technology
It is extremely important for high integration to provide an element isolation band as narrow as possible on the substrate.
[従来の技術と発明が解決しようとする問題点]さて、
Sol技術には酸素を高エネルギーでシリコン基板に深
く注入し、熱処理(アニール)して埋没した5i02
(酸化シリコン)膜を形成させるSIMOX法や陽極
化成によって選択的にシリコン基板を多孔質化し、これ
を酸化するFIPO8法が知られているが、三次元デバ
イスに最適な方法は半導体素子の積層プロセスの容易さ
より絶縁性基板上に堆積した非単結晶性のシリコン層を
ビーム照射、ランプ照射によって再結晶する堆積層再結
晶化法である。[Problems to be solved by conventional technology and invention] Now,
The Sol technology involves injecting oxygen deeply into the silicon substrate with high energy and then heat-treating (annealing) the buried 5i02.
The SIMOX method, which forms a (silicon oxide) film, and the FIPO8 method, which selectively makes a silicon substrate porous by anodization and oxidizes it, are known, but the most suitable method for three-dimensional devices is the stacking process of semiconductor elements. This is a deposited layer recrystallization method in which a non-single crystalline silicon layer deposited on an insulating substrate is recrystallized by beam irradiation or lamp irradiation due to its ease of use.
例えば、ビームとして連続発振アルゴンレーザヲ用い、
多結晶シリコン膜やアモルファスシリコン膜(非単結晶
性シリコン層)を再結晶化する方法が採られており、こ
の方法の特徴はビームを照射してシリコン層を一旦溶融
し、その冷却時に結晶成長をおこなって、1つの単結晶
に成長するごとにある。その一般的なSOI構造シリコ
ン基板の形成方法を説明すると、第2図(al〜(C)
にその工程順断面図を示している。For example, using a continuous wave argon laser as the beam,
A method is used to recrystallize a polycrystalline silicon film or an amorphous silicon film (non-monocrystalline silicon layer).The feature of this method is that the silicon layer is melted once by irradiation with a beam, and then crystals grow when the silicon layer is cooled. Each time a single crystal is grown. To explain the method of forming the general SOI structure silicon substrate, Fig. 2 (al to (C)
A cross-sectional view of the process is shown in the figure.
第2図(al参照;シリコン基板1の表面を熱酸化して
膜厚1μm程度の5i02膜2を生成して、絶縁性基板
にする。FIG. 2 (see al; the surface of a silicon substrate 1 is thermally oxidized to form a 5i02 film 2 with a thickness of about 1 μm, making it an insulating substrate.
第2図(b)参照;次いで、その上面に化学気相成長(
CV D)法によって膜厚5000人程度0多結晶シリ
コン層3′を被着する。See Figure 2(b); then chemical vapor deposition (
A polycrystalline silicon layer 3' having a thickness of approximately 5,000 wafers is deposited by the CVD method.
第2図(C1参照;次いで、連続発振アルゴンレーザビ
ームで多結晶シリコン層3°に照射し、スキャンニング
(走査)して単結晶シリコン層3に変成する。その際、
連続アルゴンレーザ(CW−^rLaser)ビームで
走査すると、多結晶シリコン層3°が加熱溶融されて、
凝固時に単結晶シリコン層3に変成されるが、レーザア
ニール条件をレーザスポッ°ト径330−1O0pφ、
レーザ出力lO〜20ワット走査速度5〜10cm/秒
程度、絶縁性基板を温度200〜500℃に加熱してお
けば、シリコン層のメルト幅が数十μm程度になり、凝
固時に単結晶化される。FIG. 2 (see C1; next, the polycrystalline silicon layer 3° is irradiated with a continuous wave argon laser beam, and is scanned to transform it into a single crystalline silicon layer 3. At that time,
When scanning with a continuous argon laser (CW-^rLaser) beam, the polycrystalline silicon layer 3° is heated and melted,
It is transformed into a single crystal silicon layer 3 during solidification, but the laser annealing conditions are set to a laser spot diameter of 330-1O0pφ,
If the insulating substrate is heated to a temperature of 200 to 500°C with a laser output of 10 to 20 watts and a scanning speed of about 5 to 10 cm/sec, the melt width of the silicon layer will be about several tens of μm, and it will become a single crystal during solidification. Ru.
しかし、この時、溶融したシリコン層はメルト幅の中央
より冷却して中央部に核ができ、その核より次第に固化
が周囲に及んで結晶が成長し、全体が単結晶化すること
が重要で、そのため、第2図には図示していないが、レ
ーザ走査線の両側に反射防止膜(例えば、Si3N4膜
)を被覆して両側を高温度に溶融させ、走査線の中心よ
り固化が始まるように構成しており、また、レーザビー
ムは円形スポットで、そのエネルギー分布は通常ガウス
分布をしているが、そのビーム形状を変えてドーナツ状
にしてビーム中心のエネルギーを周囲より低くする等の
方法が採られている。However, at this time, it is important that the molten silicon layer cools from the center of the melt width to form a nucleus in the center, and from that nucleus, the solidification gradually spreads to the surrounding areas and crystals grow, making the whole into a single crystal. Therefore, although not shown in Fig. 2, an antireflection film (for example, Si3N4 film) is coated on both sides of the laser scanning line and both sides are melted at a high temperature so that solidification starts from the center of the scanning line. The laser beam is a circular spot, and its energy distribution is normally Gaussian, but there are methods such as changing the beam shape and making it donut-shaped so that the energy at the center of the beam is lower than the surrounding area. is taken.
このようにして形成したSol構造のシリコン基板に集
積回路(IC)デバイスを作成する場合には、素子間を
電気的に分離するための素子分離帯を形成することが必
要になる。この素子分離帯の形成方法として、例えば、
従前はpn接合分離が用いられていたが、pn接合分離
は5vの電源で3μm程度の幅に形成しなければ十分な
絶縁耐圧を得ることができない。これに対して、5i0
2(酸化シリコン)膜などの絶縁膜分離では分離帯の幅
を狭くして一層の高集積化が可能になるため、最近、絶
縁膜分離がおこなわれている。When creating an integrated circuit (IC) device on the silicon substrate having the Sol structure formed in this manner, it is necessary to form an element isolation band for electrically isolating the elements. As a method for forming this element isolation band, for example,
Conventionally, pn junction isolation has been used, but sufficient dielectric strength cannot be obtained unless the pn junction isolation is formed with a width of about 3 μm using a 5V power supply. On the other hand, 5i0
Insulating film isolation, such as a 2 (silicon oxide) film, allows for even higher integration by narrowing the width of the separation band, so insulating film isolation has recently been carried out.
この従来の絶縁膜による素子分離帯の形成方法を第3図
(a)〜(C)の工程順断面図に示しており、その概要
を説明すると、
第3図(a)参照;まず、絶縁基板ll上に形成した膜
厚5000人の単結晶シリコンN12の上に、S i
O2膜/Si3 N4 (窒化シリコン)膜からなる
保護膜13を選択的に形成して、素子分離帯形成領域の
み露出させる。This conventional method of forming device isolation bands using an insulating film is shown in the step-by-step cross-sectional views of FIGS. 3(a) to 3(C). Si
A protective film 13 made of an O2 film/Si3 N4 (silicon nitride) film is selectively formed to expose only the isolation band forming region.
第3図(b)参照;次いで、素子分離帯形成領域を表面
から2000人程度エフチング除去した後、ウェットな
酸素雰囲気中で900℃、200分熱処理して露出した
単結晶シリコン層12を酸化させ、SiO□膜14を生
成して素子分離帯とする。Refer to FIG. 3(b); Next, after removing the device isolation band forming region from the surface by etching approximately 2,000 layers, the exposed single crystal silicon layer 12 is oxidized by heat treatment at 900° C. for 200 minutes in a wet oxygen atmosphere. , a SiO□ film 14 is formed to serve as an element isolation band.
第3図(C)参照:次いで、5i02膜/Si3 N4
膜からなる保護膜13を除去する。See Figure 3(C): Next, 5i02 film/Si3 N4
The protective film 13 made of a film is removed.
そうずれば、5i02膜14からなる素子分離帯が形成
され、この形成方法はLOCO3法と称して極めて著名
な方法である。By doing so, an element isolation band made of the 5i02 film 14 is formed, and this forming method is a very famous method called the LOCO3 method.
しかし、このLOCO3法はシリコンの酸化を進行させ
るために縦方向にも横方向にも同時に酸化が進行して、
膜厚5000人の単結晶シリコン層であれば最低幅が0
.5μmのSiO3膜となり、それ以上に幅の狭い素子
分離帯を形成することは困難である。However, in this LOCO3 method, the oxidation of silicon proceeds simultaneously in both the vertical and horizontal directions.
For a single crystal silicon layer with a thickness of 5000, the minimum width is 0.
.. The SiO3 film has a thickness of 5 μm, and it is difficult to form an element isolation band narrower than that.
他方、5i02膜の電界強度はQ、l メrrnの厚さ
で50V以上になるから、5v電源で駆動するデバイス
はSiO□膜からなる素子分離帯の幅は0.1 μm程
度もあれば十分な絶縁耐圧が得られる。On the other hand, since the electric field strength of the 5i02 film is 50V or more at the thickness of Q, lmerrn, it is sufficient for devices driven by a 5V power source to have a width of the device isolation band made of the SiO□ film of about 0.1 μm. A high dielectric strength voltage can be obtained.
従って、本発明はLOCOS法などによる素子分離帯よ
りも更に微少な幅のSiO3膜からなる素子分離帯を形
成して、ICを高集積化することを目的とした製造方法
を提案するものである。Therefore, the present invention proposes a manufacturing method for the purpose of highly integrating an IC by forming an element isolation band made of a SiO3 film with a width even smaller than the element isolation band formed by the LOCOS method. .
[問題点を解決するための手段]
その目的は、遮蔽マスクを設けて前記シリコン層の露出
部のほぼ半分の膜厚をエツチング除去して溝部を形成し
、次いで、前記遮蔽マスクをそのままにして該溝部に酸
素イオンを注入して熱処理し、該処理によって生成され
た酸化シリコン膜からなる素子分離帯を形成するように
した半導体装置の製造方法によって達成される。[Means for Solving the Problems] The purpose is to provide a shielding mask, remove approximately half the thickness of the exposed portion of the silicon layer to form a groove, and then leave the shielding mask as it is. This is achieved by a method of manufacturing a semiconductor device in which oxygen ions are implanted into the groove portion, heat treatment is performed, and an isolation band made of a silicon oxide film produced by the treatment is formed.
[作用]
即ち、本発明は、絶縁基板上に設けたシリコン層の素子
分離帯形成予定領域を、遮蔽マスクを設けてシリコン層
の露出部のほぼ半分の膜厚をエツチング除去し、その遮
蔽マスクを設けたまま溝部の下層に酸素イオンを注入し
て、熱処理する。そうすると、その溝部に5i02膜が
生成され、SiO2膜で埋まった素子分離帯が形成され
る。且つ、その幅はエツチング幅で規制されて、0.1
μm程度の微少な幅の素子分離帯が形成できる。[Operation] That is, in the present invention, a shielding mask is provided in a region of a silicon layer provided on an insulating substrate where an element isolation band is to be formed, and approximately half of the film thickness of the exposed portion of the silicon layer is etched away, and the shielding mask is removed. Oxygen ions are implanted into the lower layer of the groove while the groove is left in place, and heat treatment is performed. Then, a 5i02 film is generated in the groove, and an element isolation zone filled with the SiO2 film is formed. Moreover, the width is regulated by the etching width and is 0.1
An element isolation band with a minute width of about μm can be formed.
[実施例] 以下、図面を参照して実施例によって詳細に説明する。[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.
第1図(al〜(dlは本発明にかかる素子分離帯の形
成方法の工程順断面図である。FIG. 1 (al to (dl) are sectional views in the order of steps of a method for forming an isolation band according to the present invention.
第1図(a)参照;まず、シリコン基板上に絶縁膜を形
成した絶縁基板11上に、膜厚5000人の多結晶シリ
コン膜を成長し、連続アルゴンレーザでレーザアニール
して単結晶シリコン層12に変成する。Refer to FIG. 1(a); First, a polycrystalline silicon film with a thickness of 5,000 wafers is grown on an insulating substrate 11 in which an insulating film is formed on a silicon substrate, and a monocrystalline silicon layer is formed by laser annealing with a continuous argon laser. Transforms into 12.
第1図(b)参照;次いで、5i02膜/Si3N4膜
等からなる保護膜15(遮蔽マスク)を被覆し、幅0゜
1μmの素子分離帯形成領域のみ露出させた後、弗素系
反応ガスを用いたりアクティブイオンエツチング(RI
E)によって単結晶シリコン層12を2500人 (
半分の厚さ)程度の深さにエツチングして、幅0.1
μm、深さ0.25μmの溝部16を形成する。Refer to FIG. 1(b); Next, a protective film 15 (shielding mask) made of a 5i02 film/Si3N4 film, etc. is coated to expose only the device isolation band forming region with a width of 0°1 μm, and then a fluorine-based reactive gas is applied. Active ion etching (RI)
E) to form a single crystal silicon layer 12 by 2,500 people (
Etch to a depth of about half the thickness, and a width of 0.1
A groove portion 16 having a thickness of 0.25 μm and a depth of 0.25 μm is formed.
第1図(e)参照;次いで、基板全体を600℃に加熱
し、酸素イオンビームを加速エネルギー100にeV
。See Figure 1(e); Next, the entire substrate is heated to 600°C, and the oxygen ion beam is accelerated to 100 eV.
.
ドーズ遭2.2 X 10 / catの条件で溝部
16に注入する。なお、この酸素イオンは保護膜15を
設けたまま注入する。Inject into the groove 16 at a dose of 2.2 x 10/cat. Note that this oxygen ion is implanted with the protective film 15 provided.
第1図(d)参照;次いで、窒素雰囲気中において13
00〜1400℃、30分間熱処理すると、溝部の下層
が酸化されて5iO7膜17となり、ごの5i02膜1
7は体積がほぼ倍に膨脂して溝部が埋没され、幅0.1
μmの微少なS i 02膜17からなる素子分離帯が
形成される。この際、溝部に酸素イオンを注入すると、
酸素イオン濃度は中心が高く、周囲に次第に低くなった
形状の山形分布になるが、高温に熱処理すると高濃度部
分の酸素は横方向に拡散し、低濃度部分は高濃度部分に
酸素が吸い寄せられる移動が起こって、らようど溝部の
形状に合致した5i02膜が生成された形状になる。See Figure 1(d); then in a nitrogen atmosphere
When heat-treated at 00 to 1400°C for 30 minutes, the lower layer of the groove is oxidized to become the 5iO7 film 17, and the 5i02 film 1
7, the volume has expanded to almost double, the groove is buried, and the width is 0.1
An element isolation zone made of a minute S i 02 film 17 of μm size is formed. At this time, if oxygen ions are implanted into the groove,
The oxygen ion concentration is high in the center and gradually becomes lower at the periphery, forming a mountain-shaped distribution, but when heat-treated to high temperatures, the oxygen in the high-concentration areas diffuses laterally, and the low-concentration areas attract oxygen to the high-concentration areas. As a result of the movement, the 5i02 film is shaped to match the shape of the groove.
従って、本発明にかかる製造方法によれば、従来の幅0
.5μmよりも幅0.1 μm程度に小さくした素子分
離帯を形成することができる。なお、上記方法に代わり
、単結晶シリコン層12の厚み全部をエツチング除去し
て溝部を形成し、その溝に絶縁膜を気相成長法で埋没す
る方法も考えられるが、外部より被着して幅0.1 μ
m程度の1敦少な溝部を完全に埋没させることは困難で
ある。そのため、本発明にかかる形成方法が最も適して
いるものである。Therefore, according to the manufacturing method according to the present invention, the conventional width is 0.
.. It is possible to form an element isolation band whose width is smaller than 5 μm to about 0.1 μm. Note that instead of the above method, it is also possible to remove the entire thickness of the single-crystal silicon layer 12 to form a groove, and bury an insulating film in the groove by vapor phase growth. Width 0.1μ
It is difficult to completely bury a groove of about 1 m in length. Therefore, the forming method according to the present invention is most suitable.
[発明の効果]
以上の説明から明らかなように、本発明によれば従来の
115程度に微少な幅の素子分離帯を有するICデバイ
スが形成できて、その高RJn化。[Effects of the Invention] As is clear from the above description, according to the present invention, it is possible to form an IC device having an element isolation band with a width as small as 115 mm compared to the conventional device, and its RJn can be increased.
高性能化に大きく貢献するものである。This greatly contributes to higher performance.
第1図(al〜(dlは本発明にかかる形成方法の工程
順断面図、
第2図(a)〜(C)はSo [5板の形成方法の工程
順断面図、
第3図(a)〜(C)は従来の形成方法の工程順断面図
である。
図において、
Uは絶縁基板、
12は単結晶シリコン層、
15は保護膜(遮蔽マスク)、
16は溝部、
17は5i02膜(素子分離帯)
不発θ小:?・p−3形八゛方法のエネ呈1傾鉾面の第
1図
第2図FIG. 1 (al to (dl) are step-by-step sectional views of the forming method according to the present invention, FIG. 2 (a) to (C) are step-by-step sectional views of the forming method of the So ) to (C) are step-by-step sectional views of the conventional forming method. In the figures, U is an insulating substrate, 12 is a single crystal silicon layer, 15 is a protective film (shielding mask), 16 is a groove, and 17 is a 5i02 film. (Element separation band) Misfire θ small: ?・P-3 type 8゛ method energy presentation 1 Figure 2 of inclined surface
Claims (1)
において、遮蔽マスクを設けて前記シリコン層の露出部
のほぼ半分の膜厚をエッチング除去して溝部を形成し、
次いで、前記遮蔽マスクをそのままにして該溝部に酸素
イオンを注入して熱処理し、該処理によつて生成された
酸化シリコン膜からなる素子分離帯を形成するようにし
たことを特徴とする半導体装置の製造方法。In a method for forming an isolation band of a silicon layer provided on an insulating substrate, a shielding mask is provided and approximately half the film thickness of the exposed portion of the silicon layer is etched away to form a groove portion;
Next, oxygen ions are implanted into the groove portion with the shielding mask left as is, and heat treatment is performed to form an element isolation band made of a silicon oxide film produced by the treatment. manufacturing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29808487A JPH01138749A (en) | 1987-11-25 | 1987-11-25 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29808487A JPH01138749A (en) | 1987-11-25 | 1987-11-25 | Manufacturing method of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01138749A true JPH01138749A (en) | 1989-05-31 |
Family
ID=17854948
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29808487A Pending JPH01138749A (en) | 1987-11-25 | 1987-11-25 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01138749A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04324642A (en) * | 1991-04-24 | 1992-11-13 | Sanyo Electric Co Ltd | Manufacture of insulated gate type semiconductor device |
KR970067767A (en) * | 1996-03-12 | 1997-10-13 | 문정환 | Method for forming a separation film of a semiconductor element |
-
1987
- 1987-11-25 JP JP29808487A patent/JPH01138749A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04324642A (en) * | 1991-04-24 | 1992-11-13 | Sanyo Electric Co Ltd | Manufacture of insulated gate type semiconductor device |
KR970067767A (en) * | 1996-03-12 | 1997-10-13 | 문정환 | Method for forming a separation film of a semiconductor element |
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