JPH01138587A - display control device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a display control device that displays characters, images, graphs, etc. on a display screen.

[Conventional technology]

In order to display characters, images, and graphs, a display control circuit using a bitmap refresh method is used that stores the brightness and darkness of each pixel on the screen as 1 and 0.

In word processors and the like to which the display control circuit is applied, high-speed responsiveness is required when performing screen display in response to operator input. What most requires high-speed response in screen display is the scrolling operation to see parts that are not displayed when approaching the screen, and Japanese Patent Application Laid-Open No. 1983-1999 describes the display address structure for vertical scrolling.
It is disclosed in Japanese Patent No. 22184.

FIG. 8 is a block diagram of a conventional display control circuit, in which 1 is a CRT controller, 2 is an address conversion circuit, 3 is a screen memory for storing display data, and 4 is a block diagram for storing parallel display data read from the screen memory. A parallel-to-serial converter (P-3) converts the serial data into a video (VIDEO) signal, and 5 is a dot clock generation circuit that determines the sending timing of the VIDEO signal.

FIG. 9 is a detailed diagram of the address conversion circuit 2.
2 is a decoder that decodes the address (ra) output from the CRT controller 1 and outputs logic "1" only when the display data "A" is displayed (hereinafter referred to as A screen);
2 is set to logic "1" by the CPU (not shown) only when drawing (writing) display data for the A screen to the screen memory 3.
23 is a selector that selects and outputs either the output of the re-decoder 21 or the register 22 based on the output from a mode register (not shown) that determines whether or not to enter the drawing mode; 24 is an AND circuit; 25 is CRT
Area where display data “B” of controller 1 is displayed (
Output from the display start address register (8 screens below)
8 screen display start address β) and the output from the address register currently being executed (actual row address α), and if the actual row address α is larger, the output is set to logic “1”.
The comparator 26 is set to 8 by an instruction from a CPU (not shown).
27 is an adder, and 28 is a selector that selects and outputs either the actual row address α or the output of the adder 27 based on the output from the AND circuit 24. Sends address signal to screen memory 3.

This address conversion unit operates as follows. 7 (1) When drawing to the screen memory 3 (a) The CPU (not shown) sets the mode register to the drawing mode, and the display start address β of both sides of B is stored in the register 26. Two's complement is set.

Cb') Drawing of A screen display data The CPU (not shown) sets the register 22 (the output is logic "1"), inputs this to one terminal of the AND gate 24 via the selector 23, and (a) α If β, the output of the comparator 25 becomes logic "O", the output of the AND gate 24 also becomes logic "0", and the output α is selected by the selector 28 and becomes the address of the screen memory 3, and data is drawn at this address. . (A” in FIG. 10(a), A1゜A゛2) (b) If α>β, the output of the comparator 25 becomes logic “1”, the output of the AND gate 24 becomes logic “1”, and the selector 28 The output T of the adder 27 is selected and becomes the address of the screen memory 3, and data is drawn at this address. (A"2 in FIG. 10(b)) (c) Drawing figures other than A screen display data are not shown. The register 22 is reset by the CPU (the output is logic "0"), and this is inputted to one terminal of the AND gate 24 via the selector 23. As a result, the output of the AND gate 24 becomes logic "0", and the selector 28 selects the output α, which becomes the address of the screen memory 3 and data is drawn at this address.

(2) Display (a) A mode register is set to display mode by a CPU (not shown).

(b) The output of the display decoder 21 on the A screen becomes logic "1" and one terminal of the AND gate 24 becomes logic "1" via the selector 23. (a) If α<β, output α as in the case of drawing. is screen memory 3
will be the address, and the data of this address will be displayed.

(A'', AI, A' 2 in Figure 10 (C)) (b) α〉
If β, the output γ of the adder 27 becomes the address of the screen memory 3, and the data at this address is displayed, as in the case of drawing.

(A″2 in FIG. 10(c)) (c) The output of the display decoder 21 for screens other than the A screen becomes logic “0”, which is input to one terminal of the AND gate 24 via the selector 23, and is input to one terminal of the AND gate 24. The output becomes logic "0" and 1. The selector 28 makes the output α the address of the screen memory 3, and the data at this address is displayed.

As explained above, in this conventional example, the display data A''2 in the portion where the display data A2 and B overlap is shown in FIG. 10(b).
Since the image is automatically drawn as shown in FIG. 1, a vertical scroll screen of display data "A" can be obtained by arbitrarily changing the display start address of display data "A". - Incidentally, in word processors and the like to which such display control circuits are applied, high-speed responsiveness is also required for the left and right scrolling operations for viewing undisplayed portions that approach the screen. However, with this method, simply changing the display start address of display data "A" to any address on the left or right side of the display screen will not allow the display screen to compare with the previous screen because the address signal output from the CRT controller is continuous. As a result, the display screen is shifted by an arbitrary address, resulting in a vertical shift in the forward raster direction.

In a display control circuit that uses the bitmap pre-refresh method, the following methods are used to scroll the screen left and right:
For this reason, it has been common practice to move all of the display data in blocks in a designated direction, and then draw the newly appearing screen in the empty area.

The scrolling of the display control circuit disclosed in Japanese Patent Application Laid-Open No. 60-22184 is for vertical scrolling, and the address structure for horizontal scrolling is not considered.

[Problem that the invention seeks to solve]

If you want to scroll the display screen left and right as above,
All of the display data is moved in blocks in the specified left/right direction, and the newly appearing screen is drawn in the vacant area. This requires moving a large amount of data in the bitmap memory when scrolling the screen left and right.
It was difficult to say that it was suitable for high-speed processing.

An object of the present invention is to further improve the operability of a document processing device such as a word processor by increasing the speed of horizontal scrolling of the screen compared to conventional methods in a display control device that employs a bitmap refresh method. It is something to do.

[Means for solving problems]

In order to achieve this object, the present invention includes a bitmap type screen memory that stores screen data pixel by pixel, and a CR that repeatedly reads screen data from this screen memory and generates a refresh address to display it on a CRT display.
a T controller, an address conversion control register in which a display start address of the screen memory is set, and the CRT
In a display control device equipped with an address conversion circuit that converts a refresh address from a controller into a screen memory address based on a display start address set in the address conversion control register, the number of addresses of display data per raster on a display screen a raster register for setting, and a comparison means for comparing the sum of the shift amount between the start end address in the raster direction of the screen memory and the display start address and the refresh address from the CRT controller with the number of addresses set in the raster register. and selecting means for selectively outputting either the sum address or an address obtained by subtracting the number of addresses set in the raster register from the sum address as the screen memory address, based on the comparison result. It is characterized by

[Effect]

The refresh address output from the CRT controller is converted into a screen memory address based on the display start address in the raster direction on the screen memory set in the address conversion control register, and is applied to the screen memory. When the comparing means detects that this screen memory address has reached the end of the raster on the screen memory, the fresh address from the CRT controller is returned to the start end of the raster on the screen memory. is addressed in a loop.

Then, when the operator instructs horizontal scrolling, the display start address is rewritten, and the screen data in the screen memory area between the display start address before scrolling and the display start address after scrolling is updated.

〔Example〕

The present invention will be described below based on an embodiment shown in the drawings. This embodiment divides the screen memory into multiple screen areas,
In a display control device capable of continuous vertical scrolling by memory wrap-around of a divided screen of a display device that simultaneously displays the plurality of divided screen areas on a display screen, the left and right sides of the display screen are converted into addresses in a loop, This is an example of configuring a round screen.

FIG. 1 shows the overall block diagram of the screen control circuit.

In FIG. 1, the screen control circuit operates according to instructions from the CPU, but the description of the CPU, which is comprised of a microcomputer or the like, will be omitted here.

Control from the CPU is performed by signals via the CPU bus.

Reference numeral 1 denotes a CRT controller, which is controlled by the CPU via the CPU bus and generates successive signals and synchronization signals for the screen memory 3 to form a screen on the CRT monitor 8.

Reference numeral 7 denotes an oscillation circuit consisting of a crystal oscillator or the like, which supplies an operating clock for the screen control circuit. A timing generator 5 generates control signals for the entire screen control circuit, and controls access to the screen memo I73 from the CRT controller 1 and the CPU in a time-sharing manner. Reference numeral 3 denotes a screen memory, which constitutes a bitmap memory for storing whether each bit (one pixel) of the display bits constituting the screen is a bright spot or a dark spot. Reference numeral 4 denotes a shift register which inputs display data read from the screen memory 3 in parallel and outputs it in series, and this output is given to the CRT monitor 8 as a video signal.

The CRT monitor 8 uses a video signal and a synchronization signal to
Display the screen raster on T. Reference numeral 6 denotes an address conversion control register circuit for storing addresses necessary for performing the operation of the memory wrap-around configuration within the divided screen. 2 is an address for converting the screen refresh address (ra) from the CRT controller 1, based on the address set in the address conversion control register 6, so as to perform the memory wrap configuration operation of vertically scrolling within the split screen. It is a conversion circuit. Reference numeral 9 denotes a raster register circuit for storing the number of addresses per raster necessary to carry out the operation of the round screen configuration for horizontal scrolling, which will be described later. Reference numeral 10 denotes an address comparison circuit in which the address conversion control register circuit 6 and the raster register circuit 9 compare the screen refresh address (ra) from the CRT controller 1 to generate an address for performing a round screen configuration operation of horizontal scrolling. It is a circuit.

Next, the overall operation of the screen control circuit shown in FIG. 1, excluding the round screen configuration that scrolls left and right, will be explained. This is the case when the refresh address ra2 that is output is considered to be through.)

The CRT controller 1 constantly refreshes the screen according to the parameters set by the CPU, and in order for the address conversion control register circuit 6 and the address conversion circuit 2 to operate, the start address register in the CRT controller 1 is set to 0. Set. Here, screen refresh refers to the horizontal direction relative to the CRT monitor 8.
This means generation of a vertical synchronization signal and an address for reading out the screen memory 3.

The timing generator 5 gives a screen refresh address to the screen memory 3 through the address conversion circuit 2 according to instructions from the CRT controller 1, and the display data read from the screen memory 3 is sent to the shift register 4.
is input to the CR and output in series as video data.
The display screen of the T monitor 8 is formed.

On the other hand, drawing of display data to the screen memory 3 is performed by C.
This is done by the PU through the CPU bus.

A write instruction from the CPU is given to the timing generator 5, and an address that is passed between screen refreshes instructed by the CRT controller 1 is given to the screen memory 3 through the address conversion circuit 2, and display data is written to the screen memory 3. forms characters and figures on the screen memory 3.

Here, the operation of the memory wrap-around configuration for vertical scrolling will be explained using the block diagram of FIG. 5 for the address translation control register circuit 6 and the address translation circuit 2. This is the case when it is considered that the refresh address ral inputted to the address comparison circuit 10 and the refresh address ra2 outputted are passed through in FIG. 5.

In FIG. 5, 61 is a C bus given from the CPU bus.
This is a decoder for decoding PU instructions and providing them to each register. 62 is the start address (value of the output address of the CRT controller 1) of the lower screen that is divided into screens (
This is a register (referred to as SA register) that stores data (referred to as SA). Reference numeral 63 denotes a register (referred to as DSAI register) for storing a display start address (referred to as DSAI) of the upper screen divided into screens on the screen memory.

Reference numeral 64 denotes a register (referred to as DSA2 register) for storing a display start address (referred to as DSA2) of the lower screen divided into screens on the screen memory. Reference numeral 65 denotes a register (referred to as VSA register) for storing the first address (referred to as VSA) of the upper screen area of the divided screen on the screen memory. On the other hand, the address conversion circuit 2 includes a subtracter 221.224, an adder 222.223.225,
It consists of selectors 226, 227, and 228, each of which has the required number of bits. Therefore, each subtracter outputs an output Z (-A-B) and a borrow output B for inputs A and B, and each adder outputs an output Z (=A+B) and a carry output for inputs A and B. If the input S is 1 for the inputs DA and DB, each selector outputs the output C.
If A is O, select input DB and output Y.

Next, referring to the circuit diagram shown in FIG. 5, FIGS. 6 and 7 schematically show the relationship between the screen memory and the display screen.
A case in which memory wrap is configured within a screen division will be described based on the diagram.

Here, the upper screen is a text area, and the lower screen is used for a system area.

Note that FIG. 6 shows a case where no operation that constitutes memory wrap-around is performed, and D indicates the display start area.
Based on the contents of the SAI register 63 and the DSA2 register 64, the data in the screen memory 3 schematically shown in FIG.
Form as shown in figure (b). When the screen is scrolled upward to see the lower part of the content shown in area A in FIG. 6(b), the CPU
The content of is rewritten to an address indicating the downward area in FIG. 6(a), and text (for example, a portion of text for new display) is drawn in the part of the screen memory 3 to be newly displayed.

Next, if you continue scrolling, you will finally get to A.
The 95 area and the B area overlap. At this time, as shown in FIG. 7, area A is cut at the address value stored in the DSA2 register 64, and area C is then displayed. In other words, during such scroll processing, the DS
The A register 63 is set and new data is drawn in the portion corresponding to the Cel area. The screen memory area shown in FIG. 7(a) becomes as shown in FIG. 7(b) on the display screen.

Address translation times to meet these relationships! The output camera def eye address (er
a), the contents of each register (in FIGS. 5 to 7, the register name expressed in lowercase letters is the register contents value), the subtracter 221, and the adder 2230.
The relational expression with the CRT address (ra) that is input to input terminal A is as follows.

ra<sa, ra-sa<O: AtrM region mra=ra
+dsal ra2:sa, ra-sa≧ORB area mra=dsa
2+ra-3a ra+dsal ≧dsa2 ra-(dsa2-dsal)≧0; C area mra=r
a+dsal-dsa 2+vsa=vsa+ra
-(dsa 2 + dsal) As is clear from the above, when the divided screen of the display device is memory wrapped and continuously scrolled up and down, the up and down scrolling is performed by changing the display start address and drawing new data.

Next, the raster register circuit 9 and address comparison circuit 10 for horizontal scrolling according to the present invention will be explained in detail using FIG. 2.

In FIG. 2, a raster register circuit 9 includes a decoder 91 for decoding a CPU instruction given from a CPU bus and applying it to a raster register 92, which will be described later, and a raster register ( (referred to as RR) consists of 92. On the other hand, the address comparison circuit 10 consists of a subtracter 101, 102, a register 103, 104, and a selector 105.
Only the required number of bits are prepared for each.

Next, referring to the circuit diagram shown in FIG. 2, FIGS. 3 and 4 schematically show the relationship between the screen memory and the display screen.
The operation when configuring a round screen within a split screen will be explained based on the diagram.

First, with reference to FIG. 3, the configuration of a round screen when memory wrap is not configured will be described. This is the same as when there is no address conversion circuit 2 in FIG. 5, and the address ral is considered as the address (ra) from the CRT controller 1, and the address ra2 is considered as the screen memory address ra in FIG. be able to.

As shown in FIG. 3(a), when the DSA register 63 is set to address DSAI' in the middle of the raster, the subtracter 101 that compares the number of addresses per raster calculates
Refresh address ra from CRT controller 1
(For example, a few bits indicating the vertical address of the display screen) and
The number of addresses (RR-1) set in the raster register circuit 9 that stores the number of addresses per raster is compared, and the next raster is sequentially indicated. The register 103 receives the borrow output B of the subtracter 101 as a clock, and when the borrow output B changes from O to 1, the output Q (
Q's bar) is set to O, the other register 104 is cleared, and the input DA is output from the output Y of the selector 105. Further, the borrow output B of the subtracter 102 is input to the clear terminal CLR of the register 103, and when the borrow output B changes from 1 to O, the register 103 is cleared. On the other hand, the subtracter 102 uses the addresses ra and DS
The address obtained by adding AIo (for example, several bits indicating the vertical address of the display screen) is compared with the raster register circuit 9 (RR-1) that stores the number of addresses per raster, and the highest address in the screen memory is compared. The left edge is detected and the address ra is converted to the rightmost edge of the screen memory, which is the same raster, so that the left and right sides of the display screen are looped, and a borrow output B is generated to form a round screen. The register 104 receives the borrow output B of the subtracter 102 as a clock, and when the borrow output B changes from O to 1, the output Q
is set to 1, and the input DB is output from the output Y of the selector 105. When the input S is O, the selector 105 selects the address r.
a+dsal', and when the input S is 1, the address r a +DSA1'' = (RR-1) is output.

As is clear from the above, the display screen when A is drawn in area A of the screen memory in FIG. 3(a) and the DSAI register 63 is set in the middle of the raster is shown in FIG. 3(b). Simply put, DSAIo is at the top of the display screen, and the display screen can be scrolled to the left without vertical deviation in the raster forward direction, and the left and right sides of the display screen are looped to form a round screen. Can be done.

Figure 4 shows a case where a memory wrap round is configured, which is a combination of the memory wrap round and round screen described above, and the display screen of the screen memory in Figure 4 (a) is It is easy to understand that the information is displayed as shown in Figure 4 (b). In other words, as shown in Figure 5,
The adder 2 in the address conversion circuit 2 in the address conversion control register circuit 6 and the address conversion circuit 2 in the address conversion control register circuit 6 constitutes the memory wrap round.
It should be connected to the output Z of 23.

As described above, the present invention provides a display control device that adopts the bitmap refresh method as a screen refresh method, and when scrolling the screen left and right, which requires high-speed processing, the left and right scrolling operation is performed by changing the display start address and drawing new data. , the conventional left and right screen
There is no longer a need to move all of the display data in a designated direction as in roll processing, and the screen can be scrolled left and right with a much smaller amount of data processing than in the past.

By the way, the explanation of the illustrated embodiment is that among each divided screen divided into a text area and a system area, the screen memory in the text area is converted into addresses in a loop from side to side to form a round screen within a designated memory block. Although the above-described horizontal scrolling process of the screen can be performed in the text area, the system area, or even both the text area and the system area, the screen area can be used in both the text area and the system area.

In the illustrated embodiment, the CRT controller 1,
Address conversion control register circuit 6, address conversion circuit 2
, the raster register circuit 9, and the address comparison circuit 10 are each made into separate blocks. However, if circuit integration technology is used, the address conversion control register circuit 6, the address conversion circuit 2, the raster register circuit 9, and the address comparison circuit 10 and 1 inside the CRT controller 1.
It is easy to make one LSI.

〔Effect of the invention〕

As described above, the present invention provides a round screen by performing address conversion on the left and right sides of the display screen in a loop using the screen memory using a raster register and an address comparison circuit in a display control device that adopts the bitmap refresh method as a screen refresh method. By configuring this, when the operator specifies scrolling to view the right or left side of the screen where the contents of the screen are not visible, the screen will be scrolled left and right by changing the display start address and drawing a new page. . Therefore, there is no longer a need to move all of the displayed data in blocks in the specified direction, as in the conventional horizontal scrolling process of the screen, and the screen can be scrolled horizontally with a much smaller amount of data processing than before. This allows the processing results in response to the operator's instructions to be displayed on the screen in a short time.

[Brief explanation of the drawing]

The drawings show an embodiment of the display control device according to the present invention, in which FIG. 1 is an overall block diagram of the screen control circuit, and FIG. 2 shows the raster register circuit and address comparison circuit shown in FIG. The block diagrams of FIGS. 3(a) and (b) and FIGS. 4(a) and (b) schematically illustrate the relationship between the screen memory and the CRT monitor (display screen) shown in FIG. 1, respectively. FIG. 5 is a block diagram of the address translation circuit and address translation control register circuit shown in FIG. 1, FIGS. 6(a) and (b), and FIG.
Figures (a) and (b) are explanatory diagrams schematically showing the relationship between the screen memory and the CRT monitor (display screen) shown in Figure 1, respectively, and Figure 8 is a block diagram of a conventional display control circuit. , FIG. 9 is a block diagram of the address conversion circuit of FIG. 8, and FIGS. 10(a), (b), and (c) are diagrams explaining the operation of FIG. 9. 1...CRT controller, 2...address conversion circuit, 3...screen memory, 6...
...Address conversion control register, 8...CR
T monitor, 9... Raster register circuit, 10.
...Address comparison circuit. Figure 1 1: cRT controller 10: Address comparison circuit ) (b) Screen memory (C) Procedural amendment (armpit) l Display of the case Patent Application No. 193753/1983 2 Name display control device of the invention 3 Person making the amendment Relationship with the case Patent applicant (510) Co., Ltd. Hitachi, Ltd. 4 Agent December 20, 1988 6 Number of inventions increased by amendment None 7 Drawing subject to amendment 8 Contents of amendment Figure 4 of the drawing is amended as shown in Figure 4 of the amended drawing attached. . 1+-1--11〆'

Claims (1)

[Claims] 1. A bitmap screen memory that stores screen data pixel by pixel, a CRT controller that repeatedly reads screen data from this screen memory and generates a refresh address to display it on a CRT display, and a display start address of the screen memory. In a display control device comprising: an address conversion control register in which is set; and an address conversion circuit that converts a refresh address from the CRT controller into a screen memory address based on a display start address set in the address conversion control register. , a raster register for setting the number of addresses of display data per raster on the display screen, and a raster register that calculates the sum of the shift amount between the start end address in the raster direction of the screen memory and the display start address, and the refresh address from the CRT controller. a comparison means for comparing with the number of addresses set in the raster register, and based on the comparison result, selectively selects either the sum address or the address obtained by subtracting the number of addresses set in the raster register from the sum address. 1. A display control device comprising: selection means for outputting as a screen memory address.