JPH01137634A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01137634A JPH01137634A JP29681187A JP29681187A JPH01137634A JP H01137634 A JPH01137634 A JP H01137634A JP 29681187 A JP29681187 A JP 29681187A JP 29681187 A JP29681187 A JP 29681187A JP H01137634 A JPH01137634 A JP H01137634A
- Authority
- JP
- Japan
- Prior art keywords
- resist
- dry etching
- layer
- exposure
- resist pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 11
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 238000001312 dry etching Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 14
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 5
- 239000000758 substrate Substances 0.000 claims abstract description 4
- 239000000463 material Substances 0.000 claims description 3
- 125000004836 hexamethylene group Chemical group [H]C([H])([*:2])C([H])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])[*:1] 0.000 claims description 2
- 229910000838 Al alloy Inorganic materials 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 claims 1
- FFUAGWLWBBFQJT-UHFFFAOYSA-N hexamethyldisilazane Chemical compound C[Si](C)(C)N[Si](C)(C)C FFUAGWLWBBFQJT-UHFFFAOYSA-N 0.000 claims 1
- 239000011248 coating agent Substances 0.000 abstract description 3
- 238000000576 coating method Methods 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 4
- 230000018109 developmental process Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 108010057516 2-hydroxymuconic semialdehyde dehydrogenase Proteins 0.000 description 1
- 102100033983 Serpin-like protein HMSD Human genes 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 229920005601 base polymer Polymers 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
Landscapes
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Abstract
Description
【発明の詳細な説明】
[発明の目的〕
(産業上の利用分野)
本発明は半導体装置の製造方法に関するもので、特にフ
ォトレジストを使用した微細パターンを形成し、ドライ
エツチングする際に用いられるものである。[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular is used when forming a fine pattern using a photoresist and performing dry etching. It is something.
(従来の技術)
従来、半導体装置の製造時におけるフォトリソグラフィ
ー工程では、レジスト塗布・露光・現像を行なってレジ
ストパターンを形成°した後、ボストベークを行ない、
次にドライエツチングを行なっている。この場合、ドラ
イエツチングにおける選択比(=被加工材ゝ料のエツチ
ング速度/レジストのエツチング速度)が充分に太き(
ならず、加工精度やスループットが悪化している。一方
、遠紫外光あるいは紫外光を用いたキユアリング処理を
行なっても、ドライエツチングにおけるレジスト形状の
劣化を防止することはできても、選択比が向上する結果
とはならない。 ′(発明が解決しようとする問題点
)
上記問題点を解決する一番簡単な方法として、レジスト
膜厚を厚くすることが考えられるが、膜厚を厚(した場
合、解像力の低下及びパターン形成に必要な露光エネル
ギーの増加を伴う等の問題がある。(Prior Art) Conventionally, in the photolithography process during the manufacture of semiconductor devices, a resist pattern is formed by resist coating, exposure, and development, and then a post bake is performed.
Next, dry etching is performed. In this case, the selectivity ratio in dry etching (=etching speed of workpiece material/etching speed of resist) is sufficiently large (
However, processing accuracy and throughput are worsening. On the other hand, even if curing treatment using deep ultraviolet light or ultraviolet light is performed, deterioration of the resist shape during dry etching can be prevented, but the selectivity does not improve. (Problems to be Solved by the Invention) The easiest way to solve the above problems is to increase the thickness of the resist film. There are problems such as an increase in the exposure energy required.
更に、解像力を低下させることなく厚膜化する方法とし
て多層レジストプロセス等もあげられるが、プロセスが
複雑になり、コスト、スループットの点で問題がある。Furthermore, a multilayer resist process can be cited as a method of increasing the film thickness without reducing resolution, but the process becomes complicated and there are problems in terms of cost and throughput.
本発明は、レジストパターン形成後、簡単な処理を行な
うことにより、ドライエツチング時の選択比を向上させ
ることを目的とする。An object of the present invention is to improve the selectivity during dry etching by performing a simple process after forming a resist pattern.
(問題点を解決するための手段と作用)本発明は、半導
体基板上にフォトレジストを塗布し、これにパターン形
成−のための露光及び現像を行ない、レジストパターン
を形成した後、全面露光を行ない、更にSiを含有する
ガス中に上記レジストをさらした後、ドライエツチング
を行なうことを特徴とする半導体装置の製造方法である
。即ち本発明は、レジスト塗布、露光及び現像により得
られたレジストパターンを全面露光したのち、Siを含
有するガス中で処理することにより、レジスト表面をシ
リル化(Si含有ガスが拡散してベースポリマーと結合
すること)して、レジストの耐ドライエツチング性を向
上させるものである。(Means and effects for solving the problems) The present invention involves applying a photoresist onto a semiconductor substrate, exposing it to light for pattern formation, and developing it. After forming a resist pattern, the entire surface is exposed to light. This method of manufacturing a semiconductor device is characterized in that the resist is exposed to a gas containing Si and then dry etched. That is, in the present invention, after fully exposing a resist pattern obtained by resist coating, exposure, and development, the resist surface is silylated (the Si-containing gas diffuses and forms a base polymer) by treating it in a Si-containing gas. (combining with the resist) to improve the dry etching resistance of the resist.
(実施例)
以下第1図を参照して本発明の一実施例を説明する。ま
ず5iJJ板1の絶縁膜上にAJL(A、!合金でも可
)層2を1.0μm厚に、形成し、その上にポジ型フォ
トレジスト[例えばNPR−820(長瀬産業(株)製
)]3を1.4μmの厚さに塗布し、(第1図(a))
露光及び現像を行ない、所定のレジストパターンを得る
(第1図(b))。(Example) An example of the present invention will be described below with reference to FIG. First, on the insulating film of the 5iJJ board 1, an AJL (A, ! alloy) layer 2 is formed to a thickness of 1.0 μm, and a positive photoresist [for example, NPR-820 (manufactured by Nagase Sangyo Co., Ltd.)] is applied thereon. ] 3 to a thickness of 1.4 μm (Figure 1 (a))
Exposure and development are performed to obtain a predetermined resist pattern (FIG. 1(b)).
更に、3011J/(J[のエネルギー量で全面露光4
を施こした後、Siを含有するガス中例えばHMSD
(ヘキサメチレンジシラザン)雰囲気中で80℃、5分
のベーキング処理を行なってレジスト3の表面部にシリ
ル化された部分3−aを形成しく第1図((1) )
、更に適宜に120℃、4分のボストベークを行なった
後にドライエツチングを行なう(第1図(e))。この
ようにドライエツチングを行なったところ、選択比が従
来のボストベークだけの場合の2.46に対し、上記処
理を行なったものは選択比3.12と良好な結果を得た
。Furthermore, full-surface exposure 4 with an energy amount of 3011J/(J[
For example, HMSD in a gas containing Si.
(Hexamethylene disilazane) Baking treatment was performed at 80° C. for 5 minutes in an atmosphere to form a silylated portion 3-a on the surface of the resist 3 (Fig. 1 (1)).
Then, after suitably post-baking at 120° C. for 4 minutes, dry etching is performed (FIG. 1(e)). When dry etching was carried out in this manner, the selectivity ratio was 2.46 in the case of only the conventional post bake, whereas the selectivity ratio was 3.12 in the case of the above-mentioned process, which was a good result.
上記処理として、上記レジスト3を、Siを含有するガ
ス中にさらすだけでもよいが、その際80℃〜150℃
の雰囲気中で行なうのが好ましい。それは80℃以下で
は効果が薄いのと、150℃以上ではレジストパターン
が変形してしまうためである。As the above-mentioned treatment, the resist 3 may be simply exposed to a gas containing Si;
It is preferable to carry out the process in an atmosphere of This is because the effect is weak at temperatures below 80°C, and the resist pattern is deformed at temperatures above 150°C.
[発明の効果]
本発明によれば、簡、単な処理により、レジストの耐ド
ライエツチング性を向上させることができ、加工精度、
スルーブツトが向上する効果がある。[Effects of the Invention] According to the present invention, the dry etching resistance of the resist can be improved through simple processing, and the processing accuracy and
It has the effect of improving throughput.
第1図は本発明の一実施例の工程図である。
1・・・半導体基板、2・・・被加工材料、3・・・レ
ジスト、3−a・・・シリル化された部分、4・・・全
面露光の光。FIG. 1 is a process diagram of an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...Semiconductor substrate, 2...Work material, 3...Resist, 3-a...Silylated portion, 4...Light for whole surface exposure.
Claims (4)
パターン形成のための露光及び現像を行ない、レジスト
パターンを形成した後、全面露光を行ない、更にSiを
含有するガス中に上記レジストをさらした後、ドライエ
ッチングを行なうことを特徴とする半導体装置の製造方
法。(1) A photoresist is applied onto a semiconductor substrate, exposed and developed to form a pattern, and after a resist pattern is formed, the entire surface is exposed, and the resist is further exposed to gas containing Si. 1. A method for manufacturing a semiconductor device, which comprises performing dry etching after dry etching.
メチレンジシラザン)を使用することを特徴とする特許
請求の範囲第1項に記載の半導体装置の製造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein HMDS (hexamethylene disilazane) is used as the Si-containing gas.
50℃の熱処理を行なうことを特徴とする特許請求の範
囲第1項に記載の半導体装置の製造方法。(3) When exposed to the above Si-containing gas, 80°C to 1
The method for manufacturing a semiconductor device according to claim 1, characterized in that heat treatment is performed at 50°C.
としてその材料がAlまたはAl合金膜であることを特
徴とする特許請求の範囲第1項に記載の半導体装置の製
造方法。(4) The method for manufacturing a semiconductor device according to claim 1, wherein the material to be processed by the dry etching is an Al or Al alloy film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29681187A JPH01137634A (en) | 1987-11-25 | 1987-11-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP29681187A JPH01137634A (en) | 1987-11-25 | 1987-11-25 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01137634A true JPH01137634A (en) | 1989-05-30 |
Family
ID=17838451
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29681187A Pending JPH01137634A (en) | 1987-11-25 | 1987-11-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01137634A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1041445A3 (en) * | 1999-03-31 | 2001-01-17 | Infineon Technologies North America Corp. | Method of improving the etch resistance of photoresists |
DE10101734A1 (en) * | 2001-01-16 | 2002-07-25 | Osram Opto Semiconductors Gmbh | Process for forming an etching mask |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61218133A (en) * | 1985-03-19 | 1986-09-27 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Pattern formation of semiconductor device |
-
1987
- 1987-11-25 JP JP29681187A patent/JPH01137634A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61218133A (en) * | 1985-03-19 | 1986-09-27 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | Pattern formation of semiconductor device |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1041445A3 (en) * | 1999-03-31 | 2001-01-17 | Infineon Technologies North America Corp. | Method of improving the etch resistance of photoresists |
US6379869B1 (en) | 1999-03-31 | 2002-04-30 | Infineon Technologies Ag | Method of improving the etch resistance of chemically amplified photoresists by introducing silicon after patterning |
DE10101734A1 (en) * | 2001-01-16 | 2002-07-25 | Osram Opto Semiconductors Gmbh | Process for forming an etching mask |
DE10101734C2 (en) * | 2001-01-16 | 2003-04-24 | Osram Opto Semiconductors Gmbh | Method for forming an etching mask on a substrate |
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