JPH01134645A - Timing generating circuit - Google Patents

Abstract

PURPOSE:To obtain a margin for a trouble in a ROM to be divided by an address signal by writing the same bit pattern, to which a parity bit is added, to the respective address areas of the ROM. CONSTITUTION:A ROM 6 is divided into two address areas 61 and 62, and the same bit pattern, to which the parity bit is added, is stored in these areas 61 and 62. When a seizing signal is inputted from an external part through a signal line 12, data on the ROM 6 are successively read from start addresses set by the seizing signal. The data and the parity bits of the read respective addresses are checked at a parity checking circuit 7. Here, even though the trouble occurs in the ROM 6, and a parity error occurs in one address area, a normal timing signal can be generated using the other address area by changing the value of an address signal from an address selecting circuit 1. Namely, the title device can be operated without exchanging the troubled ROM 6.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a timing generation circuit that reads all contents of a read-only memory and generates all timing signals, and particularly relates to its operation when a failure occurs in the read-only memory.

(Prior Art) In information processing devices, the integration of logic circuits has become remarkable, and even in main storage devices, storage control units are increasingly being integrated into LSIs. However, in order to operate a memory element such as a dynamic MOS memory element, the RA
Timing signals such as the J row address strobe signal are required, but the timing signal generation circuit that generates these timing signals is one of the circuits that is difficult to incorporate into an LSI.

Therefore, as one of the countermeasures, a method of fully utilizing the read-only memory is known.

The method used for the read-only memo IJ' is to write all the necessary bit patterns in the read-only memory in advance, read out all the bit patterns during the operation cycle of the main memory, and then generate all the timing signals in the evening. It is.

(9) By writing the timing signal bit pattern with seven parity bits, when the other bit pattern is read out, all parity checks are performed to confirm normality.

(Problems to be Solved by the Invention) In the above-mentioned conventional timing generation circuit that generates timing signals using a read-only memory, if a parity error is detected in Fi, read data, a fatal failure will occur. There is a drawback. For example, even if only one bit of a read-only memory fails, the package in which the read-only memory is installed must be replaced. Equipped with an address selection circuit that selects the address area of the dedicated memory and the read-only memory.

The same bit pattern (kv) with a parity bit (k) added is stored in each address area of the bladder-removal-only memory divided by the address signal from the address selection circuit, so that the same timing signal can be generated no matter which address area is accessed. Due to the above disadvantages? An object of the present invention is to provide an entire timing generation circuit configured to have a margin t against a failure of a read-only memory.

(Elaborate Means to Solve All Problems) The timing generation circuit according to the present invention is elaborately constructed and includes an operation designation register, a counter, a read-only memory, an address selection circuit, and a parity check circuit. .

The operation designation register is a well-organized register that stores and holds all the operation designation signals in response to the activation signal supplied from the outside.

The counter is for manually counting the clock from the outside.

The address selection circuit divides the entire address area into the pair of first and second address areas based on the address division signal and selects one of them.

The parity check circuit is a hole-type circuit that performs a parity check on read data from the read-only memory.

The read-only memory is for storing data that generates the same timing signal at each address consisting of a pair of first and second address areas, and is for storing data for generating the same timing signal, and also for storing data for generating the same timing signal at each address consisting of a pair of first and second address areas. It is possible to generate a timing signal by inputting the output sound address information and reading the data sequentially from the start address specified by the address information according to the count value of the counter, which is further divided by the address division signal from the address selection circuit. If a parity check circuit detects a parity error, the setting value of the address selection circuit is changed. The present invention is modified so that the second address area can be used in place of the first address area to generate all the timing signals.

('i!! flowing side) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of a timing generation circuit according to the present invention. In Figure 1, 1 is an address selection circuit, 2 is an operation designation register, 3 is a counter,
4.5 is an AND gate, 6 is a read-only memory, and 7 is a parity check circuit.

Here, the address signal (ALL) sent from the address selection circuit 1 onto the signal line 14 is ``1''.

Assuming that the signal is a binary signal of O'', the read-only memory 6 is divided into two address areas 61 and 62 as shown in FIG. - Memorize the bit pattern.

When an activation signal is input from the outside through the signal line 12t-, the operation designation register 2 stores the operation designation signal on the signal line 11 and holds it until the next activation signal is input. All bits of the counter 3 are cleared by the activation signal on the signal line 12. In this state, the read start address of the read-only memory 6 is determined, and the bit pattern and parity bit of each bit are output from the read-only memory 6. A parity check circuit 7 performs an error check on these read data.

Among the data read from the start address, a bit pattern is generated so that the reset signal becomes a logic 11'', so from then on, the counter 3 outputs a signal until the reset signal on the signal line 18 becomes a logic 10''. Count the clocks on line 13.

As a result, the data on the m-output dedicated memory 6 is sequentially read from the 9th start address, which is set by the start signal on the ir line 12, and a predetermined timing signal is generated. A pit is checked by a parity check circuit 7.

here,! If a failure occurs in the read-only memory 6 and a parity error is detected, an incorrect timing signal is generally generated on the signal line 6, and the operation of the device is not guaranteed. However, the address area of the memory 6 exclusively for bladder removal is divided into two by the nine address signals sent from the address selection circuit 1 onto the signal line 14, and the address area 61 of the memory 6 is divided into two.
．． The same data is stored in 62.

Even if the aforementioned parity error occurs in the 10,000 address area, by changing all the values of the 7 address signals from address selection circuit 1, normal timing compensation can be achieved using the other address area. It can cause a lot of excitement.

Namely.

It is possible to operate the failed read-only memory 6 without replacing it.

(Effects of the Invention) As explained above, the present invention includes a read-only memory having a plurality of addresses and an address selection circuit that moves the address area of the read-only memory closer or closer, and divides the address area according to an address signal from the address selection circuit. By writing all the same bit patterns, including parity bits, into the valley address area of the read-only memory that is to be accessed, the same timing signal can be generated no matter which address area is accessed, thereby reducing the output from the address selection circuit. This has the effect that a correct timing signal can be generated by changing the value of the address signal.

Therefore, there is an effect that the troublesome sound can be recovered without replacing the read-only memory itself or the package in which the read-only memory is mounted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a timing generation circuit according to the present invention. FIG. 2 is an explanatory diagram showing division between addresses 9 of the read-only memory in FIG. 1. 1...Address selection circuit 2...Operation specification register 3...Counter 4.5
...AND gate 6...Read-only memory 7...Parity check circuit 61', 62...Address area Patent applicant NEC Corporation

Claims (1)

[Claims] an operation designation register for storing and holding an operation designation signal in response to a start signal supplied from the outside; a counter for counting by inputting a clock from the outside;
and a read-only memory for storing data for generating the same timing signal at each address consisting of a second address area, and an address division signal that divides the entire address area into the pair of first and second address areas. and an address selection circuit for selecting one of them, and a parity check circuit for performing a parity check on the read data of the read-only memory,
The read-only memory inputs the outputs of the operation designation register, the counter, and the address selection circuit as address information, and sequentially reads data according to the count value of the counter from the start address specified by the address information. is generated by adding a parity bit to the first and second address areas divided by the address division signal from the address selection circuit. The same pair of bit patterns are written, and when an error is detected in the parity check circuit, the set value of the address selection circuit is changed to use the second address area instead of the first address area. 1. A timing generation circuit characterized in that the timing generation circuit is configured to be able to generate a timing signal using a timing signal.