JPH01133408A - Digital filter - Google Patents

Abstract

PURPOSE:To simplify the hardware of a digital filter and to make the filter be capable of multi-processing by adding outputs of a main and auxiliary digital filters to each other and using the sum as the output of the digital filter. CONSTITUTION:The digital filter of this invention is constituted of a main digital filter 6 and auxiliary digital filter 11. In this constitution, the output M of a multistage digital SIGMA modulator 1 is integrated in the integrating stage (adder 7 and delayer 8) of the main digital filter 6 and differentiated in the differentiating stage (delayer 9 and subtractor 10). The output of the differentiating stage is supplied to one input of an adder 14. On the other hand, the output S of the modulator 1 is supplied to the other input of the adder 14 after it is processed at the auxiliary digital filter 11, namely, in a differentiating state (delayer 12 and subtractor 13). At the adder 14, the outputs of the filters 6 and 11 are added to each other and outputted as a digital output (y).

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital filter comprising a multi-stage delta-sigma modulator and a digital filter section connected thereto.

(Prior art) Conventionally, as this type of device, rVLST-A to D
andD Lo A converters
with Multi-5tage NoiseS
Haping Modulators J I (:AS
SP 86. YO to To.

IEEE, 1986, p. 1545-1548.

Below, according to Figure 2, the conventional digital filter
voice'. , し'ZJLt7#)li'). 6th crystal.

This digital filter is roughly divided into a multistage delta-sigma modulator 1' and a digital filter section 2'. The multi-stage delta-sigma modulator 1° includes a main ΔΣ modulator 3 consisting of a first integrator and a first quantizer, and a sub-ΔΣ modulator 4.1 consisting of a second integrator and a second quantizer. sample delay device 5,
It is composed of an adder 20 and a differentiator 21. Differentiator 21
consists of a one sample delayer 22 and a subtracter 23. The output X of the multistage delta-sigma modulator 1' is the result of delaying the output of the main ΔΣ modulator output 3 via the 1-sample delay device 5, and the result of differentiating the output of the sub-ΔΣ modulator 4 with the differentiator 21. It is shown as the sum of Here, one sample delay time is assumed to be one cycle operating time of the multistage delta-sigma modulator 1'.

On the other hand, the digital filter section 2° includes an integrating stage consisting of an adder 24 and a 1-sample delayer 25, and an n-sample delayer 26.
The configuration is such that a differential stage consisting of a subtracter 27 and a subtracter 27 are connected in series. The transfer function of an IIR digital filter is expressed as, for example, as described in "Applications of Digital Signal Processing," edited by the Institute of Electronics and Communication Engineers, May 20, 1980, p. 42-44. Filter part 2
” corresponds to the part where M=n and N=1 in equation (1), and its transfer function is the following equation (2) and a modified version of equation (2).
It is expressed by equation (3).

H(z) = (1÷z−”+z″″2nd order −・ ◆
z-(n-11) axis - (3) In the above equation, z -j represents the delay of one sample of the sampled digital data, and equation (3) represents n types from 0 to (n-1) samples. It is the sum of data with a delay of . For example -1/
If n, the digital filter output y is the average value of the n multistage delta sigma modulator outputs X, and the digital filter section 2' has a low-pass filter characteristic and attenuates the high frequency noise of the multistage delta sigma modulator 1°. Has a function. Further, the digital filter output y can be used as a filter when data is extracted at a long period of every n samples. When used as a decimation filter, the storage operation of the n-sample delay unit 26 and the subtraction operation of the subtractor 27 in the differential stage may be performed at a low rate of once every n samples.

Next, the operation speed and amount of hardware for storage and calculation of the multi-stage delta-sigma modulator 1° and the digital filter section 2' in the conventional digital filter will be explained.

The outputs of the main ΔΣ modulator 3 and the sub ΔΣ modulator 4 are each 1
Each time the output is calculated, the range of possible values increases. Output X is delay device 5 output, sub ΔΣ modulator 4
The output is the sum of three values of the polarity-inverted values of the output of the delay device 22. If each output is set to ±1, the value of the output X is within ±3 and is expressed in two's complement with three bits.

Considering the hardware for parallel calculation in the integrating stage of the digital filter section 2', in order to add n samples of the output 26 and the subtractor 27 also require the same bit width as the maximum value to be integrated.゛The operating speed of storage operations is considered as a thinning filter: the delay units 5, 22, 25, the adders 20, 24, and the subtracter 23! Every sample, the delayer 26 and the subtractor 27 are every n samples.

When realizing the function of the digital filter section '2', even if the input This is achieved by operating at the right timing. That is, if the X input is true, it counts at the rising edge of CLM1, and if it is false, it does not count, and the cumulative result is obtained at the output y every n samples, and then CLKn is set to `` and counting starts again. Problems to be Solved by the Invention However, the conventional digital filters have the following problems.

The output X of the multi-stage delta-sigma modulator 1' is 3 bits, and considering the parallel processing, the hardware of the calculation and storage elements of the digital filter section 2° is the maximum of the adder 24, subtracter 27, and delay device 25. The number of bits corresponding to the width of the output value is required, which requires a significant increase in the amount of hardware compared to hardware using a simple counter.

Furthermore, if the sampling period of 1° of the multi-stage delta-sigma modulator is very short, it may be impossible to multiplex the processing of the digital filter section 2' using a digital signal processor, etc. There were also drawbacks, such as the need to prepare clothing.

The present invention has been made to solve the problems of the prior art, and can reduce the amount of hardware, and is suitable for cases where the order of the digital filter section is high or the number of stages of the multi-stage delta-sigma modulator is large. It is an object of the present invention to provide a digital filter that can be suitably applied to the present invention.

(Means for Solving the Problems) In order to solve the problems of the prior art, the digital filter of the present invention provides a main delta-sigma filter that inputs an analog signal and outputs a 1-bit digital signal and an integrator output. A modulator, a delay device that delays a 1-bit digital signal outputted by the main delta-sigma modulator by one sample, and an integrator output from the main delta-sigma modulator is inputted to output a 1-bit digital signal. a multi-stage delta-sigma modulator consisting of at least one stage of secondary delta-sigma modulator; a digital filter; a sub-digital filter having a configuration in which the 1-bit digital signal output from the sub-delta-sigma modulator is input, and the integration stage is one step smaller than the configuration of the main digital filter; and an output of the main digital filter; and a digital filter section comprising an adder for adding the output of the sub digital filter.

(Function) In the present invention, the delay device delays the 1-bit digital signal outputted from the main delta modulator of the multistage delta-sigma modulator by one sample, and the output is sent to the integrating stage of the main digital filter of the digital filter section. Since it is used as an input to the differential stage, the integral stage and the differential stage can be realized with simple counters. Further, since the digital signal output from the sub-delta-sigma modulator of the multi-stage delta-sigma modulator is input to the sub-digital filter of the digital filter section, the sub-digital filter can be realized with a small number of bits. Then, an adder adds the outputs of the main digital filter and the sub digital filter to form the digital output of the digital filter, which simplifies the overall hardware and makes it possible to use multiple processing using a digital processor. Become. Therefore, the problems of the prior art mentioned above are solved.

(Example) Examples of the present invention will be described in detail below.

FIG. 1 is a configuration diagram of the digital filter of this embodiment,
In this figure, the same elements as in FIG. 2 are given the same reference numerals. This digital filter is broadly divided into a multistage delta-sigma modulator 1 and a digital filter section 2. Multi-stage delta-sigma modulator 1 includes main ΔΣ modulator 3 and sub-ΔΣ
It consists of a modulator 4 and a one sample delay device 5. The main ΔΣ modulator 3 output is the output M via the 1 sample delay device 5, and the sub ΔΣ
The four outputs S of the Σ modulator are the outputs of one multistage delta sigma modulator, and each of these outputs is 1 bit wide.

-, the digital filter section 2 is the main digital filter 6
, a sub digital filter 11 and an adder 14. The main digital filter 6 is composed of an integrating stage consisting of an adder 7 and a one-sample delayer 8, and a differentiating stage consisting of an n-sample delayer 9 and a subtracter 10. The sub-digital filter 11 is composed of a differentiation stage consisting of an n-sample delayer 12 and a subtracter 13. The operation speed of each operation is determined by the adder 7.
The delay device 8 operates at low speed every sample, and the subtracters 10 and 13, the adder 14 and the delay devices 9 and 12 operate at low speed every n samples.

In this embodiment, the output M of the multistage delta-sigma modulator 1 is transferred to the integrating stage (adder 7 and delayer 8) of the main digital filter 6.
, and then differentiated at a differentiation stage (delay unit 9 and subtractor 10 ), and the output thereof is supplied to one input of an adder 14 . On the other hand, the output S of the multi-stage delta-sigma modulator 1 is generated by a sub-digital filter 11, that is, a differentiating stage (delay unit 12 and subtracter 13) and then supplied to the other input of the adder 14. Then, in the adder 14, the outputs of the main digital filter 6 and the sub digital filter 11 are added to form the main power y.

Considering the hardware implementation according to this embodiment, since the output M is 1 bit, the adder 7, subtracter 10, and delay device 8゜9 of the integration stage and differentiation stage of the main digital filter 6 connected to the output M are 1 bit. , can be realized by the counter shown in FIG.

Further, since the output S of the subtracter 13 and delay device 12 of the sub digital filter 11 connected to the output S is 1 bit, for example, the above-mentioned document "Applications of Digital Signal Processing jp, 78-79
This can be realized using a 1-bit full subtracter circuit and a flip-flop circuit described in .

Furthermore, since the means for realizing the subtracter 13, delay device 12, and adder 14 operate at a low speed of every n samples, it is possible to adopt a separate multiprocessing method using a digital signal processor. It is also possible to share if a digital signal processor is provided for processing.

Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications and changes are possible. For example, even in the case of a high order digital filter unit having a plurality of integration stages and a plurality of differentiation stages, it can be similarly implemented using hardware with a 1-bit input.

Also, even when the multi-stage delta-sigma modulator has two or more stages, by providing a digital filter section corresponding to the 1-bit output of each stage, the modulator output of each stage can be converted to low-speed data using simple hardware. can be converted into , and can be realized by the multiprocessing method described above.

When the number of integration stages and the number of differentiation stages of the digital filter section are each 2, that is, a hardware implementation example of a second-order decimation filter is rA Single-Channel PCM.
Codec J IEEE TRANSACTION
ON COMMUNICATIONSVol, C0M
-27, No, 2. February 1979, 9.283-29
5. Fig, 6 and Fig of the same document,
7 shows an example of the hardware architecture and operation flowchart of a digital filter whose transfer function is represented by .

The hardware architecture takes as input the 1-bit output signal of a delta-sigma modulator. The present invention is suitably applicable to such cases as well.

As described above, it is clear that the present invention can be applied to cases where the order of the digital filter section is high or to digital filters including multi-stage delta-sigma modulators having many stages.

(Effects of the Invention) As described above in detail, according to the present invention, the 1-bit digital signal output from the main delta-sigma modulator is delayed by 1 bit and input to the main digital filter of the digital filter section. , the 1-bit digital signal output from the sub-delta-sigma modulator is input to the sub-digital filter of the digital filter section, and the outputs of the main and sub-digital filters are added together to obtain the output of the digital filter, so the hardware This has the advantage that it can be simplified and realized by a multiprocessing method.

Further, the present invention can also be applied to cases where the digital filter section has a high order or where the multistage delta-sigma modulator has many stages.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a digital filter according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional digital filter, FIG. 3 is an explanatory diagram of a counter, and FIG. 4 is an operation time chart of the counter. 1...Multi-stage delta-sigma modulator 2...Digital filter unit 3...Main ΔΣ modulator 4...Sub-ΔΣ modulator 5.8, 9.12...Delay unit 6...Main digital Filter 7.14...Adder 10.13...Subtractor 11...Sub digital filter

Claims (2)

[Claims] (1) A main delta-sigma modulator that inputs an analog signal and outputs a 1-bit digital signal and an integrator output, and a delay device that delays the 1-bit digital signal output from the main delta-sigma modulator by one sample. and at least one sub-delta-sigma modulator that inputs the integrator output from the main delta-sigma modulator and outputs a 1-bit digital signal; and the delay device outputs: A main digital filter having a 1-bit digital signal as an input, a main digital filter consisting of at least one integrating stage and at least one differentiating stage, and a 1-bit digital signal output from the sub-delta-sigma modulator; It is characterized by being comprised of a digital filter section consisting of a sub digital filter having one integration stage less than the filter structure, and an adder that adds the output of the main digital filter and the output of the sub digital filter. digital filter. (2) the sub-delta-sigma modulator is configured with multiple stages;
2. The digital filter according to claim 1, wherein an independent sub-digital filter is provided corresponding to each sub-delta-sigma modulator.