JPH01133291A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent an erroneous erasing in an already written memory cell at the time of writing by making the control gates of all the memory cell at the source side of a selected memory cell at the time of writing an L level. CONSTITUTION:Together with an output node, a writing control signal W' is inputted to a NOR gate G2 of a decoder D1, and together with the output of a gate 2, an erasing control signal E is inputted to an NOR gate G3. Thereafter, an output node N1 of the decoder D1 is inputted to the NOR gate G2 of a decoder D2 as a writing control signal, and in the same manner, the following each output node of following each decoder is inputted to a next NOR gate of a next decoder successively as the writing control signal. In this decoder circuit, an H level is supplied to control gates CG1-CG4 of cells M1-M4 at the drain side of a selected cell M5, and the L level is supplied to the cell M5 and control gates CG5-CG8 of cells M6-M8 at the source side of the cell M5. Thereafter, when the H level is given to a bit line BL, the writing of 1 datum is executed in the cells M1-M4. On the other hand, data are never destroyed in the cells M6-M8 since an electric field never spans the control gate and a substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device using a rewritable memory cell having a floating gate and a control gate.

(Prior art) In the field of EPROM, 1. MO3FET with floating gate
Ultraviolet erasable nonvolatile memory devices using memory cells of this structure are widely known. Among EFROMs, those that can be electrically erased are known as E2''PROMs.The memory array of this type of EFROM is constructed by arranging memory cells at each intersection of row lines and column lines that intersect with each other. .

In the actual pattern, the drains of the two memory cells are made common and the column lines are brought into contact with the drains to minimize the area occupied by the cells. -However, this still requires a contact portion with the column line for each common drain of two memory cells, and this contact portion occupies a large portion of the cell occupied area.

On the other hand, recently, memory cells are connected in series and NAND
An EPROM has been proposed that allows cells to be configured and the number of contact portions to be significantly reduced. However, when using this new type of memory cell structure in an EPROM, no consideration has been given to the peripheral circuitry for controlling the memory cells.

(Problems to be solved by the invention) As mentioned above, recently proposed EF using NAND cells
Regarding ROM, a peripheral circuit system for controlling it has not yet been considered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device that realizes an optimal peripheral circuit system for controlling a NAND cell when it is used.

[Structure of the Invention (Means for Solving Problems)] The EFROM according to the present invention has a plurality of memory cells each having a floating gate and a control gate connected in series to form a NAND cell. In principle, both writing and erasing utilize the exchange of electrons between the substrate and the floating gate due to the tunnel effect. In a specific write operation, the control gate of a selected memory cell constituting a NAND cell is set to an "L" level potential, and all memory cells on the drain side of the selected memory cell are set to a "H" level potential at their control gates. Apply a level potential to turn it on,
Apply "H" level potential to the bit line. At this time, all of the memory cells on the source side of the selected memory cell are given an "L" level to their control gates.
A decoder is configured. As a result, in the selected memory cell, electrons are emitted from the floating gate to the substrate, and the threshold value shifts in the negative direction. In the erase operation, an "H" level potential is applied to the control gates of all memory cells constituting the NAND cell, the channel is set to an "L" level potential, and electrons from the channel region of all memory cells are transferred to the floating gate by tunneling effect. As a result, the threshold voltages of all memory cells are shifted in the positive direction, resulting in a "0" state.

In the present invention, in the EFROM having such an operating principle, during writing, "L2" is applied to the control gates of all memory cells on the source side of unselected memory cells.
The present invention is characterized in that the decoder circuit is configured to provide a level.

(Function) In the present invention, writing and erasing are performed by tunneling between the floating gate and the substrate, which provides an oxide film with excellent film quality. Therefore, the reliability of the EFROM becomes high. In write mode -1 If the control gate of a memory cell on the source side of a selected memory cell for which a write operation has already been completed is given an "H" level potential, electrons will be injected from the substrate to the floating gate in this memory cell. , data will be destroyed.In other words, the memory cell whose threshold value has moved in the negative direction due to "11 writing" will have its threshold value shifted again in the positive direction due to electron injection into the floating gate, and the data will be destroyed. ”. In the present invention, such erroneous erasing can be prevented by setting the control gates of all memory cells on the source side of the selected memory cell to "L" level using the decoder circuit during writing.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a word line decoder circuit section of an E2 PROM NAND cell array according to an embodiment, FIGS. 2 and 3 show a more detailed configuration of the memory array according to the embodiment, and FIG. 4 shows its selection. FIG. 3 is a signal waveform diagram illustrating a write operation.

As shown in FIG. 4, in this embodiment, eight memory cells constitute one NAND cell, which are arranged in a matrix. FIG. 3(a) is a cross-sectional view of one NAND cell taken in the channel direction. Each memory cell is p
On a type Si substrate 1, an n-type layer 2 serving as a source and a drain is shared between adjacent ones, and a floating gate 3 and a control gate 4 are stacked in a self-aligned FAMO3 structure using a two-layer polycrystalline silicon film. It is configured. That is, the floating gate 3 is formed on the substrate 1 via a first gate insulating film made of a thermal oxide film, and the control gate 4 is formed thereon via a second gate insulating film made of a thermal oxide film. Figure 3 (b
) is a cross-sectional view of the memory cell section viewed in a direction perpendicular to the channel direction, in which the floating gate 3 extends even onto the element isolation region. As a result, the coupling capacitance between the floating gate 3 and the control gate 4 is set larger than the coupling capacitance between the floating gate 3 and the substrate 1, and writing is performed only by exchanging electrons due to the tunnel effect between the floating gate 3 and the substrate 1. It is now possible to erase.

The NAND cells are arranged in a matrix as shown in FIG. Looking at one NAND cell along the bit line BL1, the drain of the memory cell M at one end of the NAND cell is connected to the bit line BL via the selection MOS transistor S1.
The source of the memory cell M14 at the other end is connected to the ground potential via the selection MOS transistor S2. The same applies to other bit lines. Control lines CG1 . CG2. ...is the word line WLI+
They are arranged as W L 2 , .

A decoder circuit section for selecting a word line is configured as shown in FIG. The decoder Dl-D8 selects one of the 8-bit memory cells making up the NAND cell, and basically each has an address a1. a2. “0” of a3,
It is composed of a NAND gate G1 and an inverter 11, one of which outputs "l" depending on the combination of "1".

Output node of inverter 11 of each decoder N 01°N
02. . . , N08 includes a NO'R gate G2 . G is provided. The NOR gate G2 of the decoder D1 has an output node NOI
At the same time, the write control signal W' is inputted, and the erase control signal E is inputted to the NOR gate G3 together with the output of the NOR gate G2. Then, the output node N1 of this decoder D1 is sent to the NOR gate G2 of the next decoder D2, and then to the NOR gate G2 of the next decoder D2.
The output node N2 of the second decoder D3 sequentially enters the NOR gate G2 of the next decoder D3 as a write control signal. Erasing control signal E is sent to each decoder D2. NOR of D,...
Enter Gate G3. And each decoder Dl, D2 .・・・
The output of
, . . . are supplied to the control gates of .

FIG. 4 shows how memory cell M5 is processed by such a decoder circuit.
The figure shows operation waveforms when performing write control. That is, as shown in FIG. 4, the address al.

Let's look at the case where the write control signal 77 becomes "L level" when G2 is "H" level and address a3 is 'Lm level. Before the write control signal W7 becomes "L" level, the erase control signal E is set to "L" level in advance. ” level. First, decoder D,
is not selected because the address a3 is at the "L" level, and outputs the output node N1t::"L" level. As a result, the "H# level" is supplied to the control gate of the memory cell M1.The potential of this node N1 and its own addresses al, a2.a3 are input to the decoder D2, and in this case, "al" is "L". Since it is at the level, it is not selected, and the "L" level is output to the output node N2. Therefore, the "H" level is also applied to the control gate of memory cell M2. Similarly, decoder D2. D3. ...
inputs the decoder output from the previous stage and its own address, and outputs "L" level up to the selected address.

In this embodiment, the addresses al, a2 of the decoder D5
．． a3 all become "H# level" and enter the selected state.At this time, output node NO5 becomes "L" level, and output node N4 of the previous stage decoder D4 is "L" level, so output node N5 becomes "H2 level". become. As a result,
"L" level is supplied to the control gate of memory cell M5.

Next, the decoder D6 becomes non-selected, but the output node N8 becomes an "H" level because it enters the NOR gate G2 as the "H" level output write control signal of the previous output note N5.Hereinafter, the decoder D7. DB output node N7
．． The same applies to N8.

In this way, as shown in FIG. 4, the memory cells M1 to M on the drain side of the selected memory cell M5 are
4 control gates CG1 to CG4 are set to "H", and control gates CG5 to CG8 of selected memory cell M5 and all memory cells M6 to M8 on the source side thereof are set to "L".
Level is supplied. Then, when the bit line BL is given the "H° level," the channels of all memory cells M1 to M4 on the drain side of the selected memory cell M5 become conductive, and as a result of a large electric field being applied to the channel and control electrode surface, floating Electrons from the gate are emitted to the substrate by the tunnel effect, and "1" data is written.In the memory cells M6 to M8 on the source side of the selected memory cell M5, an electric field is applied between the control gate and the substrate. Therefore, previously written data will not be destroyed.

In the decoder circuit of FIG. 1, the erase control signal E is set to “H”.
” level, the output nodes N1 to N of each decoder
8 are all at "L# level," therefore, all control gates of memory cells M1 to M8 are given H level. When the bit line is brought to the "L2 level" in this state, electrons are injected from the substrate to the floating gates of all the memory cells M1 to M8 constituting the NAND cell, and the entire surface is erased.

FIG. 5 shows the configuration of a decoder circuit section of another embodiment.

In this embodiment, the reference addresses VQ to V3 are compared with the input addresses a1 to a3, and based on the result, the control gate of the memory cell on the drain side of the selected memory cell is set to "H" level, and the remaining memory cells are It is designed to give "L rubel" to the control gate. Consider the case where subtraction is performed to compare the input addresses a1 to a3 and the reference address V □ -V 3. Subtraction of binary numbers is performed by adding It is well known that this is carried out by adding the "two's complement" of subtracted numbers. Therefore, the addresses v1 to v3 of the decoder circuit are configured to be "two's complement numbers" as shown in FIG. 6, and these are added to the input addresses a1 to a3. However, here, only the magnitude relationship between the address of the decoder circuit and the input address is required, and the calculation result itself is not required. Therefore, attention is paid to the carry generation section of the adder circuit, and the least significant bit a1 of the input address and the least significant bit v3 of the decoder address are input to the carry generation section of the half adder. Its output and the next position a2 of the input address
Then, the next digit v2 of the decoder contention address is input to the carry generation section of the full adder.

Thereafter, the levels of the control gates CG0 to CG8 are similarly determined using the carry generation section of the full adder.

As in the previous embodiment, consider the case of writing to memory cell M5. At this time, the input address is al-“H”,
G2- “H” s a 3 ■ “L”. This is regarded as a 3-digit binary number 001, and is added to the decoder address determined by v1 to v3. As a result, CG1-
CG4 is supplied with an "H" level, and CG5 to CG8 are supplied with an "L" level. Note that V□ is used to detect whether the carry of the result of calculation up to the highest level is positive or negative.

FIG. 7 shows the configuration of a decoder circuit section of still another embodiment. The input address is (al.

G2. G3) ” (0,O,On), (0,0゜1), (0,1,0), (0,1,1), (1゜0.0
), (1,0,1) 1. (1,1,0), (1,1,
1) are possible, and a gate circuit is configured to determine in advance how far from CG1 to CG should be set to the "H0 level" for each of them. W is a write control signal, and E is a write control signal. is an erase control signal, and during writing, W-
H", E-"L". At this time, (al, G
2, G3) - (0,0,O) then CG1~C
G7-“H”, CG3-“L”, memory cell M
8 is selected. When (0, 0, 1), CG, -CG
, -“H”, CG7*CGB-“L”, and memory cell M7 is selected. When (0, 1, 0), CGI ~ CG5 - “H” s C06
~CGB - "L2," and memory cell M6 is selected. When it is (0, 1° 1), CG, ~CG4 - "H"
, CG5 to CG3-“L”, and memory cell M5 is selected. When (1, O, O), CG1 to CG3-H
", CG4 to CG3 - "L", and memory cell M4 is selected. When (1, 0, 1), CGI to CG2
- "H", CG4 to CG3 - "L", and memory cell M3 is selected. When (1, 1°0), CG
1-“H”, 062-003m “L”, and memory cell M2 is selected.

When (1, 1, 1), CG1 to CG3 are "L", and memory cell M1 is selected.

This embodiment also prevents erroneous erasure in previously written memory cells.

The present invention is not limited to the above embodiments. For example, in the above embodiment, a case has been described in which eight memory cells are connected in series to form a NAND cell, but the number of memory cells forming the NAND cell is arbitrary. In addition, the present invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, according to the present invention, writing and erasing can be performed using only tunneling between the substrate and the floating gate, and in particular, it is possible to prevent overwriting in memory cells that have already been written during writing. It is possible to provide a high-density EFROM that prevents erasure and improves reliability.

[Brief explanation of the drawing]

FIG. 1 is an equivalent circuit diagram showing the main part configuration of an EFROM according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram showing the configuration of its memory array, and FIGS. 3(a) and 3(b) are its structure. 4 is a signal waveform diagram for explaining the write operation of the EFROM, FIG. 5 is a diagram showing a decoder circuit of another embodiment, and FIG. 6 is a signal waveform diagram for explaining the operation. A diagram showing the relationship, and FIG. 7 is a diagram showing a decoder circuit of still another embodiment. DESCRIPTION OF SYMBOLS 1...Silicon substrate, 2...n small layer, 3...floating gate, 4...control gate, M (M,, Ml,...
・・）・・・Memory cell, BL (BLl, BL2.・
)...Bit line, WL (WL,, WL2.
...)...Word line, CG (CG1.CG2,
...)...Control gate terminal, D(D! r D2
+...)...Decoder. Applicant's agent Patent attorney Takehiko Suzue

Claims (2)

[Claims] (1) Floating gates and control gates are stacked on a semiconductor substrate, and multiple rewritable memory cells are connected in series to perform writing and erasing by exchanging charges using tunnel current between the floating gate and the substrate. A nonvolatile semiconductor memory device comprising NAND cells arranged in a matrix, a drain at one end of each NAND cell connected to a bit line, and a gate of each memory cell connected to a word line. , during write operation, "L" level potential is applied to the control gate of the selected memory cell in the NAND cell, and "H" level potential is applied to the control gates of all memory cells between the drain of the selected memory cell and the bit line. , includes a decoder circuit that applies an “L” level potential to the control gates of all memory cells on the source side of the selected memory cell, and applies an “H” level potential to the drain of the selected memory cell via the bit line. What is claimed is: 1. A nonvolatile semiconductor memory device configured to supply (2) the decoder circuit outputs an "L" level potential to the control gate of the memory cell corresponding to the designated address;
The nonvolatile semiconductor memory according to claim 1, wherein the output is sequentially transmitted to the control gate of the memory cell provided on the source side of the selected memory cell. Device.