JPH01132160A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device having a p-type GaAs layer or a p-type AlxGa1-xAs layer whose reliability is excellent by a method wherein a p<++> GaAs or p<++> InyGa1-yAs layer is arranged on the p-type GaAs or p-type AlxGa1-xAs layer, a non-alloy type metal layer is arranged on the p<++> layer and both are brought into ohmic contact by a tunnel junction. CONSTITUTION:A p<++> GaAs or p<++> InyGa1-yAs layer 70 is arranged on a p-type GaAs or p-type AlxGa1-xAs layer 71; a non-alloy type metal layer 60 is arranged on the p<++> GaAs or p<++> InyGa1-yAs layer 70; both are brought into ohmic contact by a tunnel junction. For example, p<+> GaAs 11 containing Be, undoped (p<->) GaAs 12, undoped AlGaAs 13, n-type AlGaAs 14 containing Si, p-type AlGaAs 15 containing Be, p-type GaAs 16 containing Be and p<++> GaAs 17 containing Be are laminated on a semiinsulating GaAs substrate 10 as shown in the figure; an emitter electrode 50 composed of Ti/Pt/Au is formed on it; in addition, a base electrode 51 and a collector electrode 52 are formed according to ordinary execution; a pnp-type 2 DEG-HBT is completed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device with excellent reliability.

[Conventional technology]

Conventionally, the emitter electrode of a GaAs/AQGaAs Pnp type heterojunction bipolar transistor has 1, for example, Applied Physics Letters, Vol. 46, p. 302 (198
5) (Appl, Phys, Lett, 46.
302 (1985)), A.
Materials such as uZn were used. The main reason for this is that n-channel FETs and bipolar transistors have been mainly n-channel FETs and npn-types, respectively.

[Problem that the invention seeks to solve]

The above conventional technology does not take into consideration the problem of p-type electrodes peculiar to electronic devices such as Pnp-type bipolar transistors, and has the problem that metals such as Zn diffuse extremely deeply into GaAs, deteriorating the p-n junction. there were. In electronic devices, it is desirable that the P-type layer has a thickness of about 200 to 300+ m, and unlike semiconductor lasers, it cannot be made as thick as 2 to 3 t1 m, which deteriorates the p-rL junction.

For example, a Pnp type two-type optical-dimensional electronic gas junction bipolar transistor (described in Japanese Patent Application No. 61-4024, hereinafter referred to as 2DE)
G-HBT), the proper form of the two-dimensional electron gas is essential. That is, it is necessary to have a high mobility of GaAs and to preserve a steep heterojunction.

However, the A u Z n-based electrode conventionally used as an ohmic electrode for p-type GaAs is characterized by forming an ohmic contact using an alloy.
tends to diffuse very deeply in GaAs,
It has been found that the pn junction deteriorates.

This Zn diffusion can reach as much as 1/1111 in some cases.

In particular, deterioration in ohmic characteristics (specific contact resistance ρC) was observed during the formation of the surface protective film CVD5iO and during the formation of the insulating film accompanying the wiring process.

This deterioration phenomenon is due to the diffusion of Zn, and due to the problems of deterioration of pn junction characteristics and deterioration of ohmic characteristics ρC, there was a big problem in terms of reliability when applying such semiconductor devices to integrated circuits. .

Additionally, as emitter dimensions become smaller, it is desirable to reduce emitter resistance. Specific contact resistance ρC is 10-'Ω
When d is exceeded, the emitter resistance becomes dominant in the large collector current region, and deterioration of the current amplification factor and cutoff frequency becomes apparent.

The object of the present invention is to provide a p-type GaAs layer or a p-type GaAs layer with excellent reliability.
An object of the present invention is to provide a semiconductor device having a type Al1xGa, -1 (As layer).

[Means for solving problems]

The above purpose is to use p-type GaAs or p-type MXGal-xAs.
p++GaAs or p''+In, Ga, -, As on the layer
arranging the p++GaAs or p''+In, Ga1
- This is achieved by a semiconductor device characterized in that a non-alloy metal layer is disposed on the As layer and the two are brought into ohmic contact through a tunnel junction.

In order to make ohmic contact by tunnel junction, for example, the p++GaAs layer contains a p-type impurity of about 5X10"a++-' or more, or p" I nyGal.
It is preferable that the -yAs layer contains a p-type impurity of about lXl0'''C!1-'' or more. In such a case, the specific contact resistance ρC becomes less than to-'Ωd and a tunnel junction is formed. In addition, the p ”I nyGal-yAs layer is
p-type GaAs or p-type All XG a 1- X A
It is preferable to gradient the composition so that the value of y is small on the side closer to the 8th layer, and the value of y is larger on the opposite side.

Non-alloy metals include Ti/Pt/Au, Mo/
Au, W, WSi, An, WN, WAQ, etc. can be used. In particular, it is preferable to use metals such as WSi, WAQ, WN, and W, which have excellent workability and can make the dimensions of the emitter electrode and emitter the same using a dry etching method. This is particularly useful when forming integrated circuits.

This will be explained using FIG. 1. Figure 1(a) (
b) is a cross-sectional view of a main part of a semiconductor device showing an outline of the present invention. In FIG. 1(a), 71 is a p-type GaAs layer (or p-type 1n, Ga1-y
70 is a p++ GaAs layer (or 1x to 19
p++In, G containing p-type impurities of the order of ΩGW-'
a knee, As layer, in this case, as mentioned above, the underlying layer is p-type G
60 is a non-alloy type metal such as Ti/Pt/Au, Mo/Au, etc. be. Such a structure can be formed by a normal lift-off method.

On the other hand, FIG. 1(b) shows WSi as a non-alloy metal.
In this example, a metal with excellent workability such as , WM, W, etc. is used. In this case, the p++ GaAs layer 70. p
The type GaAs layer 71 can be etched away by dry etching to form a shape as shown in the figure.

[For production]

In the present invention, unlike alloy type ohmic contacts,
Since there is no diffusion of atoms forming levels in the GaAs layer, highly reliable ohmic contact can be obtained. In addition, for the same reason, the specific contact resistance ρC is less deteriorated and is at least 1
A value of approximately 0-@Ωl is obtained.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

Example I FIG. 2 shows an example in which the present invention is applied to a Pnpn type GaAsBT. In the figure, 50 is Ti (300 people)/Pt (
300) / Au (1500) emitter electrode.

17 is p++Ga containing Be lXl0"am-'
As (1000 people), 16 Be 5X1017an-
"Contains p-type GaAs (1500 people), 15 is 16
p-type AQGaAs (100
0 people), 14 is an n-type containing 4 x 10" cm of Si.
lGaAs (250 people), 13 is undoped AAGa
As (50 people), 12 is undoped (p-)GaAs
(1500 people), 11 Be 5 X 10” aa
10 is a semi-insulating GaAs substrate.The base electrode 51 and the collector electrode 52 are formed according to normal specifications.Such a multilayer film is formed using molecular beam epitaxy (MBE). ), but
Element isolation was performed by mesa isolation, which may be formed by MOCVD. Emitter electrode is WSi (3500 people)
After deposition, dry etching may be used.

This semiconductor element prevented deterioration of the pn junction and made the specific contact resistance ρC 10 −6 Ωd or less.

In this embodiment, p++GaAs is used as the material 17, but p++GaAs may also be used.

Example 2 FIG. 3 shows an example in which the present invention is applied to a normal Pnp type HBT.

50 is Mo (1500 people) / Au (1500 people) emitter electrode, 21 is Mg in 5X10"CIl+-
”Including p + + nA Ga□-yAs (0,5≦
The slope is such that when y≦O, the value of y is small below the layer, and the value of y becomes large above the first layer. 1500 people), 20 is M
p-type GaAs (1
19 is a p-type AQ person), 12' is Mg 2
Corephthalic GaAs (30
00 people), 11 is the collector layer with Mg 5X10"as-
'Contains p++GaAs (3000 people), 1o is a semi-insulating GaAs substrate. The base electrode 51 and collector electrode 52 are formed by a normal method. These multilayer films are also formed by the MBE method or MOCVD method as in Example 1. The effects of Example 2 were also similar to those of Example 1.

In addition, in these examples, the case where the emitter region is formed on the surface side has been explained, but the present invention can also be applied to the formation of the collector electrode in the case of a collector top structure where the collector layer is formed on the surface side. It is effective to apply In other words, there is an n-layer base layer below the collector layer, which causes problems such as deterioration of the collector-base pn junction and collector resistance, but this problem can be solved by applying the present invention in this case as well. can.

In the above Examples 1 and 2, Be and Mg are used as p-type impurities of p++GaAs or p++InyGa1-, As for ohmic formation of the emitter electrode, and MBE method or MO
It was doped by CVD method. But gas source MBE
By the (MO-MBE) method, when an organic metal (for example, trimethyl gallium) is used as a gas source, C (carbon) can be doped as a P-type impurity. in this case,
It can be doped to approximately 10"(!m-'), and C will not diffuse even after a thermal process of 800°C or higher. In this way, the MO-MBE method can dope p++GaAs or p"I
A nyGal-yAs layer may also be formed.

〔Effect of the invention〕

According to the present invention, a metal with low diffusivity and a high concentration of p++
By forming an ohmic electrode in the emitter region using a junction of GaAs or p''In, Ga1-, As, deterioration of the pn junction is prevented and the specific contact resistance ρC is reduced to 1O-6Ω.
It can be made less than l.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a main part of an embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views of a semiconductor device of an embodiment of the present invention. lO...Semi-insulating GaAs substrate

Claims (1)

[Claims] 1. p-type GaAs or p-type Al_xGa_1_-_xA
p^+^+GaAs or p^+^+In_yG on the s layer
a_1_−_yAs layer is arranged, and the p^+^+GaAs
Alternatively, a semiconductor device characterized in that a non-alloy metal layer is disposed on the p^+^+In_yGa_1_-_yAs layer, and the two are brought into ohmic contact by a tunnel junction. 2. The above p-type GaAs or p-type Al_xGa_1_-_
2. The semiconductor device according to claim 1, wherein the xAs layer is a p-type region in a pn junction. 3. The above p^+^+GaAs or p^+^+In_yG
2. The semiconductor device according to claim 1, wherein the a_1_-_yAs layer is a layer containing carbon as a p-type impurity.