JPH01129769A - semiconductor integrated circuit - Google Patents
semiconductor integrated circuitInfo
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- JPH01129769A JPH01129769A JP62285964A JP28596487A JPH01129769A JP H01129769 A JPH01129769 A JP H01129769A JP 62285964 A JP62285964 A JP 62285964A JP 28596487 A JP28596487 A JP 28596487A JP H01129769 A JPH01129769 A JP H01129769A
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- vcc
- integrated circuit
- power supply
- semiconductor integrated
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- C—CHEMISTRY; METALLURGY
- C10—PETROLEUM, GAS OR COKE INDUSTRIES; TECHNICAL GASES CONTAINING CARBON MONOXIDE; FUELS; LUBRICANTS; PEAT
- C10L—FUELS NOT OTHERWISE PROVIDED FOR; NATURAL GAS; SYNTHETIC NATURAL GAS OBTAINED BY PROCESSES NOT COVERED BY SUBCLASSES C10G, C10K; LIQUEFIED PETROLEUM GAS; ADDING MATERIALS TO FUELS OR FIRES TO REDUCE SMOKE OR UNDESIRABLE DEPOSITS OR TO FACILITATE SOOT REMOVAL; FIRELIGHTERS
- C10L10/00—Use of additives to fuels or fires for particular purposes
- C10L10/08—Use of additives to fuels or fires for particular purposes for improving lubricity; for reducing wear
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- C—CHEMISTRY; METALLURGY
- C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
- C08K—Use of inorganic or non-macromolecular organic substances as compounding ingredients
- C08K5/00—Use of organic ingredients
- C08K5/0008—Organic ingredients according to more than one of the "one dot" groups of C08K5/01 - C08K5/59
- C08K5/005—Stabilisers against oxidation, heat, light, ozone
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- C—CHEMISTRY; METALLURGY
- C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
- C08K—Use of inorganic or non-macromolecular organic substances as compounding ingredients
- C08K5/00—Use of organic ingredients
- C08K5/36—Sulfur-, selenium-, or tellurium-containing compounds
- C08K5/37—Thiols
- C08K5/375—Thiols containing six-membered aromatic rings
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- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
- C09K—MATERIALS FOR MISCELLANEOUS APPLICATIONS, NOT PROVIDED FOR ELSEWHERE
- C09K19/00—Liquid crystal materials
- C09K19/04—Liquid crystal materials characterised by the chemical structure of the liquid crystal components, e.g. by a specific unit
- C09K19/06—Non-steroidal liquid crystal compounds
- C09K19/08—Non-steroidal liquid crystal compounds containing at least two non-condensed rings
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- C—CHEMISTRY; METALLURGY
- C10—PETROLEUM, GAS OR COKE INDUSTRIES; TECHNICAL GASES CONTAINING CARBON MONOXIDE; FUELS; LUBRICANTS; PEAT
- C10L—FUELS NOT OTHERWISE PROVIDED FOR; NATURAL GAS; SYNTHETIC NATURAL GAS OBTAINED BY PROCESSES NOT COVERED BY SUBCLASSES C10G, C10K; LIQUEFIED PETROLEUM GAS; ADDING MATERIALS TO FUELS OR FIRES TO REDUCE SMOKE OR UNDESIRABLE DEPOSITS OR TO FACILITATE SOOT REMOVAL; FIRELIGHTERS
- C10L1/00—Liquid carbonaceous fuels
- C10L1/10—Liquid carbonaceous fuels containing additives
- C10L1/14—Organic compounds
- C10L1/22—Organic compounds containing nitrogen
- C10L1/221—Organic compounds containing nitrogen compounds of uncertain formula; reaction products where mixtures of compounds are obtained
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- C—CHEMISTRY; METALLURGY
- C10—PETROLEUM, GAS OR COKE INDUSTRIES; TECHNICAL GASES CONTAINING CARBON MONOXIDE; FUELS; LUBRICANTS; PEAT
- C10L—FUELS NOT OTHERWISE PROVIDED FOR; NATURAL GAS; SYNTHETIC NATURAL GAS OBTAINED BY PROCESSES NOT COVERED BY SUBCLASSES C10G, C10K; LIQUEFIED PETROLEUM GAS; ADDING MATERIALS TO FUELS OR FIRES TO REDUCE SMOKE OR UNDESIRABLE DEPOSITS OR TO FACILITATE SOOT REMOVAL; FIRELIGHTERS
- C10L1/00—Liquid carbonaceous fuels
- C10L1/10—Liquid carbonaceous fuels containing additives
- C10L1/14—Organic compounds
- C10L1/24—Organic compounds containing sulfur, selenium and/or tellurium
- C10L1/2493—Organic compounds containing sulfur, selenium and/or tellurium compounds of uncertain formula; reactions of organic compounds (hydrocarbons, acids, esters) with sulfur or sulfur containing compounds
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- C—CHEMISTRY; METALLURGY
- C10—PETROLEUM, GAS OR COKE INDUSTRIES; TECHNICAL GASES CONTAINING CARBON MONOXIDE; FUELS; LUBRICANTS; PEAT
- C10L—FUELS NOT OTHERWISE PROVIDED FOR; NATURAL GAS; SYNTHETIC NATURAL GAS OBTAINED BY PROCESSES NOT COVERED BY SUBCLASSES C10G, C10K; LIQUEFIED PETROLEUM GAS; ADDING MATERIALS TO FUELS OR FIRES TO REDUCE SMOKE OR UNDESIRABLE DEPOSITS OR TO FACILITATE SOOT REMOVAL; FIRELIGHTERS
- C10L1/00—Liquid carbonaceous fuels
- C10L1/10—Liquid carbonaceous fuels containing additives
- C10L1/14—Organic compounds
- C10L1/26—Organic compounds containing phosphorus
- C10L1/2691—Compounds of uncertain formula; reaction of organic compounds (hydrocarbons acids, esters) with Px Sy, Px Sy Halz or sulfur and phosphorus containing compounds
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- Combustion & Propulsion (AREA)
- Manipulation Of Pulses (AREA)
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- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体集積回路に関し、特にバッチリバック
アップ可能なスタティックランダムアクセスメモリに好
適な電圧コンバータに関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to a voltage converter suitable for a static random access memory that can be backed up perfectly.
従来、電圧コンバータに関しては、第7図(a)。 Regarding the conventional voltage converter, FIG. 7(a) shows the conventional voltage converter.
(b)に示すアイ・イー・イー・イー、インターナショ
ナル・ソリッド・ステート・サーキット・コンファラン
ス、 1987テクニカルダイジエスト、p252(I
EEE l5SCC1987,Tech、Dig、 p
252)に記載のように、外部電源電位■cCと設定電
位Vgvの比較は差動アンプを用いていた。また、外部
電源から内部電源へ電荷を供給するために、N型MO8
FETとP型MO8FETの2−’)(7)MOSFE
Tを用い、NMO8FETは外部より印加する電圧VC
Cがv■より大きい場合に、アンプを動作させて駆動り
、、PMOSFETはVCCがVBIFより小さい場合
に、ゲート電極を電気的に接地し、導通状態にしていた
。この従来例は、外部電圧としてTTLの電圧5vをM
O3LSIに使用すると、MOSFETのホットキャリ
アによる特性劣化が起こるこ ゛とに対して、対策した
ものである。電源電圧vcCが大きい場合には、電圧コ
ンバータが働き、内部電源電圧vDoにはvcCより小
さい所定の電圧が印加されてホットキャリアによるMO
SFETの劣化がないようにする。また、VCCが小さ
い場合には、内部電源電圧VDDがVCCと一致するよ
うにしたものである。IEE, International Solid State Circuit Conference, 1987 Technical Digest, p252 (I
EEE 15SCC1987, Tech, Dig, p
252), a differential amplifier was used to compare the external power supply potential ■cC and the set potential Vgv. In addition, in order to supply charge from the external power supply to the internal power supply, an N-type MO8
FET and P-type MO8FET 2-') (7) MOSFE
NMO8FET uses externally applied voltage VC.
When C is larger than v■, the amplifier is operated and driven, and when VCC is smaller than VBIF, the gate electrode of the PMOSFET is electrically grounded and turned on. In this conventional example, a TTL voltage of 5V is used as an external voltage.
This is a countermeasure against the deterioration of characteristics caused by hot carriers in MOSFETs when used in O3LSIs. When the power supply voltage vcC is large, the voltage converter works, and a predetermined voltage smaller than vcC is applied to the internal power supply voltage vDo to reduce MO by hot carriers.
To prevent deterioration of SFET. Furthermore, when VCC is small, internal power supply voltage VDD is made to match VCC.
上記従来技術では、以下に述べる2つの問題点がある。 The above conventional technology has two problems as described below.
第1の問題点は、VCC電圧ディテクタに差動アンプを
使用し、どのようなりCC電圧においてもバイアス電流
を流しているために、低消費電流化が図れないことにあ
る。このような方式は、バッテリバックアップ用途のL
SIでは電流が大きすぎて使用できない。たとえば、バ
ッテリバックアップ用途のCMO8SRAM等には使用
できない。The first problem is that since a differential amplifier is used for the VCC voltage detector and a bias current is passed regardless of the CC voltage, it is impossible to reduce current consumption. This type of method is suitable for battery backup applications.
With SI, the current is too large to be used. For example, it cannot be used in CMO8SRAM for battery backup purposes.
第2の問題点は、ドライバには大きな電流を流すために
大きな面積のMOSFETを用いる必要があるが、この
従来技術では、ドライバにvccがvllwより大きい
場合にはNMO8FET、VCCがvBvより小さい場
合にはPMOSFETと2つのドライバを用いているた
めに、大きな占有面積を必要とすることである。The second problem is that it is necessary to use a large-area MOSFET in the driver to allow a large current to flow, but in this conventional technology, the driver uses an NMO8FET when vcc is larger than vllw, and when Vcc is smaller than vBv. Since it uses a PMOSFET and two drivers, it requires a large occupied area.
本発明の目的は、このような従来の問題点を解決し、電
源電位VCCが設定電位v0より小さい電位の場合の低
消費電力化を図り、低電圧動作においてはバッテリバッ
クアップ可能とし、占有面積の小さいLSI用の電圧コ
ンバータとして機能する半導体集積回路を提供すること
にある。The purpose of the present invention is to solve such conventional problems, reduce power consumption when the power supply potential VCC is lower than the set potential v0, enable battery backup in low voltage operation, and reduce the occupied area. An object of the present invention is to provide a semiconductor integrated circuit that functions as a voltage converter for a small LSI.
上記問題点を解決するため、本発明の半導体集積回路は
、半導体基板上に第1の電源電位vc0を与える配線と
第2の電源電位VOOを与える配線を有し、上記第1の
電源電位VCCとあらかじめ定められた設定電位V□と
を比較し、該比較結果を制御信号として出力し、かつ上
記電位VCCがvsWより小さい場合には電力消費が1
0μW以下になるように電流をカットする手段を有する
vcc電圧ディテクタと、上記制御信号により上記電位
VCCがVSVより大きい場合にのみ電力を消費するア
ンプとを具備し、該アンプにより上記第1の電源電位V
CCから第2の電源電位VDDへ電荷を供給するための
ドライバを駆動することに特徴がある。In order to solve the above problems, the semiconductor integrated circuit of the present invention has a wiring for supplying a first power supply potential vc0 and a wiring for supplying a second power supply potential VOO on a semiconductor substrate, and a predetermined set potential V□, and outputs the comparison result as a control signal, and if the potential VCC is smaller than vsW, the power consumption is reduced to 1.
A VCC voltage detector having a means for cutting the current so that the current becomes 0 μW or less, and an amplifier that consumes power only when the potential VCC is greater than VSV according to the control signal, and the amplifier causes the first power source to Potential V
The feature is that a driver for supplying charge from CC to the second power supply potential VDD is driven.
また、上記半導体集積回路は、上記アンプとして第1の
PMOSFETを電流源とするカレントミラー型差動ア
ンプを用い、上記制御信号により第1のPMOSFET
を制御して上記差動アンプで消費される電力を制御する
ことに特徴がある。Further, the semiconductor integrated circuit uses a current mirror type differential amplifier using the first PMOSFET as a current source as the amplifier, and the control signal causes the first PMOSFET to
The feature is that the power consumed by the differential amplifier is controlled by controlling the power consumption of the differential amplifier.
さらに、上記半導体集積回路は、上記第2の電源電位v
n。の基準となる電位vR11KFを発生させる回路に
流れる電流を上記制御信号により制御し、上記ドライバ
に第2のPMOSFETを使用し、該第2のPMOSF
ETのゲート電極を電気的に接地電位にするための手段
を有し、上記第1の電源電位vccが上記設定電位vf
1vより小さい場合には、上記制御信号により第2のP
MOSFETのゲート電極を接地電位にすることに特徴
がある。Furthermore, the semiconductor integrated circuit has the second power supply potential v
n. A current flowing through a circuit that generates a reference potential vR11KF is controlled by the control signal, a second PMOSFET is used as the driver, and the second PMOSFET is used as the driver.
It has means for electrically bringing the gate electrode of the ET to a ground potential, and the first power supply potential vcc is equal to the set potential vf.
If it is smaller than 1v, the control signal causes the second P
The feature is that the gate electrode of the MOSFET is at ground potential.
本発明においては、電源電位vccが設定電位voより
小さい場合、vccとvBWの比較回路は電力消費がき
わめて小さくなる回路を有する一方。In the present invention, when the power supply potential vcc is lower than the set potential vo, the comparison circuit between vcc and vBW has a circuit whose power consumption is extremely small.
ここから発生する制御信号によりドライバを制御するア
ンプは非動作状態にして電力消費をなくす。The control signal generated from this causes the amplifier that controls the driver to be inactive to eliminate power consumption.
また、基準電圧発生回路もこれに流れる電流をなくす。The reference voltage generation circuit also eliminates the current flowing through it.
この時、ドライバはアンプとは別の電気的手段により導
通状態に保たれる。これらのことにより、VCCがvl
lvより小さい場合は電力消費をきわめて小さくし、バ
ッテリバックアップへ応用可能な電圧変換器を実現でき
る。At this time, the driver is kept in a conductive state by electrical means separate from the amplifier. Due to these things, VCC becomes vl
If it is smaller than lv, the power consumption can be made extremely small, and a voltage converter that can be applied to battery backup can be realized.
一方、VCCがV8Vより大きい場合には、Vccがv
6vより小さい場合に用いたものと同一のドライバを用
い、これをアンプで制御してVDDを所定の電位にする
。このことにより、ドライバに必要な占有面積を小さく
できる。On the other hand, when VCC is greater than V8V, Vcc is
The same driver as that used when the voltage is smaller than 6V is used, and this is controlled by an amplifier to bring VDD to a predetermined potential. This makes it possible to reduce the area required for the driver.
以下、本発明の一実施例を、図面により詳細に説明する
。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第1図は、本発明の第1の実施例を示す半導体集積回路
の基本構成図である。FIG. 1 is a basic configuration diagram of a semiconductor integrated circuit showing a first embodiment of the present invention.
第1図において、1はノードから与えられる第1の電源
電位VCCと設定電位v8vとを比較するV c c
’!圧ディテクタ、2は基準電圧V R,、を有する差
動アンプ、3は第1の電源電位vC0がら第2の電源電
位vDoへ電荷を供給するためのドライバ、4はVCC
電圧ディテクタ1から出力される制御信号に応じて差動
アンプ2をON10 F Fするスイッチである。また
、5はVCC電圧ディテクタ1に内蔵する電流カット回
路であり、電位vcCとV。。In FIG. 1, 1 is V c c which compares the first power supply potential VCC given from the node and the set potential v8v.
'! 2 is a differential amplifier having a reference voltage VR, 3 is a driver for supplying charge from the first power supply potential vC0 to the second power supply potential vDo, 4 is VCC.
This is a switch that turns on the differential amplifier 2 according to the control signal output from the voltage detector 1. Further, 5 is a current cut circuit built in the VCC voltage detector 1, and has potentials vcC and V. .
を比較して、VCCがv8.より小さい場合には電圧デ
ィテクタ1に流れる電流を切って消費電流をなくす。す
なおち、電力消費が1oμW以下になるようにする。以
下1本実施例の動作を説明する。By comparing VCC with v8. If it is smaller, the current flowing to the voltage detector 1 is cut off to eliminate the current consumption. In other words, the power consumption should be 1oμW or less. The operation of this embodiment will be explained below.
vcc電圧ディテクタ1からは、vccとv8vを比較
した結果に応じて制御信号を出力し、Vooがvoより
大きい場合には、スイッチ4がONとなり、差動アンプ
2を動作させる。差動アンプ2では、基準電圧■R6F
に応じてドライバ3を制御してVOOを与える端子に電
荷を供給する。ここで、差動アンプ2の入力には、vo
o電位のフィードバックがかかっており、V、f、がV
SWより大きい場合には、vooをvR6Fに一致する
ようにドライバ3を制御するようになっている。また、
VC,がV、svより小さい場合には、電流カット回路
5によりスイッチ4を0FF(非動作状態)して差動ア
ンプ2に流れる電流をなくすことができる。The vcc voltage detector 1 outputs a control signal according to the result of comparing vcc and v8v, and when Voo is larger than vo, the switch 4 is turned on and the differential amplifier 2 is operated. In differential amplifier 2, the reference voltage ■R6F
The driver 3 is controlled in accordance with this to supply charge to the terminal that provides VOO. Here, the input of the differential amplifier 2 is vo
o potential feedback is applied, and V and f are V
If it is larger than SW, the driver 3 is controlled so that voo matches vR6F. Also,
When VC, is smaller than V, sv, the current cut circuit 5 turns off the switch 4 (inactive state) to eliminate the current flowing to the differential amplifier 2.
以上の結果により、VCCがV8%lより小さい場合に
は、vcc電圧ディテクタ1.差動アンプ2による消費
電力をなくし、SRAM等のバッテリバックアップ用途
のLSIと組み合わせることが可能となる。According to the above results, when VCC is smaller than V8%l, the vcc voltage detector 1. The power consumption by the differential amplifier 2 is eliminated, and it becomes possible to combine it with an LSI for battery backup use such as an SRAM.
第2図は1本発明の第2の実施例を示す半導体集積回路
の構成図である。これは、第1図の基本構成を少し具体
化したものである。FIG. 2 is a block diagram of a semiconductor integrated circuit showing a second embodiment of the present invention. This is a slightly more specific version of the basic configuration shown in FIG.
本実施例においては、基準電圧発生器6.差動アンプ2
はそれぞれPMOSFET7および8を通して電源VC
Cに接続されており、VCCがv9vより大きい場合に
は、制御信号によりPMOSFET7および8が導通し
て、基準電圧発生器6および差動アンプ2を動作させて
ドライバとなるPMO3FET9を制御する。一方、v
cCがVf3Wより小さい場合には、PMOSFET7
および8を制御信号によりカットオフして基準電圧発生
器6および差動アンプ2に流れる電流を抑える一方、N
MO8FETIOを導通状態にしてPMO3FET9の
ゲート電位を与えるノード1°1を接地電位にしてPM
OSFET9を導通状態にしてVDDとvo。を一致さ
せる。このようにすることにより。In this embodiment, the reference voltage generator 6. Differential amplifier 2
are connected to the power supply VC through PMOSFETs 7 and 8, respectively.
When VCC is greater than v9v, the control signal turns on PMOSFETs 7 and 8, operates reference voltage generator 6 and differential amplifier 2, and controls PMO3FET 9, which serves as a driver. On the other hand, v
If cC is less than Vf3W, PMOSFET7
and 8 are cut off by a control signal to suppress the current flowing to the reference voltage generator 6 and the differential amplifier 2.
MO8FETIO is made conductive and node 1°1, which provides gate potential of PMO3FET9, is set to ground potential and PM
OSFET9 is made conductive and VDD and vo. Match. By doing this.
voo端子に接続されている回路のみに電流が流れるこ
とになる。この時、vDo端子にバッテリバックアップ
可能なSRAM等のLSIを接続することにより、バッ
テリバックアップ可能なシステムにすることができる。Current will flow only through the circuit connected to the voo terminal. At this time, by connecting an LSI such as an SRAM capable of battery backup to the vDo terminal, it is possible to create a system capable of battery backup.
また1本実施例においては、vo。からVDDに電荷を
供給する手段として、vcoがVSWより大きい場合も
小さい場合もPMOSFET9を用いているために、両
者の場合にそれぞれドライバを分けた場合よりも占有面
積を小さくすることができる。Moreover, in one embodiment, vo. Since the PMOSFET 9 is used as a means for supplying charge from to VDD both when vco is larger than VSW and when it is smaller than VSW, the occupied area can be made smaller than when separate drivers are used in both cases.
第3図は、第1図または第2図におけるVCC電圧ディ
テクタ1の具体的回路構成図である。FIG. 3 is a specific circuit diagram of the VCC voltage detector 1 shown in FIG. 1 or 2. In FIG.
第3図において、20,21,22,23はNMOSF
ETであり、ダイオード接続になっている。In Figure 3, 20, 21, 22, 23 are NMOSF
ET and is diode-connected.
24.27は抵抗、25はコンデンサ、26はNMOS
FET、15はNMOSFET28およびPMOSFE
T29から構成されたCMOSインバータ、16はNM
OSFET30およびPMOSFET31から構成され
たCMOSインバータである。24.27 is resistor, 25 is capacitor, 26 is NMOS
FET, 15 is NMOSFET28 and PMOSFE
CMOS inverter composed of T29, 16 is NM
This is a CMOS inverter composed of an OSFET 30 and a PMOSFET 31.
第4図は、第3図のvC0電圧ディテクタ1の回路動作
を説明するための図である。(a)はvcCに対する端
子32.33の電位であり、(b)はvcoに対する第
3図のIi、I、を示したものである。以下、第3図の
回路動作を第4図により説明する。FIG. 4 is a diagram for explaining the circuit operation of the vC0 voltage detector 1 of FIG. 3. (a) shows the potential of terminals 32, 33 with respect to vcC, and (b) shows Ii, I of FIG. 3 with respect to vco. Hereinafter, the operation of the circuit shown in FIG. 3 will be explained with reference to FIG.
MOSFET20〜23はダイオード接続になっている
ために、1つのMOSFETの電圧電流式は次式のよう
に与えられる。Since the MOSFETs 20 to 23 are diode-connected, the voltage-current equation for one MOSFET is given by the following equation.
ID”(!(ffiogVo) ’ ” ’ (
1)但し、Vo≦vT8
I o= k (Va−V?+1)” ・” ・(
2)但し、VD>VT□
ニーで、I、はドレイン電流、VDはドレイン電圧で、
ダイオード接続のためVcと一致している。ID” (! (ffiogVo) ' ” ' (
1) However, Vo≦vT8 I o= k (Va-V?+1)” ・” ・(
2) However, VD>VT□ knee, I is the drain current, VD is the drain voltage,
Due to diode connection, it matches Vc.
α、には定数、VよはMOSFETのしきい値電圧であ
る。(1)式はいわゆるサブシュレッショールド領域で
電流が小さくできる。(2)式は大電流領域を示してい
る。α is a constant, and V is the threshold voltage of the MOSFET. Equation (1) allows the current to be small in the so-called subthreshold region. Equation (2) indicates a large current region.
いま、V丁、=0.9Vとする。すなわち、 VCC=
2.8Vとした場合(Vcc< Vg、(7)状態)、
VCC電圧は20〜23のMOSFETで分圧されるこ
とになり、1つのMOSFETにかかる電圧は、0.7
vとなる。コノ場合、MOSFET(7)電流は(1)
式で与えられる式、すなわちサブシュレッショールド領
域になり、ここに流れる電流は第4図(b)で示すよう
に非常に小さくなる。したがって、端子32はほとんど
v8Bと同電位になる。すると、MOSFET26は非
導通状態になり、端子33はvccと同電位になる。後
段にはバッファとしてのCMOSインバータが2段つい
ているので、端子34にはVCCと同電位の信号が出方
される。一方、VCCが78wより大きい場合、たとえ
ば、VCCが5vの場合、MOSFET20〜23にか
かる電圧は77以上になるために、(2)式で与えられ
る大電流領域で動作する。すると、抵抗24に電流が流
れるために端子32の電位がMOSFET26を導通状
態にする程の電位になる。すると、端子33がVIii
13に近い電位になり、結果として端子34にはVおと
同電位の信号が出力される。Now, let Vd = 0.9V. That is, VCC=
When set to 2.8V (Vcc<Vg, (7) state),
The VCC voltage will be divided by 20 to 23 MOSFETs, and the voltage applied to one MOSFET will be 0.7
It becomes v. In this case, MOSFET (7) current is (1)
In other words, it becomes a subthreshold region, and the current flowing here becomes extremely small as shown in FIG. 4(b). Therefore, the terminal 32 has almost the same potential as v8B. Then, MOSFET 26 becomes non-conductive, and terminal 33 becomes at the same potential as vcc. Since there are two stages of CMOS inverters as buffers in the latter stage, a signal having the same potential as VCC is outputted to the terminal 34. On the other hand, when VCC is larger than 78W, for example, when VCC is 5V, the voltage applied to MOSFETs 20 to 23 becomes 77 or more, so that the MOSFET operates in the large current region given by equation (2). Then, since a current flows through the resistor 24, the potential of the terminal 32 becomes such a potential as to make the MOSFET 26 conductive. Then, terminal 33 becomes VIiii
As a result, a signal having the same potential as V is output to the terminal 34.
このように、本回路においては、vcCがv8Wより小
さい場合と大きい場合でそれぞれ端子34に対して、そ
れを判定した信号7;を出力するが、特にvcCがv8
.より小さい場合には、回路中定常的に流れる電流はほ
とんどなく、低消費電力化が達成できる。In this way, this circuit outputs the determined signal 7 to the terminal 34 when vcC is smaller than v8W and when it is larger than v8W, but especially when vcC is v8W,
.. When it is smaller, almost no current flows steadily in the circuit, and low power consumption can be achieved.
第5図(a) it第1図または第2図におけるアンプ
とドライバの部分の具体的回路構成図であり、(b)は
差動アンプの構成例を示す図である。FIG. 5(a) is a specific circuit configuration diagram of the amplifier and driver portion in FIG. 1 or FIG. 2, and FIG. 5(b) is a diagram showing an example of the configuration of a differential amplifier.
第5図において、51はVCC電圧ディテクタ1から発
生する信号T;゛を与える端子であり、55は差動アン
プ、53はドライバとなるPMOSFET、52はアン
プ55のスイッチとなるPMOSFET、54はドライ
バのスイッチとなるNMOSFET、56は基準電圧発
生器、58 ハP MOSFET、59はNMOSFE
Tである。In FIG. 5, 51 is a terminal that provides a signal T; generated from the VCC voltage detector 1, 55 is a differential amplifier, 53 is a PMOSFET that serves as a driver, 52 is a PMOSFET that serves as a switch for the amplifier 55, and 54 is a driver. 56 is a reference voltage generator, 58 is a P MOSFET, and 59 is an NMOSFE.
It is T.
次に本回路の動作を説明する。Next, the operation of this circuit will be explained.
■信号が” High ”の場合、すなわち、VCCが
■8Wより小さい場合はPMOSFET52は非導通状
態になり、アンプ55は動作しない。また、MOSFE
T54が導通状態になり、端子57がVoslt!位に
なるので、PMOSFET53が導通状態になり、vo
CとVDDの電位を同電位にする。■When the signal is "High", that is, when VCC is smaller than ■8W, the PMOSFET 52 becomes non-conductive and the amplifier 55 does not operate. Also, MOSFE
T54 becomes conductive and terminal 57 becomes Voslt! PMOSFET 53 becomes conductive and vo
Make the potentials of C and VDD the same.
一方、四がII L Ov IIの場合、すなわちVC
Cがvglより大きい場合には、NMOSFET54が
非導通状態になる一方、PMOSFET52が導通状態
になり、アンプ55が動作し、基準電圧V□。On the other hand, if 4 is II L Ov II, that is, VC
When C is larger than vgl, the NMOSFET 54 becomes non-conductive, while the PMOSFET 52 becomes conductive, the amplifier 55 operates, and the reference voltage V□.
とV。f、が同電位になるようにPMOSFET52が
導通状態になり、アンプ55が動作し、基′$雷電圧R
EFとvooが同電位になるようにPMOSFET53
を制御するように負帰還をかけた回路になっている。こ
こで、vREFとして、Vool)J子に接続する内部
回路のMOSFETがホットキャリアによる劣化を受け
ないような電圧を選ぶ必要がある。このように、実施例
の回路においては。and V. The PMOSFET 52 becomes conductive so that f and have the same potential, the amplifier 55 operates, and the basic lightning voltage R
PMOSFET53 so that EF and voo have the same potential
The circuit is designed with negative feedback to control. Here, it is necessary to select a voltage as vREF such that the MOSFET of the internal circuit connected to the Vool) J terminal is not degraded by hot carriers. In this way, in the circuit of the embodiment.
VCCがV8vより小さい場合には、MOSFET53
以外で電力消費することがなく、低電力化が図れる回路
になっている。If VCC is less than V8v, MOSFET53
It is a circuit that consumes no power other than that, making it possible to reduce power consumption.
また、VCCがV。よりも大きい場合、小さい場合共に
ドライバとしてPMO3FET53を用いているので、
面積を小さくできる。また、上記の差動アンプ55は第
5図(b)で示したようなカレントミラー型が例として
あげられる。Also, VCC is V. Since PMO3FET53 is used as a driver for both larger and smaller cases,
The area can be reduced. Further, the above-mentioned differential amplifier 55 may be of a current mirror type as shown in FIG. 5(b).
第6図は、上記基準電圧VR1!、を作る回路の具体的
構成図である。基準電圧V R,、は電池等を用いても
よいが、第6図のように、回路的に作ることもできる0
本回路はVCC電圧をNMOSFET61〜64と、P
MOSFET65.66で分圧して作るものである。こ
の時、PMOSFET67はI信号により導通および非
導通状態に選択することができる。すなわち、VCC電
圧がVSWより小さい場合には、このPMOSFET6
7が非導通状態になり、ここで消費する電力をなくすこ
とが可能である。FIG. 6 shows the reference voltage VR1! , is a specific configuration diagram of a circuit for making . The reference voltage V R, , may be generated using a battery or the like, but it can also be created using a circuit as shown in Figure 6.
This circuit connects the VCC voltage to NMOSFETs 61 to 64 and P
It is created by dividing the pressure using MOSFETs 65 and 66. At this time, the PMOSFET 67 can be selected to be conductive or non-conductive by the I signal. That is, when the VCC voltage is lower than VSW, this PMOSFET6
7 becomes non-conductive, and it is possible to eliminate the power consumed here.
以上説明したように、本発明によれば、電源電位VCC
が設定電位vBvより小さい場合には、VCC電圧ディ
テクタ、増幅器、基準電圧発生器には電流がほとんど流
れないようになっているので低消費電力化でき、さらに
ドライバを導通状態にしてVCCとVDDを導通状態に
できる。一方、VCCがVSWより大きい場合には、
Vcc??!圧ディテクタ。As explained above, according to the present invention, the power supply potential VCC
When V is smaller than the set potential vBv, almost no current flows through the VCC voltage detector, amplifier, and reference voltage generator, resulting in lower power consumption.Furthermore, the driver is made conductive to connect VCC and VDD. Can be made conductive. On the other hand, if VCC is greater than VSW,
Vcc? ? ! pressure detector.
増幅器、基準電圧発生器には電流を流すことを必要とす
るが、増幅器によりドライバを制御してvo。を基準電
圧発生器から発生する基準電圧にできるので、vccf
l!圧が大きくても、vDD端子につながるLSI中の
MOSFETのホットキャリアによる劣化のない信頼性
の高いLSIを実現できる。また、いずれの動作の場合
も同一のドライバを用いるため、ドライバの占める占有
面積を小さくできる。The amplifier and reference voltage generator require current to flow, and the driver is controlled by the amplifier. can be the reference voltage generated from the reference voltage generator, so vccf
l! Even if the voltage is large, a highly reliable LSI that is free from deterioration due to hot carriers in the MOSFET in the LSI connected to the vDD terminal can be realized. Furthermore, since the same driver is used for both operations, the area occupied by the driver can be reduced.
第1図は本発明の第1の実施例を示す半導体集積回路の
基本構成図、第2図は本発明の第2の実施例を示す半導
体集積回路の構成図、第3図は本発明の実施例における
VCC電圧ディテクタの具体的回路構成図、第4図は第
3図におけるVCC電圧ディテクタの動作を説明するた
めの図、第5図は本発明の実施例における増幅器とドラ
イバの部分の回路の具体的構成図、第6図は本発明の実
施例における基準電圧V□2を作る回路の具体的構成図
、第7図は従来の半導体集積回路(電圧コンバータ)の
構成図である。
1:Vcc電圧ディテクタ、2:差動アンプ、3:ドラ
イバ、4:スイッチ、5:電流カット回路、6:基準電
圧発生回路、7,8,9 : PMOSFET、10
: NMOSFET、11 :ノード。
第 1 図
第 2 図
VCC
第 3 図
cc
′S25 ””・第 4
図
(a)
VCC(ト)
第 5 図
(a)
CCFIG. 1 is a basic configuration diagram of a semiconductor integrated circuit showing a first embodiment of the invention, FIG. 2 is a configuration diagram of a semiconductor integrated circuit showing a second embodiment of the invention, and FIG. A specific circuit configuration diagram of the VCC voltage detector in the embodiment, FIG. 4 is a diagram for explaining the operation of the VCC voltage detector in FIG. 3, and FIG. 5 is a circuit diagram of the amplifier and driver portion in the embodiment of the present invention. FIG. 6 is a specific configuration diagram of a circuit for generating the reference voltage V□2 in an embodiment of the present invention, and FIG. 7 is a configuration diagram of a conventional semiconductor integrated circuit (voltage converter). 1: Vcc voltage detector, 2: Differential amplifier, 3: Driver, 4: Switch, 5: Current cut circuit, 6: Reference voltage generation circuit, 7, 8, 9: PMOSFET, 10
: NMOSFET, 11 : Node. Fig. 1 Fig. 2 VCC Fig. 3 cc 'S25 ""・No. 4
Figure (a) VCC (G) Figure 5 (a) CC
Claims (1)
配線と第2の電源電位V_D_Dを与える配線を有し、
上記第1の電源電位V_C_Cとあらかじめ定められた
設定電位V_S_Wとを比較し、該比較結果を制御信号
として出力し、かつ上記電位V_C_CがV_S_Wよ
り小さい場合には電力消費が10μW以下になるように
電流をカットする手段を有するV_C_C電圧ディテク
タと、上記制御信号により上記電位V_C_CがV_S
_Wより大きい場合にのみ電力を消費するアンプとを具
備し、該アンプにより上記第1の電源電位V_C_Cか
ら第2の電源電位V_D_Dへ電荷を供給するためのド
ライバを駆動することを特徴とする半導体集積回路。 2、特許請求の範囲第1項記載の半導体集積回路におい
て、上記アンプとして第1の電流源を有する差動アンプ
を用い、上記制御信号により第1の電流源を制御して上
記差動アンプで消費される電力を制御することを特徴と
する半導体集積回路。 3、特許請求の範囲第2項記載の半導体集積回路におい
て、上記第2の電源電位V_D_Dの基準となる電位V
_R_E_Fを発生させる回路に流れる電流を上記制御
信号により制御することを特徴とする半導体集積回路。 4、特許請求の範囲第3項記載の半導体集積回路におい
て、上記ドライバに第2のPMOSFETを使用し、該
第2のPMOSFETのゲート電極を電気的に接地電位
にするための手段を有し、上記第1の電源電位V_C_
Cが上記設定電位V_S_Wより小さい場合には、上記
制御信号により第2のPMOSFETのゲート電極を接
地電位にすることを特徴とする半導体集積回路。[Claims] 1. A semiconductor substrate has a wiring for supplying a first power supply potential V_C_C and a wiring for supplying a second power supply potential V_D_D,
The first power supply potential V_C_C is compared with a predetermined set potential V_S_W, and the comparison result is output as a control signal, and when the potential V_C_C is smaller than V_S_W, the power consumption is set to 10 μW or less. A V_C_C voltage detector having means for cutting current; and the control signal causes the potential V_C_C to be set to V_S.
and an amplifier that consumes power only when the power is greater than _W, and the amplifier drives a driver for supplying charge from the first power supply potential V_C_C to the second power supply potential V_D_D. integrated circuit. 2. In the semiconductor integrated circuit according to claim 1, a differential amplifier having a first current source is used as the amplifier, and the first current source is controlled by the control signal to operate the differential amplifier. A semiconductor integrated circuit characterized by controlling power consumption. 3. In the semiconductor integrated circuit according to claim 2, a potential V serving as a reference for the second power supply potential V_D_D
A semiconductor integrated circuit characterized in that a current flowing through a circuit that generates _R_E_F is controlled by the control signal. 4. The semiconductor integrated circuit according to claim 3, wherein a second PMOSFET is used as the driver, and means for electrically bringing the gate electrode of the second PMOSFET to a ground potential; The first power supply potential V_C_
A semiconductor integrated circuit characterized in that when C is smaller than the set potential V_S_W, the gate electrode of the second PMOSFET is brought to a ground potential by the control signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62285964A JPH01129769A (en) | 1987-11-12 | 1987-11-12 | semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62285964A JPH01129769A (en) | 1987-11-12 | 1987-11-12 | semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01129769A true JPH01129769A (en) | 1989-05-23 |
Family
ID=17698239
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62285964A Pending JPH01129769A (en) | 1987-11-12 | 1987-11-12 | semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01129769A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06295585A (en) * | 1991-08-19 | 1994-10-21 | Samsung Electron Co Ltd | Inside power supply voltage generating circuit |
JPH08211954A (en) * | 1995-02-08 | 1996-08-20 | Nec Corp | Voltage reduction circuit for power supply |
-
1987
- 1987-11-12 JP JP62285964A patent/JPH01129769A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06295585A (en) * | 1991-08-19 | 1994-10-21 | Samsung Electron Co Ltd | Inside power supply voltage generating circuit |
JPH08211954A (en) * | 1995-02-08 | 1996-08-20 | Nec Corp | Voltage reduction circuit for power supply |
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