JPH01129611A - Logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a logic circuit using a transmission gate (or transfer gate), the purpose is to reduce the number of elements and increase the speed. 1 transmission gate, a second transmission gate to which a second input signal is input, and a third input signal to input the first transmission gate;
and turning on one of the second transmission gates;
switching means for turning off the other;
It consists of an inverter to which both output signals of the transmission gate are supplied, or a normal multi-input logic gate that does not include a transmission gate.

[Industrial application field]

The present invention relates to a logic circuit, and particularly to a logic circuit using a transmission gate (hereinafter abbreviated as TG).

In order to construct a high-speed, highly integrated large-scale integrated circuit (LS1), it is necessary to configure the internal digital (binary) logic circuit group at high speed and with a small number of elements. .

[Conventional technology]

In the following explanation, a circuit based on positive logic will be described, but a circuit having a similar function for negative logic can also be considered.

Figure 14 shows the conventional exclusive OR circuit (FOR circuit) -
Example circuit diagram not shown. Q1 in the figure. Q3゜Q5~Q8. Q
l3 are P-channel MO8 type transistors, Q2.
Q4. Q9 to Q12 and Ql4 are each N channel MO
8 type transistor, Ql and Q2. Q3 and Q4. Ql3
and Ql4 each constitute a CMOS inverter.

This FOR circuit operates when input signals A and B are each at a high level (hereinafter referred to as "'H"), or when each is at a low level (hereinafter referred to as "'H").
Below ii L! ), the output signal Y is '
L”, one of A and B is “H” and the other is “L”
'', Y becomes 7/Hrr. That is, the logical formula of this FOR circuit becomes Y=A-B+A-B.

FIG. 15 is a circuit diagram of an example of a conventional exclusive NOR circuit (ENOR circuit), in which Q1, Q3. Q15~01g,
Ql3 is a P-channel MO8 type transistor.

Q2. Q4. Q19-Q22. Ql4 is an N-channel MO8 type transistor, and its logical formula is Y=A −8+
It is represented by A-B.

16 and 17 are conventional logic circuits corresponding to FIGS. 4 and 5, respectively, which will be described later. The logic circuit shown in FIG.
Channel MO8 type transistor Q23. Q24.
N-channel MO8 type transistor Q 25. Q2
6, and the logic circuit shown in FIG. 17 is obtained by adding an inverter 1 to the logic circuit shown in FIG.

In Fig. 16, input signals @A and B are both 11 L I
I's only one-stop transistor Q23. Q24 is on respectively.

Q25. Q26 is turned off, and the output signal Y becomes ``H''.
'', but in other cases Y becomes II L''.

That is, this logic circuit is a NOR circuit expressed by the logical formula Y-8.0.

The conventional logic circuit shown in FIG. 17 includes transistors Q24.
Since the inverter 1 is provided on the gate input side of Q25, the logical formula is expressed as Y-A.B, and the output signal Y is "only when the input signal A is Lr L II and B is "H". “I””.

18 and 19 are conventional logic circuits corresponding to FIGS. 6 and 7, which will be described later, respectively. The logic circuit shown in FIG. 18 is a P-channel MO3 type transistor Q27.028. N-channel MO8 type transistor Q29. Q30 and inverter 2, and the logic circuit shown in FIG.
This circuit is obtained by removing the inverter 2 from the logic circuit shown in FIG.

In the circuit shown in FIG. 18, when the input signal is 'H' and the input signal B is 'L', transistors Q27 and Q28 are turned off, transistors Q29 and Q30 are turned on, and the output signal Y is 'L'. However, for other combinations of input logic values, at least one of the transistors Q27 and 028 is on, and each of Q29 and Q30 is off, so the output signal Y becomes HTT.

Therefore, the logical formula of this logic circuit is expressed as Y=A+B.

Furthermore, in the conventional logic circuit shown in FIG. 19, the inverter 2 that inverts the input signal B is removed, so the logic equation becomes Y=A-B, which is a NANDAND circuit.

20 and 21 are conventional logic circuits corresponding to FIGS. 8 and 9 described later, respectively. The logic circuit shown in FIG. 20 is the output signal Y of the conventional logic circuit shown in FIG. Inverter 3 is installed on the transmission line, and the logical formula is Y=A+B
This is an OR circuit shown in .

Furthermore, since the conventional logic circuit shown in FIG. 21 is provided with an inverter 3 in the transmission path of the NAND AND circuit signal Y shown in FIG. It becomes an AND circuit.

FIG. 22 shows a conventional logic circuit corresponding to FIG. 12 described later, which is composed of two human-powered FOR circuits 4, 5, two human-powered NOR circuits 6, and an inverter 7, and receives input signal A.

For B, C, and D, the output signal Y goes to Y=A −B+.
A logic circuit represented by B + CD + CD is visualized.

Furthermore, FIG. 23 shows another example of a conventional logic circuit, and the first one described later.
It corresponds to the logic circuit shown in Figure 3, and the logic formula is Y= (A+
+8+)・A2・B2.

In FIG. 23, Q31. Q33. Q35~Q3
8 are P channel MO8 type transistors, Q32°Q34 . Q31.
Input signal 81 is supplied to the gate of Q32, and
The input signal B2 is supplied to the gates of Q33, Q34, which constitute the CMOS inverter, and the gates of Q38, Q34, which also constitute the CMOS inverter. Input signal A2 is supplied to the gate of Q42, and Q35. Input signal AI to each gate of Q39
is input.

The conventional logic circuits described above use field effect transistors (FETs) such as MO8 type transistors, but FETs such as MO8 type transistors are used.
TGs that utilize the bidirectional characteristics of ET (same electrical characteristics even if the source and drain electrodes are reversed) are not used, and TGs are used only as part of selectors and flip-flops, and are generally not used. It is not used in logic circuits. This is due to the fact that when switching signal paths using two or more sets of TGs, it is difficult to suppress the on/off timing between each TG to within an acceptable limit.

However, this problem can be solved by specifying the conditions for using TG to a circuit configuration that operates within predictable timing deviations, and if TG is used wisely, it can achieve high speed with fewer elements. A desired logic circuit can be constructed.

For example, FIG. 24 is a circuit diagram of an example of a conventional FOR circuit using TGs, in which inverters 8.9. N channel MO
8 type transistor Q43. Q45. P channel M
O8 type transistor Q44. Consists of Q46. Transistors Q43 and Q44 are first TGs that control switching of input signal B according to input signals A and A, and transistors Q45 and Q46 are first TGs that control switching of input signal B from inverter 9 according to input signals A and A. 2 T
It is G.

According to this circuit, when one of input signals A and B is "H" and the usage is "L It", an output of "H" is obtained, and when input signals A and B have the same logical value, it is An output of L 11 is obtained.

Also, FIG. 25 shows another conventional logic circuit using TG,
A full adder circuit is composed of an EOR circuit mainly composed of TG. In the same figure, Q50. Q52. Q54゜Q5
6. Q58. Q627i [Q63ha N channel/L
/MOS type transistor, Q51. Q53. Q
55. Q57. Q59゜Q60 and Q61 are P channel M OS! f'! Transistors 11 to 16 are inverters, A and B are input signals, CI is a carry input signal, S is a sum output signal, and co is a carry output signal. Input signal A is applied to each transistor Q50 to Q53. Q6o
, Q63 are input to control the switching, and the input signal B is supplied to the TG consisting of Q50 and Q51, while the polarity is inverted by the inverter 12 and the input signal B is inputted to control the switching of Q52 and Q51.
53, and is also supplied to the transistor Q61.
These are respectively supplied to the gates of ゜Q62.

In the carry calculation section, when both input signals A and B are "H", the carry output signal co becomes llHIt, and when both A and B are "lIt", the carry output signal co becomes llHIt.

is erased ("L"), and when A and B do not match, the carry output signal CO becomes the inverted carry input signal c■.

FIG. 26 is a circuit diagram of still another example of the conventional circuit, which constitutes one bit of a Manchester type pull-up adder. In the figure, Xj and Yj are input signals, Cj-1 is a Killerly input signal, Sj is an inverted ZAM output signal, Cj is a carry output signal, 17 to 21 are TGs, and 22 to 24 are inverters.

[Problem that the invention seeks to solve]

The conventional logic circuits shown in FIGS. 14 to 23 have problems in that they have a large number of elements and have slow switching speeds.

Furthermore, the conventional logic circuit shown in FIG. 24 has fewer elements and is faster than the conventional exclusive OR circuit shown in FIG. This is equivalent to a circuit in which the on-resistances of the two are connected in series and the diffused capacitances of the drain and source are connected, resulting in a problem that the waveform becomes dull and the speed decreases.Moreover, when the waveform becomes dull, the period during which the current flows There was also the problem that power consumption was large due to the long time.

Furthermore, the conventional logic circuit shown in FIG.
The input side of the circuit is positive logic, while the output side is negative logic, which poses a problem in that the circuit design is troublesome due to the mixture of logics.

Furthermore, in the conventional logic circuit shown in FIG. 26, in order to output the carry signal Cj of the required logic, the inverter 23.
As shown by 24, two stages are required, causing signal delay, and
There are problems in that the number of circuit elements increases and one more stage of inverter is required to obtain the required logic output Sj for the sum output inversion signal Sj.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a logic circuit that can realize a reduction in the number of elements and an increase in speed.

[Means for solving problems]

FIG. 1A shows a circuit diagram of the principle of the first invention described in claim 1. In the figure, TG1 and TG2 are the first. Second transmission gate (TG), I1, 12
is an inverter, A1. A2 and B are the first. 2nd and 3rd
is the input signal, and Y is the output signal.

TG1 and TG2 are supplied with input signals A1 and A2, respectively. Inverter ■2 is that person's J signal B and its output signal B
This constitutes a switching means that turns on one of TGI and TG2 and turns off the other.

The inverter 11 has both output terminals TG1 and TG2 connected to its input terminal.

Moreover, FIG. 18 shows a principle circuit diagram of the second invention described in claim 82. In the figure, the same components as in FIG. 1A are denoted by the same reference numerals, and the explanation thereof will be omitted. In FIG. 1B, 30 is an ordinary multi-input logic gate that does not include a transmission gate, and both output signals TG1 and TG2 are supplied to one input terminal of the gate.

That is, the second invention is characterized in that a normal multi-input logic gate 30 is used instead of the inverter 11 in the first invention.

[Effect]

It is well known that the above TG1 and TG2 have a structure in which the drains and sources of a P-channel FET and an N-channel FET are connected to each other. Here, the FFT used in the present invention is MOS (Metal 0x
ide Sem1conductor) FET system (NMO8, PMO8, 0MO8), MIS (Meta
l In5lator Sem1conductor
) FET system (FET using nitride film gate FET or other insulating film for gate junction), YES
(HEtal Sem1conductor) FET type (GaAs(Si)MESFET, High Electron Mobility Transistor (HEMT) etc.), the gate electrode and channel region are DC insulated, and the source,
It is a three-terminal element with bidirectional characteristics such that the electrical characteristics are almost the same even if the drain terminals are exchanged, and the channel impedance differs by about one order of magnitude or more when the gate input is OII and 1411+. It is an element having

In Figures 1A and 1B, input signal B is 118
When it is II, TGI is on and TG2 is off, so only the input signal A1 passes through TGl and is input to inverter ■1.
Alternatively, it is supplied to a conventional multi-input logic gate 30. Also,
When the input signal B is 'L'', TGI is off and Te2 is on, so only the input signal Δ2 passes through Te2 and is supplied to the inverter 11 or the normal multi-input logic gate 30.Inverter 11. Normal multi-input logic gate 30
is an output signal Y to which logic according to a predetermined logical formula is applied.
is taken out.

In other words, since either G1 or Te2 is always in the on state, the TG must be used so as not to generate a net that is internally floating (high impedance) in response to the combination of inputs.
Satisfies usage conditions.

Furthermore, the difference in the input timing to the gate terminals of TGl and Te2 is at most the delay time required for an inverter with a fanout of 1, and normally this delay time is the longest compared to the delay times in other logic circuits. Since it is short, this timing shift does not cause logic malfunction.

A typical multi-input logic gate 30 is a multi-input simple logic gate (ie, an OR circuit, a NOR circuit).

AND circuit, NAND AND circuit sum gate (to ND-O
R-inverter, 0R-AND-inverter), and multiplexer gate.

Therefore, like the inverter 11, this ordinary multi-input logic gate 30 has the characteristic of cutting off the DC component in its input signal. Therefore, the DC component in the output signal of TGI or Te2 is not generated in the output signal Y, and the signal propagation delay time due to the on-resistance of TG1 and Te2 can be made shorter than the delay time of one stage of inverter. Therefore, even if a plurality of circuits of the present invention are connected in series, waveform distortion hardly occurs, and high-speed logical operations are possible.

Further, in the circuit of the present invention, the inverters 11 and 12 and the normal multi-input logic gate 30 have the same logic, and positive logic and negative logic do not coexist.

In addition, in order to minimize the signal delay caused by the inverter 12 and the signal delay due to the increase in load associated with mutual wiring, it is necessary to
In SI design, etc., inverter ■2 is replaced with TG1 and Te2.
must be placed close to the gate terminal. For this purpose, it is desirable to define and use the entire circuit shown in FIGS. 1A and 1B as a logic cell so that it can be treated as one unified unit.

〔Example〕

2 to 9 are circuit diagrams of each embodiment of the first invention,
FIG. 12 and FIG. 13 show respective embodiments of the second invention. In each figure, the same components as in FIGS. 1A and 1B are designated by the same reference numerals, and their explanations will be omitted.

FIG. 2 shows a circuit diagram of the first embodiment of the present invention, in which an inverter 3 is provided on the transmission path of the input signal A to the input terminal of Te2. According to this embodiment, since the input signal A1 of TG1 is A and the input signal A2 of Te3 is A, the logical formula will be explained next with reference to FIG. 3 for a second embodiment of the present invention. This embodiment is characterized in that the inverter 4 is provided only on the transmission path of the input signal A of the TG1. Therefore, according to this embodiment, since the input signal A1 of TGl is A and the input signal A2 of Te2 is △, the logical formula is Y=A-B+A-B (2), and the two-man power ENOR circuit is realizable.

Next, a third embodiment of the present invention will be described with reference to FIG. In this embodiment, the input signal A1 of TG1 is fixed at a potential corresponding to "1" (that is, 'H') (in the C803 circuit, it is 0, for example +5V), and the input signal A2 of Te2 is fixed to A
It is characterized by the following points. Therefore, the logical formula of this embodiment is Y=A-B (3), and when the input signal B is "L", the inverted signal A of the input signal A is obtained, and when the input signal B is H", the input signal "'1''
It is possible to realize a logic circuit that can obtain an inverted signal II OII ("L") of ("H").

FIG. 5 is a circuit diagram of a fourth embodiment of the present invention, which is characterized in that the input signal A1 of TG1 is fixed to A, the input signal A2 of TG2 is fixed to "1", and Y = A -8 ( 4) A logic circuit expressed by the logical formula can be realized.

In addition, in Fig. 5, if input signals A and B are exchanged, Y-
A logic circuit expressed by the logical formula 8.B can be realized.

Next, a fifth embodiment of the present invention will be explained with reference to FIG.
The potential (0M0) corresponding to T (that is, “L”)
In the 8 circuit, fix it to V33F (e.g. oV), and
The feature is that the input signal A of TG2, 2 is set to A.

Therefore, according to this embodiment, the logical formula is Y=8 to B (5) It is expressed as

In addition, in Fig. 6, if input signals A and B are exchanged, Y
A logic circuit with the logical formula =A-t-B can be realized.

Next, a sixth embodiment of the present invention will be explained with reference to FIG.
This is a configuration in which O゛′ and A are swapped, and the logical formula is Y = A − B (6)
A two-person NAND circuit expressed as can be realized.

Next, a seventh embodiment of the circuit of the present invention will be described with reference to FIG. In this embodiment, the input signal A1 of the TGI is set to 0", T
The feature is that the input signal A2 of G2 is 8. That is, the input signal A is phase-inverted by the inverter 5 and then input to the TG2.

According to this embodiment, the logical formula is Y = A -1-B (
7), and it is possible to realize a two-person OR circuit.

Next, an eighth embodiment of the present invention will be described with reference to FIG. 9. In this embodiment, the TGI input signal Δ1 is set to K.

It is characterized in that the input signal of TG2 is fixed at the potential of logic N 1 II, and an inverter □6 is provided in the input signal transmission path of TGI of the fourth embodiment shown in FIG. .

The logical formula of this example is Y=A −B ■,
A two-person AND circuit can be realized.

By the way, in the logic circuits shown in FIGS. 4, 5, and 9, the input signal of TGI or TG2 is fixed at logic "1". On the other hand, as shown in FIG. 10(A), the input signal of TG consisting of P-channel FET Pl and N-channel FET N1 is logic it 1 t+, input signal B is applied to the gate of Pl, and an inverter is applied to the gate of N1. A circuit to which output signal B of I7 is applied generally includes an inverter 7 and an FET, as shown in FIG. 10(B).
It is possible to replace Nl with a circuit in which each of them is omitted.

Therefore, TG1 shown in FIG. 4 and TG2 shown in FIGS. 5 and 9 may each be configured with only one P-channel FET. However, since the inverter 12 is necessary to control another TG2 or TGl, it cannot be deleted. Therefore, the number of elements in this case is 118I in the logic circuits of FIGS. 4, 5, and 9.
I 711 , 117 u and '9'', which are one less than I , 113'' and 'io' (since the inverters 11 and 12 are composed of CMOS inverters, the number of elements is II 2 II each). ).

Similarly, as shown in N11 diagram (A), FETP1 and N1
Fixedly input a logic “0” signal to the TG consisting of
N1 is input signal B, and P is output signal RB of inverter ■8.
As shown in the same figure (B), the circuit that controls
It can be replaced with channel FET N1.

Therefore, each TGI shown in FIGS. 6 and 8 can be replaced with one N-channel FET, and the TG2 shown in FIG.
can be replaced with one N-channel FET. Therefore, the number of elements in the logic circuit in this case is "8", 8" and It 10 PI
each one less than Id 7 u , 11711
and 119 II.

Next, a ninth embodiment of the present invention will be described with reference to FIG. 12. In this embodiment, instead of the inverter 11, a normal two-man NAND game 1-
In addition, one circuit section is connected to each of the two input terminals of the NAND gate in the logic circuit shown in FIG. 2, except for the inverter (1).

In FIG. 12, a signal expressed by a logical formula B+λ stone extracted from a circuit section consisting of TGla, TG2a, and inverters 12a and 13a is supplied to each gate of a P-channel transistor Tr1 and an N-channel transistor Tr3. . - direction, TGlb, TG2b,
A signal expressed by the logical formula C-D+Te·100 taken out from the circuit section consisting of inverters 12b and I3b is supplied to each gate of P-channel 1 helangistor Tr2 and N-channel transistor Tr4.

The transistors Tr1 to Tr4 constitute a NAND gate, which outputs a logic "O" signal only when the input logic of each gate of the transistors Tr1 to Tr4 is 11111, and outputs a logic "O" signal for other input logic combinations. is logic”
i” signal is output.

As a result, from the common connection point of the transistors Tr1 to Tr3, the following logical formula Y = A −B +A −B −1−C−D + C
An output signal Y represented by -D (9) is taken out.

Next, a tenth embodiment of the present invention will be described with reference to FIG. 13. In this embodiment, in place of the inverter (1), a normal two-man power NOR gate consisting of transistors Tr5 to Tr8 is used, and the inverter (1) in the logic circuit shown in FIG. 6 is connected to each of the two input terminals of the NOR gate. The circuit sections except for the inverter 11 in the logic circuit shown in FIG. 5 are connected. However, in this embodiment, the circuit section corresponding to TGla uses one N-channel [ETN1] as shown in FIG. 11(B), and the circuit section corresponding to TG2b uses the circuit section shown in FIG. 10(B). One P-channel FET P1 is used as shown in FIG.

In FIG. 13, the logical formula (At ・B+ ) taken out from the circuit section consisting of TG2a, N1 and T2a
An output signal NR1 represented by is supplied to each gate of a P channel transistor Tr6 and an N channel transistor Tr7. Also T G Ib.

A signal NR2 expressed by the logical formula (A2 + B2) extracted from the circuit section consisting of Pl and 12b is supplied to each gate of the P-channel transistor Tr5 and the N-channel transistor Tr8.

The transistors Tr5 to Tr8 are activated only when the signals NR1 and NR2 are both logic 410 II.
and Tr6 are turned on, and the transistor Tr
7 and Tr8 are turned off at the same time, so logic ""1
" signal Y is taken out from the common connection point of transistors Tr6 to Tr8. Otherwise, at least one of transistors Tr7 and Tr8 is on, and at least one of transistors Tr5 and Tr6 is off, so the logic "0" is taken out from the common connection point of transistors Tr6 to Tr8. Outputs the belief @Y of °'.

Therefore, the transistors Tr5 to Tr8 form a NOR gate, and the output signal is expressed by the following logical formula Y = (At +
B+ ) ・(A2 ・B2) (10)

Next, simulation results of the delay times of the respective embodiments of the present invention described above and the corresponding conventional logic circuits shown in FIGS. 14 to 23 will be described. here,
The delay time of a logic circuit varies depending on the magnitude of the load capacitance attached to the output terminal of the circuit, and usually a linear relationship is established between the circuit delay and the magnitude of the load capacitance. The magnitude of the load capacity 1 is described in fanout (FO) as a unit, and the circuit's extension equation is % formula (11). However, the delay times of the 762 circuit a, b: constants that do not depend on fanout FO: fanout The delay time τd of the circuit with load can be calculated from the normalized number with the input gate capacitance of the inverter as 1.

Therefore, 00MO81, 3μm technology, 0MO8
The width of all FETs is the same. ■The capacitance attached to each terminal of the circuit is the wiring capacitance (unchanged between terminals), the input capacitance of the first stage logic gate (gate capacitance, gate overlap capacitance), and the source-drain junction capacitance. The results of delay time simulation under the condition that the logic circuit consists of the following are summarized in FIG. 27, together with the logical formula of the logic circuit, the figure number showing the logic circuit, and the effects of the embodiment. However, in Figure 27, *1
indicates the case where FO=1, and *2 indicates the case where FO=7.

As can be seen from FIG. 27, the first embodiment of the present invention shown in FIGS. 2 and 3. According to the second embodiment, the number of elements is smaller than the conventional circuit shown in FIGS. 14 and 15, and when FO=1, the delay time is small (high speed), and as the number of FO increases, the speed increases. The difference becomes more pronounced.

In addition, the third section shown in FIG. 4 and FIG. In the fourth example,
The number of elements is larger than that of the conventional circuit shown in Figs. 16 and 17, and when FO = 1, the delay time is equal to or slightly longer than the conventional circuit, but as shown in Fig. 27, in the case of FO-7, This example was faster.

In addition, 5. shown in FIGS. 6 and 7. The sixth embodiment is slower than the conventional circuits shown in FIGS. 18 and 19, but when there are more FOs, it is faster than the conventional circuit by 1q. Also, even if the circuit itself is slower than the conventional circuit, it may become faster when combined with other circuits.

Figure 13 is an example of this.
As shown in figure 1c, the same logical formula Y-(A+ +B+)・A2
・Delay time of B2 conventional circuit 2.32 nsJ: Rimo 0
．． A delay time of 1.98 ns, which is 34 ns shorter, was obtained.

As described above, in each embodiment of the present invention, the value of a in equation (11) is smaller than that of the conventional logic circuit, and the fan-out number FO
Although it is slower than the conventional circuit when there are few FOs, it becomes faster when there are many FOs.

By the way, when designing the layout of an LSI such as a standard cell type or gate array using the multi-input logic circuits of the above-mentioned embodiments, at least one of them is registered as a standard logic cell, and other similar logic cells are registered. It is desirable to use and design it as necessary in conjunction with registered logic cells.

Note that the present invention is not limited to the above embodiments, and for example, as a normal multi-input logic gate, NΔND,
Not limited to each gate of NOR, but also OR.

It may be a simple gate with multiple inputs such as AND, or a complex gate. Further, it is sufficient that the circuit section of the main part of the present invention is connected to at least one input terminal among the plurality of input terminals of the multi-input logic gate.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to reduce the number of elements and increase the speed by using it as at least a partial circuit in a large-scale circuit, and by using an inverter provided at the output stage or an ordinary multi-input logic gate. Since the DC component is blocked,
Even when multiple circuits of the present invention are connected in cascade, there is almost no waveform distortion, which enables high-speed logic operations and reduces power consumption.Furthermore, since positive logic and negative logic are not mixed, the circuit It has the advantage of being easy to recruit.

[Brief explanation of the drawing]

1A and 1B are principle circuit diagrams of the first and second inventions, respectively; FIGS. 2 to 9, 12, and 13 are circuit diagrams showing respective embodiments of the present invention; 10 and 11 are diagrams showing modified examples of each main part of the present invention, FIGS. 14 to 26 are circuit diagrams showing respective conventional circuits, and FIG. 27 is a diagram showing each embodiment of the present invention. A comparison diagram with a conventional example is shown. In the figure, TGl is the first transmission gate, TG2 is the second transmission gate, 11 to I8.12
a, 12b, 13a, and 13b represent the first input signal of the inverter A1, A2 the second input signal, B the third input signal, and 30 a normal multi-input logic gate. ＾Noku 9 Bell lid ()

Claims (2)

[Claims] (1) A first transmission gate (TG1) to which the first input signal (A1) is input, a second transmission gate (TG2) to which the second input signal (A2) is input; Turn on one of the first and second transmission gates (TG1, TG2) by the input signal (B) of No. 3;
switching means (12) for turning off the other; said first and second transmission gates (TG1);
, TG2) to which the inverter (11
), and a logic circuit characterized by the following. (2) a first transmission gate (TG1) to which the first input signal (A1) is input; a second transmission gate (TG2) to which the second input signal (A2) is input; Turn on one of the first and second transmission gates (TG1, TG2) by the input signal (B) of No. 3;
switching means (12) for turning off the other; said first and second transmission gates (TG1);
, TG2) are supplied to at least one of its input terminals, and outputs an output signal (Y) having a predetermined logic value. A logic circuit characterized by: