JPH01129359A - Computing element and its driving method - Google Patents

Abstract

PURPOSE:To execute an algorithm, which execute a signal processing, at a high speed by providing a second register, which temporarily stores an accumulated result in the half of computation, separately from a first register, which is always used for the accumulating computation and stores the result of the computation, and totally adding the contents of those registers. CONSTITUTION:A first partial product is computed with a first mode and a same value is stored to the first register 11 and the second register 12 respectively. Next, in the computation of a second partial product, a second mode is obtained and the first register 11 is reset. Then, the partial product is computed and the second register 12 still stores the first value by an input and output prohibiting instruction. The computation of a third partial product is also executed with the second mode samely, however, the third mode is executed in a first step. Namely, the first partial product stored in the the first register 11 and the second partial product accumulated in the second register 12 are added and accumulated in the second register 12. By repeating this operation, a time to be needed for an (M+1)/2-number of addition can be removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an arithmetic unit that has a register for temporarily storing accumulated results and that improves the speed and efficiency of signal processing, and a method for driving the arithmetic unit.

[Conventional technology]

Accumulation is an operation that adds and stores an input signal and the result of addition up to that point, and is one of the important operations, along with multiplication, in the field of digital signal processing. Figure 2 shows
This is a conventional example of an arithmetic unit that performs accumulation. This arithmetic unit includes an adder circuit 15. Register 16° input signal line 5. Adder circuit output signal line 7. It consists of a register output signal line 6.

According to this arithmetic unit, an input signal transmitted from an input signal line 5 and the stored contents of a register 16 transmitted from a signal line 6 are added in an adder circuit 15, and the result is inputted to a register 16 through a signal line 7 and stored. do. By repeating this operation, signals input in time series can be accumulated.

[Problem that the invention seeks to solve]

However, in recent years, studies on high-speed algorithms for signal processing have progressed, and it has become difficult to realize high-speed and efficient algorithms using only the conventional accumulation function.

FIR (fin
This will be explained using filtering (item impulse response) as an example. Here, it is assumed that the multiplication function and the accumulation function are operated in a vibrating manner to perform a sum-of-products operation. FIR filtering with weighting coefficients for MXM pixels can be expressed by equation (1).

y (u, v) ... (1) where = (M-1)/2 (M is an odd number),
y (u, v) is the output at point (u, v), (h(i
, j)) are weighting coefficients, and (x (u, v)) is the input image signal.

However, if formula (1) is implemented as is, MXM product-sum operations are required for each pixel.

Therefore, a method has been devised to speed up the algorithm (1) (2) by utilizing the symmetry of the weighting coefficients of FIR filtering (Japanese Patent Application No. 59-262031).

"2-dimensional digital filter"). In this method, first,
The sum of partial products Cu+V is determined as follows.

... (2) Due to the symmetry of the weighting coefficients, h (-i, j) = h (i.

j), so C'u-2i+v=C-'utv --
・(3) becomes. Therefore, by using (2) and (3) 2, equation (1) is transformed into (4) 2.

・ ・ ・ (4) Here, the first term of equation (4) is already calculated when calculating the output of 21 pixels before, so there is no need to calculate it, and the sum of products operation can be reduced to about 1/2. .

However, the problem is 2xk=M-1 additions. By eliminating this number of additions, true speed-up can be achieved. However, conventional arithmetic units cannot eliminate this addition and cannot fully utilize the high speed of the algorithm.

SUMMARY OF THE INVENTION An object of the present invention is to provide an arithmetic unit and a driving method thereof that can solve the conventional problems and perform complex signal processing using accumulation at high speed.

[Means for solving problems]

An arithmetic unit according to a first aspect of the present invention includes: an adding circuit; a first selector that selects one signal from an output signal of the adding circuit and an external input signal; and storing an output signal of the first selector. a first register whose stored contents are used as a second input signal of the adder circuit; a second register which stores an output signal of the adder circuit and supplies the stored contents to a second selector; A second selector selects one signal from among the output signals of the two registers and the external input signal, and sets the selected signal as the first input signal of the adder circuit.

A second invention includes: an adding circuit; a first selector that selects one signal from an output signal of the adding circuit and an external input signal; and storing an output signal of the first selector; a first register which takes as the second input signal of the adder circuit; a second register which stores the output signal of the adder circuit and supplies the stored contents to a second selector; In a method for driving an arithmetic unit, the method includes a second selector that selects one signal from an output signal and the external input signal and sets it as a first input signal of the addition circuit, in a first mode, The first selector selects the output signal of the adder circuit, and the first register.

Both second registers accumulate the output signals of the adder circuit, and the second selector selects the external input signal and supplies it to the adder circuit; the first register selects the output signal of the adder circuit, the first register accumulates the output signal of the adder circuit, and the second register retains the memory contents up to that point according to a manual prohibition instruction; A second selector selects the external input signal and supplies it to the addition circuit, and in a third mode, the first selector selects the external input signal and writes it in the first register. At the same time, the adder circuit receives the output signal of the first register,
It is characterized in that the output signals of the second register are added.

[Effect]

The principle of the present invention is that, in addition to the first register that is always used for cumulative calculations and stores the results, the arithmetic unit that performs the cumulative calculations has a second register that temporarily stores the partial results of the cumulative calculations. By adding the contents at once, the algorithm for signal processing can be executed at high speed.

The high-speed algorithm for FIR filtering described in the conventional example divides M2 product-sum operations into M parts, and uses the M partial products for addition in the next process.

In order to calculate and store each of the M-divided values, it is necessary to reset the accumulator each time the M-divided values are calculated, and the accumulated results up to that point are lost each time. Therefore, by always saving and storing the accumulated results in the second register until the reset, the algorithm can be executed at high speed without losing the calculation results.

〔Example〕 Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an arithmetic unit according to the first invention. Since the second invention is a method for driving the arithmetic unit of the first invention, an embodiment of the second invention will be described below along with a detailed description of the first invention.

The arithmetic unit in FIG. 1 includes a first selector 13. First register 11. Second selector 17. Second register 12° adder circuit 14. External input signal line 1. First input signal line 9. Second
Input signal line 3. Output signal of adder circuit 144. First selector output signal line 10. It consists of the output signal line 8 of the second register.

The first selector 13 selects one signal from the output signal of the adder circuit 14 and the external input signal.

The first register 11 stores the output signal of the first selector 13 and outputs the stored contents as the second input signal of the adder circuit 14.

The second register 12 stores the output signal of the adder circuit 14 and supplies the stored contents to the second selector 17.

The second selector 17 selects one signal from the output signal of the second register 12 and the external input signal, and outputs it as the first input signal of the adder circuit 14 .

The adder circuit 14 adds the first input signal and the second input signal.

Next, a method of driving the arithmetic unit shown in FIG. 1 will be explained.

The first mode is a normal accumulation mode, and the first selector 13 selects the signal on the output signal line 4 of the adder circuit 14 and supplies it to the first register 11. The second register 12 is also
Storing the signal on the output signal line 4 of the adder circuit 14 - At this time, the second selector 17 selects the external input signal line 1 and does not affect the addition operation of the adder circuit 14. In this first mode, the signals input from the input signal line 1 are accumulated one after another, and the results are stored in the first register 17. The data is stored in the second register 12.

The second mode is a mode for holding the accumulated results up to the middle,
The first selector 13 selects the adder circuit 4 as in the first mode.
The signal on the output signal line 4 is selected and supplied to the first register 11. The second register 12 prohibits input by an input prohibition instruction, and holds the accumulated results up to that point. At this time, the second selector 17 selects the external input signal line 1 and does not affect the addition operation of the addition circuit 14. This second mode makes it possible to perform accumulation in the first register 11 while holding intermediate accumulation results in the second register I2.

In the third mode, the accumulation result of the first register 11 and the second
This is a total addition mode in which the accumulated results of the registers 12 are added all at once. The first selector 13 selects the signal on the external input signal line 1 and stores it in the first register 11 . At the same time, the output signal of the first register 11 and the output signal of the second register 1
The two output signals are added together by the adder circuit 14 and output to the output signal line 4. At this time, the signals on the external input signal line 1 are not added by the addition circuit 14 due to the addition prohibition command.

When executing the high-speed FIR filtering algorithm described in the conventional example, M2 product-sum operations are divided into M parts, M partial products are calculated, and (M-1) 72 of them are used for later processing. and the remaining (M+1) 72 pieces are used for addition. According to the present invention, these (M+1) 72 additions can be eliminated and processing speed can be increased. Specifically, this procedure is described in steps 1 and 2. This will be explained using the third mode.

First, in the first mode, calculate the first partial product, and
The same value is stored in each of the registers IL and the second register I2. Next, in the calculation of the second partial product, the second mode is set, the first register 11 is reset, the partial product is calculated, and the second register 12 is set to the first value by the input/output prohibition instruction. remains stored. The third partial product is calculated in the same way in the second mode, but
The third mode is performed in the first step. In other words,
The first partial product stored in the first register 11 and the second partial product stored in the second register 12 are added and stored in the second register 12. By repeating this operation, the time required for (M+1)72 additions can be eliminated.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an arithmetic unit and a driving method thereof that can perform accumulation of regular signal processing algorithms such as FIR filtering at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the first invention of the present application, and FIG. 2 is a block diagram showing a conventional example. 1...External input signal line 3...Second input signal line 4...Addition circuit output signal line 5...Input signal line 6.8...Register output Signal line 7...Adder circuit output signal line 9.10...Selector output signal line 11...First register 12...Second register 13... First selector 14, 15...Addition circuit 16...Register 17...Second selector agent Yoshiyuki Iwasa, patent attorney

Claims (2)

[Claims] (1) an adder circuit; a first selector that selects one signal from the output signal of the adder circuit and an external input signal; and stores the output signal of the first selector and adds the stored contents to the adder; a first register that serves as a second input signal of the circuit; a second register that stores the output signal of the adder circuit and supplies the stored contents to a second selector; and an output signal of the second register. and a second selector that selects one signal from the external input signals and sets it as the first input signal of the adder circuit. (2) an adder circuit; a first selector that selects one signal from the output signal of the adder circuit and an external input signal; and stores the output signal of the first selector and adds the stored contents to the adder; a first register that serves as a second input signal of the circuit; a second register that stores the output signal of the adder circuit and supplies the stored contents to a second selector; and an output signal of the second register. and a second selector that selects one signal from the external input signals and sets it as the first input signal of the addition circuit, in the first mode, the first A selector selects the output signal of the adder circuit, the first register and the second register both accumulate the output signal of the adder circuit, and the second register selects the output signal of the adder circuit.
a selector selects the external input signal and supplies it to the addition circuit; in a second mode, the first selector selects the output signal of the addition circuit; and the first register selects the output signal of the addition circuit; The output signals of the circuit are accumulated, the second register retains the stored contents up to that point by an input prohibition instruction, and the second selector selects the external input signal and supplies it to the addition circuit. , in the third mode, the first selector selects the external input signal and stores it in the first register;
A method for driving an arithmetic unit, wherein the adder circuit adds an output signal of the first register and an output signal of the second register.