JPH01128897A - Semiconductor ic device - Google Patents
Semiconductor ic deviceInfo
- Publication number
- JPH01128897A JPH01128897A JP62288027A JP28802787A JPH01128897A JP H01128897 A JPH01128897 A JP H01128897A JP 62288027 A JP62288027 A JP 62288027A JP 28802787 A JP28802787 A JP 28802787A JP H01128897 A JPH01128897 A JP H01128897A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- lead frame
- leads
- mounting pieces
- reliability
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 229920005989 resin Polymers 0.000 claims abstract description 31
- 239000011347 resin Substances 0.000 claims abstract description 31
- 230000003014 reinforcing effect Effects 0.000 claims abstract description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052751 metal Inorganic materials 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims abstract description 8
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 8
- 239000010703 silicon Substances 0.000 claims abstract description 8
- 238000000465 moulding Methods 0.000 abstract description 12
- 238000000034 method Methods 0.000 abstract description 2
- 238000003754 machining Methods 0.000 abstract 2
- 230000005855 radiation Effects 0.000 abstract 1
- 230000008719 thickening Effects 0.000 abstract 1
- 238000012545 processing Methods 0.000 description 8
- 238000012360 testing method Methods 0.000 description 7
- 238000007789 sealing Methods 0.000 description 5
- 235000012431 wafers Nutrition 0.000 description 5
- 230000035939 shock Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 241000209219 Hordeum Species 0.000 description 2
- 235000007340 Hordeum vulgare Nutrition 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000001721 transfer moulding Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 229910018499 Ni—F Inorganic materials 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 239000004695 Polyether sulfone Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004734 Polyphenylene sulfide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000748 compression moulding Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000000178 monomer Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920002492 poly(sulfone) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920006393 polyether sulfone Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000069 polyphenylene sulfide Polymers 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Credit Cards Or The Like (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
［技術分野１
本発明は、ＩＣカードなどに組み込んで用いられる薄型
の半導体ＩＣ装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field 1] The present invention relates to a thin semiconductor IC device that is incorporated into an IC card or the like.
［背景技術］
ＩＣカードなどに組み込んで使用する半導体ＩＣ装置は
薄く形成することが要求されるものであり、従来から例
えば第３図に示すようにプリント配線板１１を基板とし
、これにＩＣチップ１を実装すると共に封止ｔＭ脂１２
で封止することによって製造されたものが提供されてい
る。しかしこのものでは、スルーホール１３の加工やＩ
Ｃチップ１を搭載する凹所１４の座ぐり加工、ＩＣチッ
プ１とスルーホール１３とを導通させる回路１５の形成
、ＩＣＣチップの搭載及びＩＣチップ１と回路１５との
間のワイヤー２２のボンディング、など多くの製造工数
を必要とするという問題があり、また外部に露出させる
端子１６はプリント配線板１１に積層される銅箔とその
表面のわずかのメツキ層によって形成されることになり
、この端子１６への接点の作用頻度が多（なると摩耗さ
れ易く、外部への接続の信頼性に問題が生じるおそれが
ある。さらにＩＣチップ１はプリント配線板１１に搭載
された状態で封！ヒ樹脂１２内に封入されてぃるだめに
、ＩＣチップ１の発熱が封止樹脂１２内にこもってしま
うという問題もある。[Background Art] Semiconductor IC devices used by being incorporated into IC cards and the like are required to be formed thinly. Conventionally, for example, as shown in FIG. 3, a printed wiring board 11 is used as a substrate, and an IC chip is mounted on this. 1 and sealing tM resin 12
Products manufactured by sealing with However, with this one, processing of through hole 13 and I
Countersinking of the recess 14 in which the C chip 1 is mounted, formation of the circuit 15 that connects the IC chip 1 and the through hole 13, mounting of the ICC chip, and bonding of the wire 22 between the IC chip 1 and the circuit 15, In addition, the terminals 16 exposed to the outside are formed by the copper foil laminated on the printed wiring board 11 and a small plating layer on the surface of the copper foil. If the contacts to 16 act frequently (if so, they will be easily worn out and there is a risk of problems with the reliability of external connections.Furthermore, while the IC chip 1 is mounted on the printed wiring board 11, it is sealed with resin 12). There is also the problem that the heat generated by the IC chip 1 is trapped in the sealing resin 12 because the IC chip 1 is not sealed inside.
［発明の目的１
本発明は、上記の点に鑑みて為されたものであり、加工
工数を低減することができ、また端子の摩耗による外部
への接続の信頼性に問題が生じるおそれがなく、さらに
ＩＣチップの放熱性に優れ、加えてＩＣチップの保護に
優れると共にＩＣチップとリードとの間の導通信頼性を
高めることができる半導体ＩＣ装置を提供することを目
的とするものである。[Objective of the Invention 1] The present invention has been made in view of the above points, and it is possible to reduce the number of processing steps, and there is no risk of problems occurring in the reliability of external connections due to terminal wear. Furthermore, it is an object of the present invention to provide a semiconductor IC device which has excellent heat dissipation properties of an IC chip, which is also excellent in protection of the IC chip, and which can improve the reliability of conduction between the IC chip and the leads.
［発明の開示１
しかして本発明に係る半導体ＩＣ装置は、線膨張係数が
３ Ｘ １０−６／℃〜１．８ Ｘ １０−５／”Ｃの
金属リードフレーム２の複数本の各リード３，３・・・
にチップ搭載片５を形成すると共にチップ搭載片５の肉
厚をリード３の他の部分の厚みよりも厚く形成し、この
各チップ搭載片５の片側表面にシリコンウェハーで形成
されるＩＣチップ１を搭載して直接実装すると共にリー
ドフレーム２に設けた補強片７をＩＣチップ１に添わせ
、ＩＣチップ１をリー・ド３及び補強片７とともに成形
樹脂４内に封入し、成形樹脂４の表面にチップ搭載片５
の他方の片側表面を露出さ゛せで成ることを特徴とする
ものであり、以下本発明を実施例により詳述する。DISCLOSURE OF THE INVENTION 1 The semiconductor IC device according to the present invention has a linear expansion coefficient of 3 x 10-6/°C to 1.8 x 10-5/"C, each of the plurality of leads 3 of the metal lead frame 2. ,3...
A chip mounting piece 5 is formed on the chip mounting piece 5, and the thickness of the chip mounting piece 5 is formed to be thicker than the thickness of other parts of the lead 3, and an IC chip 1 formed of a silicon wafer is formed on one surface of each chip mounting piece 5. At the same time, the reinforcing piece 7 provided on the lead frame 2 is attached to the IC chip 1, and the IC chip 1 is encapsulated together with the leads 3 and the reinforcing piece 7 in the molded resin 4. Chip mounting piece 5 on the surface
The invention is characterized in that the other one side of the surface is left exposed.The present invention will be described in detail below with reference to Examples.
リードフレーム２は４２アロイ（Ｎｉ４２％のＮｉ−Ｆ
ｅ合金）などの金属帯板をプレス加工などすることによ
って形成されるものであり、第２図に示すように左右一
対のフレーム１７．１７を連結片１８で接続して長尺に
形成しである。隣合う連結片１８．１８間の部分が半導
体ＩＣ装置を作成するための一つの単位となるものであ
り、この各隣合う連結片１８．１８間の部分においてそ
れぞれ７レーム１７，１７から複数本づつリード３．３
・・・が延出しである。この各リード３の先部は屈曲部
１９及び幅広のチップ搭載片５として形成しである。リ
ードフレーム２において７レーム１７やリード３は同じ
厚みに形成されるが、チップ搭載片５はその肉厚をリー
ド３の他の部分よりも厚く（例えば１．２〜５倍程度）
形成するようにしである。Lead frame 2 is made of 42 alloy (42% Ni-F)
It is formed by pressing a metal strip such as e-alloy), and is formed into a long piece by connecting a pair of left and right frames 17 and 17 with a connecting piece 18, as shown in Figure 2. be. The portion between adjacent connecting pieces 18.18 becomes one unit for making a semiconductor IC device, and in the area between each adjacent connecting piece 18.18, a plurality of 7 frames 17, 17 are formed. Lead 3.3
...is an extension. The tip of each lead 3 is formed as a bent portion 19 and a wide chip mounting piece 5. In the lead frame 2, the seven frames 17 and the leads 3 are formed to have the same thickness, but the chip mounting piece 5 is thicker than other parts of the leads 3 (for example, about 1.2 to 5 times).
It is like forming.
また、各リード３．３の開において左右の７レーム１７
．１７開に細い補強片７が一体に設けである。第２図に
おいて２３はリードフレーム２を自動送りするために７
レーム１７に形成した送り孔である。Also, in the opening of each lead 3.3, 7 frames 17 on the left and right
．． A thin reinforcing piece 7 is integrally provided at the 17 opening. In FIG. 2, 23 is 7 for automatically feeding the lead frame 2.
This is a feed hole formed in the frame 17.
このリードフレーム２を用いて半導体ＩＣ装置を製造す
るのであるが、まずＩＣチップ１の実装をおこなう。Ｉ
Ｃチップ１の実装は第２図に鎖線で示すように各チップ
搭載片５，５・・・の上面にＩＣチップ１を直接重ね、
ワイヤーレスで搭載する直接実装によっておこなう。こ
の直接実装としては例えば７リツプチツプ実装でおこな
うことがで外る。すなわち、ＩＣチップ１の電極に半田
などのバンブ２０を形成し、このバンプ２０とチップ搭
載片５とを半田付は接合するのである。このように直接
実装することによって、リード３へのＩＣチップ１の固
定と電気的接続とを同時におこなうことができることに
なる。またこのようにＩＣチップ１を実装した状態にお
いて、リードフレーム２に設けた補強片７はＩＣチップ
１の下側に添うように位置している。そしてこのように
ＩＣチップ１を搭載したのちに成形をおこない、ＩＣチ
ップ１を各リード３及び補強片７とともに成形樹脂４内
に埋入して封止する。この成形は長尺の１７ ＋上フレ
ーム２を連続的にトランスファー成形装置や圧縮成形装
置などに送り込むことによっておこなうことができる。A semiconductor IC device is manufactured using this lead frame 2. First, the IC chip 1 is mounted. I
To mount the C chip 1, place the IC chip 1 directly on top of each chip mounting piece 5, 5, etc. as shown by the chain line in FIG.
This is done by direct mounting wirelessly. This direct mounting can be carried out, for example, by 7-lip chip mounting. That is, a bump 20 made of solder or the like is formed on the electrode of the IC chip 1, and the bump 20 and the chip mounting piece 5 are joined by soldering. By directly mounting in this way, it is possible to simultaneously fix the IC chip 1 to the leads 3 and make electrical connections. Further, in the state in which the IC chip 1 is mounted in this manner, the reinforcing piece 7 provided on the lead frame 2 is positioned along the lower side of the IC chip 1. After mounting the IC chip 1 in this manner, molding is performed, and the IC chip 1 is embedded together with each lead 3 and reinforcing piece 7 in the molding resin 4 and sealed. This molding can be carried out by continuously feeding the long 17+ upper frame 2 into a transfer molding device, a compression molding device, or the like.
またこの成形に用いる樹脂としては特に限定されるもの
ではないが、フェノール、エポキシ、シリコン、ポリイ
ミドなどの熱硬化性樹脂、ポリフェニレンサルファイド
、ポリサル７すン、ポリエーテルスルホン、ポリアリ−
ルスルホンなどの熱可塑性樹脂を用いることができる。The resins used for this molding are not particularly limited, but include thermosetting resins such as phenol, epoxy, silicone, and polyimide, polyphenylene sulfide, polysulfone, polyether sulfone, and polyaryl.
Thermoplastic resins such as lusulfone can be used.
このように成形して成形樹脂４にＩＣチップ１とリード
３，３・・・とを討入するにあたって、チップ搭載片５
の裏側の面を第１図に示すように成形樹脂４の下側の表
面から露出させるようにしてあり、このチップ搭載片５
の露出面で外部への接続端子６が形成されるようにしで
ある。ここでチップ搭載片５は肉厚が厚く形成しである
ために、肉厚を厚くした寸法分ＩＣチップ１の下面と成
形樹脂４の下面との間の距離を太き（することができ、
すなわちＩＣチップ１の下側の成形樹脂４の厚みｔを大
きく確保することができることになり、封止によるＩＣ
チップ１の保護効果を高めることができる。またこのよ
うにＩＣチップ１の下側の成形樹脂４の厚みｔを大きく
確保できるために、補強片７の全体を確実に成形樹脂４
に埋入させることもできることになる。そして各リード
３，３・・・を７レーム１７から切り離すことによって
、リードフレーム２から第１図のように形成される半導
体ＩＣ装置Ａを得ることができる。When molding the IC chip 1 and the leads 3, 3, etc. into the molded resin 4 by molding in this way, the chip mounting piece 5
The back side of the chip mounting piece 5 is exposed from the lower surface of the molded resin 4 as shown in FIG.
A connecting terminal 6 to the outside is formed on the exposed surface of the holder. Here, since the chip mounting piece 5 is formed to have a thick wall, the distance between the lower surface of the IC chip 1 and the lower surface of the molded resin 4 can be increased by the increased wall thickness.
In other words, it is possible to ensure a large thickness t of the molding resin 4 on the lower side of the IC chip 1, which allows the IC to be sealed by sealing.
The protection effect of the chip 1 can be enhanced. In addition, since the thickness t of the molded resin 4 on the lower side of the IC chip 1 can be ensured large in this way, the entire reinforcing piece 7 can be reliably covered with the molded resin 4.
This means that it can also be embedded in Then, by cutting each lead 3, 3, . . . from the seven frames 17, a semiconductor IC device A formed as shown in FIG. 1 can be obtained from the lead frame 2.
このように形成される半導体ＩＣ装置Ａにあって、ＩＣ
チップ１はリードフレーム２のリード３に接続されてい
るために、プリント配線板１１を基板として用いる第３
図の従来例のようにスルーホール加工や回路加工などを
するような必要はなく、またＩＣチップ１は直接実装で
チップ搭載片５に搭載されているために、固定と電気的
接続とを同時におこなうことができてワイヤーボンディ
ングなどの必要がなく、従って製造にあたっての加工エ
敗を少なくすることがでさるものである。In the semiconductor IC device A formed in this way, the IC
Since the chip 1 is connected to the leads 3 of the lead frame 2, the third
Unlike the conventional example shown in the figure, there is no need to perform through-hole processing or circuit processing, and since the IC chip 1 is directly mounted on the chip mounting piece 5, fixing and electrical connection can be performed at the same time. This method eliminates the need for wire bonding, and therefore reduces processing errors during manufacturing.
また基板は金型成形した成形樹脂４によって形成するこ
とがでさるため１三、基板を積層成形で得られるプリン
ト配線板１１で形成する場合よりも厚みの寸法精度良く
形成することができ、ＩＣカードに組み込む場合など薄
さが要求されるパッケージとして好適であると共に、Ｉ
Ｃチップ１はモールド成形され材料密度が高い成形樹脂
４中に封止されていることになり、封止による耐湿性能
を高めることがで慇ると共に外力の影響からＩＣチップ
１を有効に保護することができる。さらには、リードフ
レーム２に設けた補強片７がＩＣチップ１に添って成形
樹脂４に埋入されているために、ＩＣチップ１の箇所に
外力が加わってもこの外力を補強片７で受けることがで
き、ＩＣチップ１が成形樹脂４中で破壊されることを防
止することができるものである。In addition, since the board can be formed from the molded resin 4 molded with a mold, it is possible to form the board with better dimensional accuracy in thickness than when the board is formed from the printed wiring board 11 obtained by lamination molding. It is suitable as a package that requires thinness, such as when incorporated into a card, and is
The C chip 1 is molded and sealed in the molded resin 4 having a high material density, which improves moisture resistance due to sealing and effectively protects the IC chip 1 from the influence of external forces. be able to. Furthermore, since the reinforcing piece 7 provided on the lead frame 2 is embedded in the molded resin 4 along the IC chip 1, even if an external force is applied to the IC chip 1, the reinforcing piece 7 will absorb this external force. This makes it possible to prevent the IC chip 1 from being destroyed in the molding resin 4.
このように形成される半導体ＩＣ装置Ａは、例えばＩＣ
カードに用いられるものであり、リード３のチップ搭載
片５の露出面で形成される端子６をＩＣカードの表面か
ら露出させた状態で、半導体ＩＣ装置ＡをＩＣカード内
に一体に埋め込んで組み込むことができる。ここで、端
子６はリード３よりもさらに肉厚の厚いチップ搭載片５
の露出面で形成されるために、接点などとの接触頻度が
高くて摩耗があっても摩滅したりするようなおそれはな
く、外部への接続の信頼性が低下することはないもので
ある。また端子６として露出するチップ搭載片５にはＩ
Ｃチップ１が直接後して実装されているものであり、Ｉ
Ｃチップ１の発熱をこの部分から外部に効率良く放熱す
ることができ、熱が成形樹脂４中にこもることを防止す
ることができるものである。特にｔｊＩＪ２図の実施例
のようにチップ搭載片５を幅広く形成しておくことによ
って放熱性を高めることができる。尚、第１図の実施例
ではリード３の外側端部３ａも成形樹脂４から突出させ
であるが、半導体ＩＣ装置ＡをＩＣカードに組み込むと
きなどにこのリード３の突出する端部３ａを位置決めと
して利用したり、また静電気を逃がすための７−ス端子
として利用したりすることができる。The semiconductor IC device A formed in this way is, for example, an IC
The semiconductor IC device A is integrally embedded into the IC card, with the terminal 6 formed by the exposed surface of the chip mounting piece 5 of the lead 3 exposed from the surface of the IC card. be able to. Here, the terminal 6 is a chip mounting piece 5 which is thicker than the lead 3.
Since it is formed on the exposed surface of the contact point, there is no risk of wear and tear even if there is wear due to frequent contact with contacts, etc., and the reliability of the connection to the outside will not deteriorate. In addition, the chip mounting piece 5 exposed as the terminal 6 has an I
The C chip 1 is mounted directly after the I chip.
The heat generated by the C-chip 1 can be efficiently radiated to the outside from this portion, and the heat can be prevented from being trapped in the molded resin 4. In particular, by forming the chip mounting piece 5 widely as in the embodiment shown in FIG. tjIJ2, heat dissipation can be improved. In the embodiment shown in FIG. 1, the outer ends 3a of the leads 3 are also made to protrude from the molded resin 4, but when incorporating the semiconductor IC device A into an IC card, etc., the protruding ends 3a of the leads 3 are positioned. It can also be used as a 7-base terminal for dissipating static electricity.
また本発明において、前記リードフレーム２を形成する
金属材料としては、＃ｉ膨張係数が３×１０−’／’Ｃ
−１，８Ｘ １０−５／’Ｃノモノ、好マシくは線膨張
係数が４ Ｘ １０−’／’Ｃ〜９ Ｘ １０−’／’
Ｃのものを用いるものである。ＩＣチップ１としてはシ
リコンウェハーで形成したものが用いられるが、シリコ
ンウェハーのＭ膨張係数３〜４ Ｘ １０−６／℃に対
してリー・ドフレーム２の線膨張係数が大きべ異なると
、温度変化に伴う膨張寸法の差でリードフレーム２のリ
ード３のチップ搭載片−５とＩＣチップ１との接合箇所
にずれが生じ、ＩＣチップ１とリード３との間の導通信
頼性に問題が生じるおそれがあるために、リードフレー
ム２として＃ｉ膨張係数が１，８Ｘ１０−５７’Ｃ以下
のものを用いるものである。リードフレーム２に用いる
ことがでさる金属として線膨張係数が３ Ｘ １０−６
／’Ｃより小さいものは見当たらないために、リードフ
レーム２の線膨張係数の下限は事実上３Ｘ１０−’／’
Ｃに設定されることになる。Further, in the present invention, the metal material forming the lead frame 2 has an #i expansion coefficient of 3×10-'/'C
-1,8X 10-5/'C monomer, preferably linear expansion coefficient of 4 X 10-'/'C ~ 9 X 10-'/'
C. is used. The IC chip 1 is made of a silicon wafer, but if the linear expansion coefficient of the lead frame 2 is significantly different from the silicon wafer's M expansion coefficient of 3 to 4 x 10-6/°C, the temperature Due to the difference in expansion dimensions due to the change, a deviation occurs at the joint between the chip mounting piece 5 of the lead 3 of the lead frame 2 and the IC chip 1, causing a problem in the reliability of conduction between the IC chip 1 and the lead 3. Because of this risk, a lead frame 2 with #i expansion coefficient of 1.8X10-57'C or less is used. A metal that can be used for lead frame 2 has a coefficient of linear expansion of 3 x 10-6
Since nothing smaller than /'C is found, the lower limit of the linear expansion coefficient of lead frame 2 is actually 3X10-'/'
It will be set to C.
ここで、リードフレーム２の線膨張係数の影響を試験に
よって例証する。Here, the influence of the linear expansion coefficient of the lead frame 2 will be illustrated by a test.
大麦に示す材料で形成したり−ド７レームを用い、この
リードフレームのリードに２．３Ｘ３．２１で厚み０．
２ＩＩＩ１１１のくし形Ａｌｌ配線を形成したシリコン
ウェハー製の評価用チップを半田バンプで７リツプチツ
プ実装し、トランスファー成形装置でエポキシ樹脂封止
成形をおこなった。このようにして作成したパッケージ
について、−６５℃に冷却したのちに１５０℃に加熱す
る捏作を１サイクルとして繰り返す熱衝撃試験をおこな
い、各サイクル毎に断線不良の発生の有無を検査した。A frame made of the material shown in barley is used, and the leads of this lead frame are 2.3 x 3.21 and have a thickness of 0.
Seven evaluation chips made of silicon wafers with 2III111 comb-shaped All wiring were mounted using solder bumps, and encapsulated with epoxy resin using a transfer molding machine. The package thus produced was subjected to a thermal shock test in which fabrication in which the package was cooled to -65°C and then heated to 150°C was repeated as one cycle, and the occurrence of disconnection defects was examined for each cycle.
試験は１０個のサンプルについておこない、５個のサン
プルが断線したときの熱衝撃のサイクル数を結果として
大麦に示した。The test was conducted on 10 samples, and the number of cycles of thermal shock when 5 samples were disconnected was shown as the result for barley.
表に見られるように、試験５の＃ｉ膨張係数が２゜３Ｘ
１０−’／’Ｃのアルミニウムでリードフレームを形成
するようにしたものでは、熱衝撃試験の結果は悪いが、
＃ｉ膨張係数が３ Ｘ １０ ’−’／’Ｃ〜１゜８
Ｘ １０−’／’Ｃの範囲に含まれる試験１〜４のもの
では良好な熱衝撃試験の結果が得られることが確認され
る。尚、断線不良の総てはリードとチップの半田バンプ
との外れであった。As seen in the table, #i expansion coefficient of test 5 is 2°3X
The lead frame made of 10-'/'C aluminum gave poor thermal shock test results, but
#i expansion coefficient is 3 x 10'-'/'C~1°8
It is confirmed that good thermal shock test results can be obtained in Tests 1 to 4 which fall within the range of X 10-'/'C. Note that all of the disconnection defects were due to disconnection between the leads and the solder bumps on the chip.
［発明の効果］
上述のように本発明にあっては、金属り−′＋ｔフレー
ムの複数本の各リードのチップ搭載片の片側表面にＩＣ
チップを搭載して直接実装すると共にＩＣチップをリー
ドとともに成形樹脂内に封入するようにしであるので、
ＩＣチップは成形樹脂を基板としリードフレームのリー
ドに接続された状態で搭載されるものであり、プリント
配線板を基板として用いる従来例のようにスルーホール
加工や回路形成、ワイヤーボンディングなどの加工をす
る必要はなく、製造にあたっての加工エ敗を少なくする
ことができるものである。、また、チップ搭載片の肉厚
をリードの他の部分よりも厚く形成し、成形樹脂の表面
にチップ搭載片のＩＣチップを搭載した側と反対側の面
を端子として露出させるようにしたので、チップ搭載片
の露出面で形成される端子に摩耗があってもリードより
さらに厚みの厚いチップ搭載片が摩滅するようなおそれ
はほとんどなく、外部への接続の信頼性が低下すること
はないものであり、さらに端子として露出するチップ搭
載片にはＩＣチップが直接後して実装されているもので
あって、ＩＣチップの発熱をこの部分から外部に効率良
く放熱することができ、ＩＣチップの熱が成形樹脂中に
こもることを防止できるものである。加、えて、リード
フレームに設けた補強片をＩＣチップに添わせるように
しであるので、ＩＣチップの箇所に外力が加わってもこ
の外力を補強片で受けてＩＣチップが成形樹脂内で変形
されたりすることを防止でき、ＩＣチ、ンプの保護の効
果を高めることができるものである。[Effects of the Invention] As described above, in the present invention, an IC is mounted on one surface of the chip mounting piece of each of the plurality of leads of the metal frame.
Since the IC chip is mounted and directly mounted, and the IC chip is encapsulated together with the leads in the molded resin,
An IC chip is mounted on a molded resin substrate connected to the leads of a lead frame, and does not require processing such as through-hole processing, circuit formation, and wire bonding, as in the conventional case where a printed wiring board is used as a substrate. There is no need to do this, and processing errors during manufacturing can be reduced. In addition, the thickness of the chip mounting piece is made thicker than the other parts of the lead, and the side of the chip mounting piece opposite to the side on which the IC chip is mounted is exposed as a terminal on the surface of the molded resin. Even if there is wear on the terminal formed on the exposed surface of the chip mounting piece, there is little risk that the chip mounting piece, which is thicker than the lead, will wear out, and the reliability of the connection to the outside will not deteriorate. Furthermore, the IC chip is mounted directly behind the chip mounting piece that is exposed as a terminal, and the heat generated by the IC chip can be efficiently dissipated from this part to the outside. This prevents heat from being trapped in the molded resin. In addition, since the reinforcing piece provided on the lead frame is attached to the IC chip, even if an external force is applied to the IC chip, this external force will be received by the reinforcing piece and the IC chip will be deformed within the molding resin. This can prevent damage to the IC chip and increase the effect of protecting the IC chip.
また、リードフレームを線膨張係数が３Ｘ１０−’／℃
〜１．８ Ｘ １０−’／’Ｃの金属で形成しであるの
で、線膨張係数が３〜４ Ｘ １０−’／’Ｃのンリコ
ンウェハーのＩＣチップにリードフレームの線膨張係数
を近似させ、熱膨張の差でＩＣチップとリードのチップ
搭載片との間の接合が外れて導通信頼性が低下すること
を防止することができるものである。In addition, the linear expansion coefficient of the lead frame is 3X10-'/℃
Since it is made of metal with a coefficient of ~1.8 x 10-'/'C, the coefficient of linear expansion of the lead frame can be approximated to the IC chip of a silicon wafer with a coefficient of linear expansion of 3 to 4 x 10-'/'C. This makes it possible to prevent the connection between the IC chip and the chip mounting piece of the lead from coming loose due to a difference in thermal expansion, thereby preventing the conduction reliability from decreasing.
第１図は本発明の一実施例の断面図、第２図は同上に用
いるリードフレームの一部の斜視図、第３図は従来例の
断面図である。
１はＩＣチップ、２はリードフレーム、３はリード、４
は成形樹脂、５はチップ搭載片、６は端子、７は補強片
である。FIG. 1 is a sectional view of one embodiment of the present invention, FIG. 2 is a perspective view of a part of a lead frame used in the same, and FIG. 3 is a sectional view of a conventional example. 1 is an IC chip, 2 is a lead frame, 3 is a lead, 4
5 is a molded resin, 5 is a chip mounting piece, 6 is a terminal, and 7 is a reinforcing piece.
Claims (1)
１０＾−＾５／℃の金属リードフレームの複数本の各リ
ードにチップ搭載片を形成すると共にチップ搭載片の肉
厚をリードの他の部分の厚みよりも厚く形成し、このチ
ップ搭載片の片側表面にシリコンウェハーで形成される
ＩＣチップを搭載して直接実装すると共にリードフレー
ムに設けた補強片をＩＣチップに添わせ、ＩＣチップを
リード及び補強片とともに成形樹脂内に封入し、成形樹
脂の表面にチップ搭載片の他方の片側表面を露出させて
成ることを特徴とする半導体ＩＣ装置。(1) Linear expansion coefficient is 3 x 10^-^6/°C ~ 1.8 x
A chip mounting piece is formed on each of the multiple leads of a 10^-^5/℃ metal lead frame, and the thickness of the chip mounting piece is formed to be thicker than the thickness of other parts of the lead. An IC chip formed of a silicon wafer is mounted on one surface and directly mounted, a reinforcing piece provided on a lead frame is attached to the IC chip, the IC chip is encapsulated together with the leads and reinforcing piece in a molded resin, and the molded resin 1. A semiconductor IC device characterized in that the other one side surface of a chip mounting piece is exposed on the surface of the semiconductor IC device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62288027A JPH01128897A (en) | 1987-11-14 | 1987-11-14 | Semiconductor ic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62288027A JPH01128897A (en) | 1987-11-14 | 1987-11-14 | Semiconductor ic device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01128897A true JPH01128897A (en) | 1989-05-22 |
Family
ID=17724868
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62288027A Pending JPH01128897A (en) | 1987-11-14 | 1987-11-14 | Semiconductor ic device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01128897A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6716670B1 (en) | 2002-01-09 | 2004-04-06 | Bridge Semiconductor Corporation | Method of forming a three-dimensional stacked semiconductor package device |
| US6936495B1 (en) | 2002-01-09 | 2005-08-30 | Bridge Semiconductor Corporation | Method of making an optoelectronic semiconductor package device |
| US6987034B1 (en) | 2002-01-09 | 2006-01-17 | Bridge Semiconductor Corporation | Method of making a semiconductor package device that includes singulating and trimming a lead |
-
1987
- 1987-11-14 JP JP62288027A patent/JPH01128897A/en active Pending
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6716670B1 (en) | 2002-01-09 | 2004-04-06 | Bridge Semiconductor Corporation | Method of forming a three-dimensional stacked semiconductor package device |
| US6774659B1 (en) | 2002-01-09 | 2004-08-10 | Bridge Semiconductor Corporation | Method of testing a semiconductor package device |
| US6803651B1 (en) | 2002-01-09 | 2004-10-12 | Bridge Semiconductor Corporation | Optoelectronic semiconductor package device |
| US6891276B1 (en) * | 2002-01-09 | 2005-05-10 | Bridge Semiconductor Corporation | Semiconductor package device |
| US6908794B1 (en) | 2002-01-09 | 2005-06-21 | Bridge Semiconductor Corporation | Method of making a semiconductor package device that includes a conductive trace with recessed and non-recessed portions |
| US6936495B1 (en) | 2002-01-09 | 2005-08-30 | Bridge Semiconductor Corporation | Method of making an optoelectronic semiconductor package device |
| US6987034B1 (en) | 2002-01-09 | 2006-01-17 | Bridge Semiconductor Corporation | Method of making a semiconductor package device that includes singulating and trimming a lead |
| US6989584B1 (en) | 2002-01-09 | 2006-01-24 | Bridge Semiconductor Corporation | Semiconductor package device that includes a conductive trace with a routing line, a terminal and a lead |
| US6989295B1 (en) | 2002-01-09 | 2006-01-24 | Bridge Semiconductor Corporation | Method of making a semiconductor package device that includes an insulative housing with first and second housing portions |
| US7009309B1 (en) | 2002-01-09 | 2006-03-07 | Bridge Semiconductor Corporation | Semiconductor package device that includes an insulative housing with a protruding peripheral portion |
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