JPH01128636A - System for transmitting data intra-asynchronous equipments - Google Patents

Abstract

PURPOSE:To execute data transmission between systems which are mutually operated in asyncheonization at high speed with exact control by providing a transmission side equipment to have a T-type flip-flop and a defferentiation circuit to detect the output of a synchronizing circuit. CONSTITUTION:Data to be transmitted from a #1 system 10 to a #2 system 30 are written to a transmission register 11 by a set signal to be synchronized to a clock C1 of the #1 system 10 based on a set input. Simultaneously, a T-type flip-flop 12 sends a trigger signal synchronized to the clock C1 to a synchronizing circuit 31 of the #2 system 30. The synchronizing circuit 31 sends the receiving data which are synchronized to a clock C2 of the #2 system 30. Then, based on a differentiation output to be obtained by detecting the leading and trailing edges of the output of the synchronizing circuit 31, a differentiation circuit 32 sets the data which are sent per bit from the transmission register 11 through data lines 211, 212-21n to a receiving register 33. Thus, the data transmission can be executed at the high speed.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a data transmission method between asynchronous devices for transmitting data between devices connected by a plurality of data lines that operate asynchronously to each other and perform parallel transmission. The purpose is to perform high-speed data transmission between systems operating on a transmitter under precise control. a transmission line comprising a transmitting side device including a T-type flip-flop for transmitting data, a plurality of data lines for transmitting data from the transmitting register, and a trigger signal line for transmitting the output of the flip-flop; , a receiving side device comprising: a synchronization circuit that synchronizes the trigger signal with its own clock; a differentiation circuit that detects the output of the synchronization circuit; and a reception register that sets the data using the output of the differentiation circuit. Consists of.

[Industrial application field]

The present invention relates to a data transmission method between asynchronous devices for transmitting data between devices connected by a plurality of data lines that operate asynchronously and perform parallel transmission.

[Conventional technology]

Figure 3 shows a conventional data transmission method between devices connected by a dedicated data line, where data is transmitted as parallel signals from #1 system 1 to #2 system 3, which are operating asynchronously. , the data sent in synchronization with the clock C1 of the #1 system is transferred to #2.
It is received in synchronization with the system clock C2.

In system #1, when set inputs are supplied to flip-flop 12 and gate circuit 13, data to be transmitted is sent to gate circuit 1. Based on the set signal synchronized with the clock CI which is the output of the transmitting register 1. At the same time, 7 lip-flop 1□ is set,
A trigger signal is sent from the output of this flip-flop 12 via the trigger signal line 22 of the transmission line 2 to the synchronization circuit 31 of the #2 system.

#2 The synchronization circuit 31 provided in the system #2 receives the trigger signal transmitted via the trigger signal line 22.
2 system clock C2, and uses this as a reception control signal to be sent to the gate circuit 3. supply to. Then, based on the reception control signal synchronized with the clock C2 obtained from the output of the gate circuit 33, the data lines 211+ 212+ .
The data being sent through 21° is received by the receiving register 3.
Set to 2.

As mentioned above, when the data sent from the transmission register 11 in synchronization with the clock C1 of the #1 system is synchronized with the clock C2 of the #2 system based on the trigger signal and is set in the reception register 32. , a reception signal is sent back from the #2 system to the synchronization circuit 14 of the #1 system via the signal line 23.

Then, the above synchronization circuit 1. The reception signal that is returned in synchronization with the clock C2 is synchronized with the clock C1 of the #1 system, and this is sent to the flip-flop 12 as a reset signal, and the flip-flop 12 is set to the reset state and the next data is sent. Prepare for transmission.

[Problem that the invention seeks to solve]

In the conventional data transmission method between asynchronous devices as described above, the sending device cannot prepare to send the next data after receiving the signal from the receiving device until the signal is returned. When it is desired to send data, there is a waiting time and there is a problem that loss time occurs.

In addition, two control lines are required for synchronization, one for the bird and the other for reception, and when bidirectional data transfer or multiple data buses are used, the number of control lines increases and each control line is required. There was a problem that a synchronization circuit was required for each line.

An object of the present invention is to provide a data transmission system between asynchronous devices that allows data transmission between systems that operate asynchronously to be performed at high speed under accurate control.

[Means for solving problems]

As shown in the principle diagram of FIG. 1, the transmission includes a transmission register 11 and a T-type flip-flop 12 that inverts and sends out a trigger signal when the writing of data to be transmitted to the transmission register 11 is completed. side device 10, and a plurality of data lines 218, 212. for transmitting data bit by bit from the transmission register 11 to the receiving side device.
... 21, and a trigger signal line 22 for transmitting the trigger signal from the T-type flip-flop 12, and a trigger signal line 22 for transmitting the trigger signal from the transmitting device 10.
A synchronization circuit 31 that synchronizes the trigger signal transmitted through the synchronization circuit 31 with its own clock; a differentiation circuit 32 that detects the rise and fall of the output of this synchronization circuit 31; The above data line 211
, 212. ...211. Data is transmitted between the asynchronous devices by the receiving side device 30, which includes a receiving register 33 into which bit-by-bit data transmitted via the receiving register 33 is set.

[For production]

Data to be transmitted from the #1 system 10 to the #2 system 30 is transferred to the transmission register 11 by a set signal synchronized with the clock C1 of the #1 system 10 based on the set manual.
written to.

Furthermore, at the same time as writing the data to the transmission register 11, the T-type flip-flop 12 synchronizes the #2 system 30 by sending a trigger signal synchronized with the clock C1 via the trigger signal line 22 of the transmission line 20. The signal is sent to the circuit 31.

The synchronization circuit 31, which has received the trigger signal from the T-type flip-flop 12, sends the received data synchronized to the lock C2 through the #2 system 30 to the differentiating circuit 32. Based on the differential output obtained by detecting the rising and falling edges of the outputs of the data lines 21 . ．． 212.・・・
・21. The data being sent out bit by bit via the receiving register 33 is set in the receiving register 33.

〔Example〕

FIG. 2 shows an embodiment of the present invention in which a plurality of pieces of data are simultaneously transmitted to the #2 system. Components corresponding to those in FIG. 1 are denoted by the same reference numerals. It is.

#1 The output section of the system 10 includes a transmission register 11 that temporarily stores the data to be transmitted, and a T-type flip-flop that inverts and generates a trigger signal when the writing of the data to be transmitted to the transmission register 11 is completed. 12. The set signal for writing data to be transmitted to the transmission register 11 based on the set input is sent to the clock C1 of the #1 system.
It is composed of a gate circuit 13 that outputs an output in synchronization with.

Further, the receiving section of the #2 system 30 includes flip-flops 310 and 312 that synchronize the trigger signal transmitted from the T-type flip-flop 12 via the trigger signal line 22 with the clock C2' of the #2 system. A synchronization circuit 31, a D-type flip-flop 32, which detects the rise and fall of the received data synchronized by the synchronization circuit 31. and exclusive OR circuit 322
A differentiating circuit 32 composed of a differentiating circuit 32, a gate circuit 34 that synchronizes the differential output of this differentiating circuit 32 with the clock C2 and outputting a reception control signal, and a data line 21+ from the transmitting register 11 based on the output of this gate circuit 34. 212.・・・
. . . It is composed of a receiving register 33 in which bit-by-bit data sent out via the register 217 is set.

Between the transmitting side and receiving side systems that operate asynchronously with each other, the data to be transmitted from the #1 system 10 to the #2 system 30 is the output of the gate circuit 13 synchronized with the clock CI based on the set input. The data lines 211, 212, .・・・
・21. .

The received signal is sent to the receiving register 33 of the #2 system 30 via the #2 system 30.

Furthermore, when writing of data to the transmission register 11 based on the above set signal is completed, a trigger signal synchronized with the clock CI is sent from the T-type flip-flop 12 to the #2 system via the trigger signal line 22 of the transmission line 20. 30 synchronization circuit 31.

The synchronization circuit 31 that receives the trigger signal sent from the T-type flip-flop 12 includes two-stage flip-flops a1.
, 3t, and its clock CI from the #l system
The trigger signal sent in synchronization with the #2 system clock C2 is latched by the first stage flip-flop 311, and is sent to the second stage flip-flop 31.
2 to #2 is read by the clock C2 of the system.

The synchronization circuit 31 converts the trigger signal into its own clock C2.
The signal Sa obtained by synchronizing with is supplied to a D-type flip-flop 321 and an exclusive OR circuit 322 that constitute a differentiating circuit 32, where the rise and fall of the signal Sa from the synchronization circuit 31 are detected. be done. At this time, the signal sb, which is the signal Sa delayed by one clock, is output from the output of the D-type flip-flop 321 operating with the clock C2 of the #2 system, and the exclusive OR circuit 322 outputs the signal Sa and the signal Sb. The exclusive OR of is taken.

The output of the above exclusive OR circuit 322 is connected to the output Sa of the synchronization circuit 31 and the D-type flip-flop 32.
becomes active when the outputs sb of the two do not match, and this active output is taken out via the gate circuit 34 as a reception control signal synchronized with the clock C2. Then, only one cycle when the trigger signal is inverted based on the reception control signal output from the differentiating circuit 32 is sent from the transmission register 11 via the data lines 21□521□, -21i of the transmission line 20. The data for each bit is sent to the reception register 33.
is set to

〔Effect of the invention〕

According to the present invention described above, in parallel data transmission between asynchronous devices, reception from the receiving system does not require signal return, so the number of control lines between systems can be reduced and the synchronization circuit can be Since this is no longer necessary, the number of components can be significantly reduced. In addition, it is possible to set the next transmission data to the transmit register of the transmitting system after the minimum time required for setting the data to the receiving register of the receiving system without waiting for the reception (return of the word). As a result, it is possible to achieve the effect of efficiently transmitting data continuously.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing a conventional example. 10...#1 system (transmitting side equipment), 11... transmitting register, 12... T-type flip-flop, 20
...transmission line, 21. ．． 212.・・・ 21.・・・
・Data line, 22...Trigger signal line, 30...#2
System (receiving side device), 31... synchronization circuit, 32
...Differential circuit, 33...Reception register.

Claims (1)

[Claims] A transmitting side device comprising a transmitting register (11) and a T-type flip-flop (12) that inverts and sends out a trigger signal when writing of data to be transmitted to the transmitting register is completed. (10), and multiple data lines (21) for transmitting each bit from the transmission register to the receiving device.
_1, 21_2, ...21_n) and a trigger signal line (22) that transmits the output of the flip-flop; a synchronization circuit (31) that synchronizes the generated trigger signal with its own clock; a differentiation circuit (32) that detects the rise and fall of the output of this synchronization circuit; A method for transmitting data between asynchronous devices, comprising a receiving device (30) and a receiving register (33) in which each bit of transmitted data is set.