JPH01128534A - Mounting method for semiconductor element on transparent substrate - Google Patents

Abstract

PURPOSE:To shield a light at an IC chip simultaneously during the manufacture of a semiconductor element and to further reduce the stray capacitance due to wirings by forming a light shielding film during manufacturing step of a FET, shielding a light incident from a glass substrate, and setting a distance between a conductive material and the film to a specific value or less. CONSTITUTION:A light shielding gate electrode 2 is formed of Cr on a glass substrate 1. A light shielding layer 3 of a COG region is held at a ground potential or a predetermined potential. The height 50 of bump for connecting an IC chip 1 to a wiring conductive film 9 by a COG bump 10 is so set that the distance between a wiring conductive film 9 and the chip 11 becomes 1$mum or more. This is because, if a dust is engaged, it might be short-circuited. Further, this is because, when the height 50 of the bump is set 10mum or more, the forming accuracy of the bump itself is deteriorated. In order to complete as a liquid crystal display, an opposite glass substrate containing a color filter, opposite electrode, etc., is disposed on a TFT region isolated at 1mm or more from the chip 11.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a so-called chip-on-glass (hereinafter abbreviated as COG) in which an IC chip, which is a semiconductor element, is mounted on a transparent substrate, such as a glass substrate. Furthermore, the present invention
As the active layer, for example, amorphous silicon (hereinafter a-3t: H
The present invention relates to a mounting method for forming a thin film transistor (hereinafter abbreviated as TPT) using a thin film transistor (hereinafter abbreviated as TPT) on a glass substrate.

Conventional technology a-3t: TPT using H can be easily formed over a large area at a relatively 1 degree temperature around 200''C.
It is being researched to be applied to dimensional sensors and liquid crystal displays. Conventionally, signals for driving these semiconductor elements are provided by a mounting method in which an electrode is provided at the edge of the substrate and an external circuit is connected using a flexible film.

On the other hand, in order to increase added value, semiconductor devices using single-crystal silicon as a substrate are becoming more densely packed. One-dimensional sensors and liquid crystal displays formed on glass substrates are no exception, and they are also being made larger by taking advantage of the characteristics of glass substrates. Flexible films use expensive polyimide resin, and as the size and density of flexible films increases, the number and area of films to be mounted increases, making the cost of materials more expensive. Furthermore, the number of contacts increases, which causes problems in terms of reliability, so IC chips are mounted directly on the glass substrate.
The OG method has been used.

However, in the case of -dimensional sensors, liquid crystal displays, etc.
Intense light was incident from the glass substrate side and directly irradiated the IC chip.

Problems that the invention aims to solve COG IC chips usually do not have a light-shielding film;
A method was used in which the entire substrate was finally shielded from light. However, dimensional sensors and liquid crystal displays are difficult to use due to their complicated light input methods and due to the miniaturization of the entire device.
It has been difficult to use a method of blocking light at the end of these manufacturing steps.

When a light shielding film is not used, in the case of a liquid crystal display (1) Normally, when the IC chip is completely shielded from light, the signal-to-noise ratio of the image sharpness is about 4o to 5o, but the fluorescent light beam of 1000 lux is When the IC chip is irradiated with the illuminance of
This ratio was about 1o or less.

Means for solving the problem During the manufacturing process of TPT used as one-dimensional sensors and switching elements of liquid crystal displays, light-shielding gate electrode material or source electrode material is used in the area where semiconductor elements such as IC chips are arranged. A light-shielding film is formed on a transparent substrate, such as a glass substrate, using the method to block light incident from the glass substrate side.

Furthermore, in order to reduce the capacitance formed between the IC chip and the light shielding film, it is desirable to set the distance between the conductive material on the IC chip and the light shielding film to 1 μm or more and 10 μm or less, and fill the space with an insulating material except for a part. .

Further, the intervals between parts such as auxiliary capacitors installed on the glass substrate should be 11111 or more.

Function: The IC chip can block light from the glass surface by using the light-shielding gate electrode material or source electrode material.
By providing a distance of 1 μm or more between these light shielding films and the IC chip, the capacitance formed between them is reduced.

The reason why it has to be 10 μm or less is because the molding accuracy deteriorates when forming the bump itself. In addition, reliability can be improved by inserting an insulator between the substrate and the IC chip, and the adhesive strength of the components can be improved by leaving a gap of 1 wA or more between components installed on the glass substrate. can.

EXAMPLE Hereinafter, regarding an example, FIG. 1 shows a cross-sectional view for explaining the manufacturing process by taking a liquid crystal display as an example. The cross-sectional view is divided into a TFT region 1oO and a COG region 200.

A light-shielding gate electrode 2 made of Cr is formed on a glass substrate 1 (FIG. 1). In the COG region, it becomes a light shielding layer 3. The light shielding layer 3 is divided into a plurality of regions in order to reduce the capacitance. Depending on the frequency used in the IC, the light shielding layer 3 may be a single region.

In a high frequency glow discharge device, the TPT gate insulating film 4, T
An a-3t:H film 6, which is the active layer of PT, and a protective film 6 are formed, and contact holes 7 for the source and drain portions are opened (FIG. 2). The gate insulating film 4 has multiple layers due to the TPT manufacturing process. Next, an n-type a-3t:H film 8 is formed (FIG. 3).

Next, a metal film containing A1 is deposited to form a wiring conductive film 9 which also serves as source and drain electrodes (FIG. 4). C.O.
The light shielding layer 3 in the G region is maintained at a ground potential or a certain potential. The height of the bump that connects the IC chip 11 to the wiring conductive film 9 using the COG bump 10 is 5o.
The distance between the wiring conductive film 9 and the IC chip 11 is set to be 1 μm or more. This is because there is a possibility of a short circuit if dust or the like is caught between them, and because the driving frequency of the IC chip 11 is high, capacitive coupling is formed between the wiring conductive film 9 and the IC chip 11. This is to prevent Further, if the height 50 of the bump is set to 10 μm or more, the molding accuracy of the bump itself deteriorates. In order to complete a liquid crystal display, a counter glass substrate containing color filters, counter electrodes, etc. is connected to IC chips 11 and 1.
The liquid crystal is placed over the TFT area with a gap of at least mm, and liquid crystal is injected, but this is omitted here.

The second example will be described below.

In FIG. 4, the contact conductive material on the glass substrate 1 side with the COG bump 1o is a conductive film 9 for wiring and lines.

In the first example, it was a metal film containing AI.

When using a metal oxide conductive film such as ITO (Indium Tin Oxide), it is necessary to raise the temperature to about 150'C or more in order to lower the sheet resistance, and to prevent oxidation of the underlying metal film surface. It is better to form IT○ directly on the glass substrate 1. For this purpose, ITO or the like is formed between the light shielding layer 3 and the glass substrate 1 shown in FIG.
In the figure, before connecting the IC chip 11 using the COG bump, a wiring conductive film 9. Protective film 6°a-3i: H film 6, gate insulating film 4, and light shielding layer 3 are etched. Consider the bump height 50 at this time. The distance between the IC chip 11 and the wiring conductive film 9 is
It becomes smaller than the height 60 of the bump depending on the thickness of the wiring conductive film 9 and the like. Considering this, the height 50 of the bump is determined, and the distance between the IC chip 11 and the wiring conductive film 9 is set to 1 μm.
The thickness must be 10 μm or less. The distance limit is as explained in the first embodiment.

In Fig. 4, the strong light enters mainly from the bottom to the top of the drawing, and the direction of light incidence 6 in Fig. 4 is
It is shown as 0.

Effects of the Invention The mounting method according to the present invention allows CO of semiconductor devices to be removed using light, which was previously avoided due to optical instability.
Light shielding for G-mounted IC chips can be created at the same time as semiconductor element manufacturing, and stray capacitance due to wiring can also be reduced. No extra processes are required, and the process is simple and inexpensive. With this, a semiconductor element can be mounted on a transparent substrate.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing the first step of the semiconductor device mounting method according to the present invention, FIG. 2 is a cross-sectional view showing the second step of the mounting method according to the present invention, and FIG. FIG. 4 is a sectional view of the fourth step of the mounting method according to the present invention. 2...Light-shielding gate electrode, 3...Light-shielding film, 4...Gate insulating film, 5...6-
5i: H film, 9... conductive film for wiring, 60...
... Bump height, 60 ... Light incident direction, 1
00...TFT area, 200...CO
G area. Name of agent: Patent attorney Toshio Nakao and 1 other person/-
, f7" lath difference 4 anti-shading ridge conductive film υθ-cocr deposit area 6- protective film Fig. 3 δ-7L"iq a-3i: H film

Claims (3)

[Claims] (1) A light-shielding gate electrode of a thin film transistor divided into a plurality of parts, an insulating thin film of multiple layers, a semiconductor thin film as an active layer of the transistor, a source electrode, a drain electrode, and a semiconductor element are arranged on a transparent substrate as constituent elements. including,
A method for mounting a semiconductor element on a transparent substrate, characterized in that light incident from the transparent substrate side is blocked by the gate electrode material or the source electrode material formed during the thin film transistor manufacturing process. (2) The distance between the light-shielding gate electrode material and/or source electrode material and the conductive material on the semiconductor element is set to 1 μm or more and 10 μm or less, and the space formed by the distance is partially filled with an insulating material. A method for mounting a semiconductor element on a transparent substrate as claimed in claim 1. (3) A method for mounting a semiconductor element on a transparent substrate according to claim 1, characterized in that the distance between each component installed on the transparent substrate is 1 mm or more.