JPH01128268A - Recording and reproducing device - Google Patents

Abstract

PURPOSE:To attain consecutive recording matched to the phase of a reproducing signal by obtaining a phase shift between the reproducing signal and a reference address, correcting the phase of a recording address and executing consecutive recording by using the corrected recording address. CONSTITUTION:A correction data generation part 310 obtains a difference between the phase of the reference address R3RADR and that of a reproduction block address PBAD, and gives phase shift correction data STBLK to a recording timing generation part 316. The generation part 316 generates the recording address RCADR with data STBLK transmitted from the generation part 310 as an initial value. Since the recording timing is generated so that it is matched to the phase of the reproducing signal, a new recording track can be generated by matching it to the original phase at the time of the consecutive recording.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital data recording and reproducing apparatus such as an R-DAT (rotating head type digital audio tape recorder).

BACKGROUND ART In recent years, digital recording technology has been applied to many fields such as audio and video, CD players, and R-DAT.

Technologies such as digital VTR have been established.

Among these, in addition to basic recording and playback technologies, applied technical fields such as after-recording and splicing recording have become important.

When performing after-recording, splicing recording, etc., it is necessary to perform new recording in accordance with the playback signal. If the reproduction signal and the recording signal have different phases, the recording format itself cannot be guaranteed, and normal tracking servo and reproduction cannot be performed.

Therefore, in a conventional recording device, taking R-DAT as an example, a signal processing unit generates a timing signal that serves as a reference for the rotation of a cylinder equipped with two heads, and based on this signal, the rotational phase of the cylinder is A servo system has been used to synchronize the timing of the signal processing unit and the signal processing unit.

Problems to be Solved by the Invention However, with the above configuration, a mechanical PG (phase generator) is required to know the rotational phase of the cylinder, and PG installation errors and detection errors become problems. The phase accuracy between the playback signal and the timing of the signal processing section is not sufficient, resulting in after-recording, m
When performing new recording, the phase of the surface recording track and the new recording track do not match, which has the problem of adversely affecting subsequent reproduction.

In view of the above problems, the present invention extracts the block address in the reproduced signal and compares it with the reference address at that time.
By detecting the phase shift between the reproduced signal and the reference address and reflecting the result on the recording address, the recording address and the reproduced signal are aligned in phase, and a continuous recording track is formed even during after-recording and splicing recording. The present invention provides a recording and reproducing device that can perform the following functions.

Means for Solving the Problems In order to solve the above problems, the recording/reproducing apparatus of the present invention includes a recording phase detection means for detecting the recording phase of the first recording track, and a recording phase detecting means for detecting the recording phase of the first recording track. The second recording track is composed of a continuous recording control means for controlling the recording phase of the second recording track.

Operation The present invention uses the above-described configuration to detect a valid block address, use the reference address and block address at this time to determine the phase shift between the reproduced signal and the reference address, and correct the phase of the recording address. After recording, splicing recording, etc. that match the phase of the reproduced signal are performed using the recorded address.

Embodiment Hereinafter, a first embodiment of the recording/reproducing apparatus of the present invention will be described.
This will be explained with reference to the drawings.

FIG. 1 shows a first embodiment in which the recording/reproducing apparatus of the present invention is applied to an R-DAT (rotating head type digital audio tape recorder).

In Figure 1, l00a and 100b are each ±2
A recording/reproducing head with an azimuth angle of 0 degrees, 101 is a cylinder, 102 is a magnetic tape, 1.03a, 103b
104 is a reel that winds up the tape 102, and 104 is a tape 10.
105 is a head amplifier for recording and reproducing, 106 is an equalizer for equalizing the waveform of the reproduced signal, and 107 is for extracting a reproduced clock PCK for punching the reproduced signal from the reproduced signal. PT-
L (phas6 Looked [, oop) circuit, 108 is a modulation/demodulation unit for demodulating the reproduced signal and modulating the recording signal, and 109 is a code processing processor for performing error detection, correction, and generation of an error correction code. , 110
111 is a RAM unit that stores modulation/demodulation data, PCM data, etc., and 111 is a PC that performs interpolation processing of reproduced PCM data.
M processing unit, 112 is an A/D converter, 113 is a D/D converter;
The A comparator 114 receives the cylinder synchronization signal R3CP.
, and modulation/demodulation section 108, code processing processor 109, RA
A timing generating section 115 that generates a basic clock for the M section 110 and the PCM control section 111 is a servo block that controls the cylinder 101, the reels 103a and 103b, and the capstan 104. Reference numeral 116 denotes a system control unit that instructs the mode of the system.

Next, the flow of signals during recording will be explained.

When the system control unit 116 instructs the recording mode, the audio input AIN is input to the A/D converter 112 and converted into 16-bit 1-PCM data.

The PCM data is input to the PCM control section 111, sent as 8-bit data to the RAM section 110, interleaved, and saved. The code processing processor 109 is R
An error correction code is added to the PCM data saved in the AM section 110 to generate pre-modulation data, and the data is stored in the RAM section 110.
Save to. After that, the modulation/demodulation section 108 and the RAM section 1
10 receives modulated data at a predetermined timing, performs modulation processing, and generates a recording signal RFOUT. The recording signal RFOUT is sent to the head 100a through the head amplifier 105.

100b.

On the other hand, the servo block 115 includes the timing generator 1
The rotation of the cylinder 1010 is controlled based on the cylinder synchronization signal R3CP generated by No. 14, and the head touch section and the recording signal RFOUT are aligned in phase, and a head switching signal H3W is generated to determine whether the azimuth is +azimuth or -azimuth. Decide whether to send recording current to the head.

FIGS. 2(a) to 2(d) are timing charts showing the operation of the servo block. Figure 2 (al~(d)
, R3CP is the cylinder synchronization signal, and the servo
The block controls cylinder rotation so that the recording signal RFOUT and the head touch are in phase. It also generates a signal H3W for switching between +azimuth head Hp and -azimuth head l(m).

At this time, the tape 102 runs at a constant speed, and tracks with a width of - are recorded.

Next, the flow of signals during reproduction will be explained.

When the system control unit 116 instructs the playback mode, the cylinder 101 is controlled by the servo block 115 based on R3CP, and the head touch period and demodulation timing are synchronized, as in the case of recording.

Furthermore, the tape speed is ATF (Automa
The head is controlled to trace the track using a technique called ticTrack Finding.

The head signal RFSG reproduced from the heads 100a and 100b is supplied to an equalizer 106 through a head up 105, subjected to waveform equalization, and then supplied to a PLL 107, where a reproduced clock is extracted and supplied to a modulation/demodulation section 108.

The modulation/demodulation section 108 transfers the demodulated data to the RAM section 110.
write to. Further, the code processing processor 109 has RAM
Demodulated data is read out from section 110 and error detection and error correction are performed. The PCM control unit reads the corrected 8-bit data from the RAM unit 110, de-interleaves it, and sends it to the D/A converter 13 as 16-bit data.
supply to. Furthermore, interpolation processing is performed on data determined by the code processing processor 109 to be uncorrectable. The D/A converter 13 converts the PCM data into an audio signal Aou.
Convert to t and output.

Next, the detailed configuration of modulation/demodulation section 108 will be explained.

FIG. 3 is a block diagram showing the configuration of modulation/demodulation section 108.

In FIG. 3, 301 is the NRZI modulated reproduction signal R.
NRZI inverse converter that converts FIN to NRZ signal, 30
4 extracts the block synchronization signal 5YNC from the NRZ signal, sends the DSYNC that provides the reference timing to the reproduction timing generator, and erroneously outputs the block synchronization signal 5YNC.
This is a synchronization protection unit that protects D5YNC from occurring even if D5YNC is detected. Further, the synchronization protection unit outputs an out-of-synchronization flag 5YNC when detecting out-of-synchronization.

302 is an S-P converter that performs serial-to-parallel conversion of the NRZ signal using the word clock WDCK generated by the reproduction timing generator, and 303 is an S-P converter that converts the 10-bit data subjected to S-P conversion into 8-bit data. At the same time, for data that does not conform to the 8-10 modulation rule, R
It is an 8-10 decoder that sets the F error flag RFF.

Reference numeral 305 denotes a reproduction timing generation unit that generates timing for demodulation processing using a reproduction clock PCK based on the synchronization detection flag DSYNC sent from the synchronization protection unit 304. The reproduction timing generating section 305
Conversion clock WDCK.

Reproduction word address PWAD for writing demodulated data into RAM section 110 and RAM write request signal WRR
AM and a 5YNC window MASK used by the synchronization protection unit 304 are generated.

306 follows block 5YNCO (3 words, Wl
, W2. P parity check is performed, and only when the RF flag RFF-0 (no error) supplied from the 8-10 decoder 303 and the parity check is OK,
This is a parity check section that sets a parity OK flag PRF. The block format of R-DAT is shown in FIG. 4 fa).

Further, FIG. 4(b) shows the format of W2. The block address BLK in W2 is 7 bits in the main data area and 4 bits in the sub data area. That is, each track has 128 blocks in the main data area and 16 blocks in the sub data area. Furthermore, the MSB of W2 is a sub-area flag that becomes '1' when it is a sub-data area.

FIG. 5 shows the track format of R-DAT.

307 outputs the fetched block address BLK as the reproduction block address PBAD when the parity OK flag PRF=1, and outputs the previous block address PBLK-'+1 as the reproduction block address PBAD when PRF=0. It also detects the continuity of block addresses and sets the block continuity flag BC.
This is a block address detection unit that sends out F.

308 is BCF=1 (block address consecutive).

And when PRF=1, that is, when two valid block addresses are detected in succession, the count is increased and the out-of-synchronization flag 5YNG from the synchronization protection section is set to 1.
The continuous flag counter is cleared when (out of synchronization occurs) or when BCF=O (block address discontinuity) and PRF=1, and the count value of the continuous flag counter reaches a specific value N. BZRVF outputs the block address valid flag BZRVF when
This is a continuous flag counting section consisting of a generation circuit.

309 is an address launch that simultaneously latches the reproduction block address PBAD and the reference address R3ADR output from the reference timing generation section 315 at the timing when BZRVF is output; The phase of the reproduced signal,
This is a correction data generation section that calculates the error between the phase of the reference address outputted by the reference timing generation section 315 and provides phase shift correction data STBLK to the recording timing generation section 316.

Reference numeral 311 is a gate for writing demodulated data into the RAM section 110, and is opened during reproduction by a recording/reproduction switching signal PR.

314 is an 8-10 encoder that performs 8-10 conversion; 31
3 is a P-8 converter that performs parallel-to-serial conversion;
12 is NRZ that performs NRZI conversion on serial data.
It is an I converter, and the output recording signal RFOUT is output from the head.
The signal is supplied to amplifier 105.

Reference numeral 315 is a reference timing generating section that generates fixed timing on a crystal basis based on the cylinder synchronization signal R3CP.

The recording timing generating section 316 generates a recording address RCADR used for reading pre-modulated data from the RAM section, and also generates a clock for 8-10 conversion and parallel-serial conversion. Recording address RCA
DR is phase shift correction data 5T sent from the correction data generation unit 310 based on the cylinder synchronization signal R3CP.
It is generated using BLK as the initial value. In other words, the recording timing for R3CP can be shifted by the phase shift correction data 5TBLK. It also sends Raido MASKT for the 5YNC mask to the synchronization protection section.

317 is an address conversion unit that converts the recording address into a format suitable for the address of the RAM unit; 318 is a unit that switches the reference address R3ADR, the reproduction block address PBAD, and the reproduction word address PWAD using the recording/reproduction switching signal PR, This is an address selector that is supplied as RAM ADR.

Next, a phase shift correction process that can be used for dubbing, splicing recording, etc. will be explained.

As explained in FIGS. 2(a) to (dl), in the playback mode, the servo block 115 controls the phase of the head touch based on the cylinder synchronization signal R3CP, and reproduces the correct phase with respect to R3CP. Signal RFIN
control so that it is obtained.

However, in R-DAT, etc., there are problems such as errors in installing the PC (phase generator) that detects the rotational phase of the cylinder, and when considering compatibility, it becomes a problem that sufficient cylinder phase control is not possible. ing.

Therefore, when the phase of the reproduced signal RFIN deviates with respect to R3CP, the amount of deviation is detected and the initial phase of the recording timing generator 316 can be shifted several blocks before and after R3CP. do. In other words, since the recording timing is generated in accordance with the phase of the playback signal,
The recording track during after-recording can be matched to the original track. Also, when recording splices,
A new recording track can be formed in accordance with the original phase.

First, a method for detecting a phase shift of a reproduced signal will be explained.

FIGS. 6(a) to 6(11) are timing charts showing the process of generating a block address valid flag BZRVF, which is output when a highly reliable block address is detected.

In FIGS. 6(a) to 6(i), PBAD indicates the block address detected by the block address detection section 307.

0, 1, 2, 7, 8.・・・・・・19 is parity O
Indicates the block address of K, (127), (3
), (5) indicates parity NG and indicates an interpolated block address. a.

b is a block where 5YNG is set, that is, a block where an out-of-synchronization has occurred, and C is a block whose block address was incorrectly detected due to a missed parity check.

PRF is a parity OK flag sent by the parity check section 306.

In BCF, the previous block and the current block are blocks.
This is a block continuity flag that is set when addresses are consecutive, and is generated by the block address detection unit 307 by comparing the previous block address and the current block address.

Continuous flag counter (output value: QBC) is BCF-
When PRF=1, that is, when the block addresses are consecutive, it is counted up. Also, BCF-P
At RF-1, that is, when the block addresses are discontinuous, the continuity flag counter is cleared. Also P
When RF=O, that is, when the block address is unknown, the continuous flag counter holds the previous value.

5YNG is detected by the synchronization protection unit 306 when an out-of-synchronization is detected, that is, M times in a row (M=1.2.3
...) This is an out-of-synchronization flag that is set when SYNC is not detected at a specific interval. The continuous flag counter (output value: QBC) is cleared by 5YNG.

Therefore, counter clear signal CNTCR=SYN
When G+BCF-PRF=1, the continuity flag counter is cleared.

BCCK is the counter enable signal CNTEN=B
CF-PRF is punched out with a pulse at a specific timing and is used as a clock for a continuous flag counter, but since the parity OK flag PRF is not set at d, it is not counted up. The block address valid flag BZRVF is a flag that is set when the output values Q and C of the continuous flag counter reach N (N=L2, 3...), and the reproduction block address PBAD and recording address at this time are RCADR is B ZRVF
It is latched on the rising edge of . Here, it is set as N-4, so BZRVF stands at 0 points. In other words,
In a state where there is no synchronization loss, the continuity of block addresses with OK parity is checked, and when BCCK is asserted N times, the last block address is adopted as a highly reliable block address that will not miss parity. ,
The reference address R3ADR at that time is latched and the phase shift is determined.

Next, the phase shift correction process will be explained.

If the phase shift of the reproduced signal with respect to R3CP is ΔADR, then ΔADR = PBAD + OFS - R38D R (1) PBAD: Reproduction block address OFS: Address offset R3^DR = Reference address OFS has a phase shift of ΔADR of '0' The address when
It is Ofse Nodo.

To Δ When DR=0 OFS = R3ADR-PBAD
(2) becomes. The address offset OFS varies depending on which area's block address is used.

FIGS. 7(a) to (fl) show the relationship between the reproduced block address PBAD and the reference address R3ADR in R-DAT.The 0FSO value is defined as follows so as to satisfy equation (2).

Area 2) Also, in Figure 7 (al ~ (fl), SUB P
CM is a signal for identifying the sub data area and main data area, R12CP is a signal for distinguishing between the first half and the second half of a track, and SUBPCM and R1
Based on 2CP, signals of sub data area 1, sub data area 2, and main data area can be extracted. Therefore SUBPCM and R12CP
Since the address offset OFS can be set to a correct value by using , phase shift detection can be realized by using the block address of any of the three areas mentioned above.

On the other hand, the recording timing generating section 316 generates the recording address RCADR based on R3CP, and the initial value of the address is determined based on the phase shift correction data 5TBLK.

8(a) to 8(g) are timing charts showing the operation of the recording timing generator 316. FIG. 8(a)
In ~(g), R3ADR is a reference address starting from the edge of R3CP. Also, when the phase shift correction data 5TBLK=O (block), the recording address RCA
In DR, the O block starts from the edge of R3CP. When 5TBLK=0.5 ()'tfftsuk), R
CADR starts at 0.5 blocks and has a phase advance of 0.5 blocks relative to R3CP. 5TBLK--
When 1,0 (block), RCADR starts from -1,0 block and has a phase delayed by 1.0 block with respect to R,3CP. In other words, the nth track recording address RCADR(n) is RCADR' (n) -R3AD'R+ S T B
It is expressed as L K (n) - (3). Therefore, using equation (1), the phase shift ΔAD of the nth track is
If R(n) is calculated and the phase shift correction data 5TBLK (n+1) of the next track is set to 5TBLK (n+1) - ΔADR(n), the phase of the recording address will follow the phase of the playback signal with a delay of one track. do. For example, when the reproduced signal RFIN is delayed by one block, if STBL K =-1, 0, the phase of the reproduced signal RFIN will match the phase of RCADR.

Therefore, R corrected by S T B L K
By performing after-recording using CADR timing, it becomes possible to record in the same phase as the reproduced signal.

Although independent timing generating sections are used here as the reference timing generating section and the recording timing generating section, if the phase shift correction data S T B LK and the recording address RCADR generated by the recording timing generating section are used, Since the reference address R3ADR can be obtained, the reference timing generation section and the recording timing generation section can be shared. R3ADR can be expressed as R3ADR=RCADR(n)-3TBLK(n) using the phase shift correction data 5TBLK(n) of the nth track and the recording address RCADR(n).

Next, after-recording using the above-described phase shift correction processing will be explained.

FIG. 9 (al to fg) is a timing chart showing the timing of after-recording of the sub data area.

In FIGS. 9(a) to 9(g), it is assumed that the reproduction signal RFIN is delayed by 10 blocks with respect to the cylinder synchronization signal R3CP. 5RPR is a switching signal for the head amplifier, and the head amplifier 105 is in the reproducing state when 5RPR=0, and in the recording state when 5RPR=1. At this time, the sub data area is in recording mode and the main data area is in playback mode. Therefore, phase shift detection processing is performed using the block address of the main data area.

Since the phase of the recording address RCADR is delayed by 10 blocks due to the phase shift correction process described above, the recording signal RFOUT is generated with a phase delay of 10 blocks accordingly. Also, head amplifier switching signal 5R
PR is also generated based on RCADR, so 10
Block is behind.

Also, write request signal WRRAM to RAM and read request signal RDl? AM also has a playback signal and R'CA, respectively.
Delayed by 10 blocks to match DR.

Therefore, the recording pattern after after-recording is continuous, and the ATF signal used for servo control is not erased, so stable reproduction is possible.

Also, when performing after-recording in the main data area, set 5RPR = 1 in the main data area to enter recording mode, and use the block address in the sub data area to detect the phase shift. .

Next, spliced recording using the above-described phase shift detection method will be explained.

FIG. 10 is a block diagram showing the configuration of a modulation/demodulation section of a second embodiment of the recording/reproducing apparatus of the present invention.

Note that explanations of parts that overlap with FIG. 3 showing the configuration of the modulation/demodulation section in the first embodiment of the present invention will be omitted.

Further, the configuration of the entire system is similar to that shown in FIG. 1, which shows the configuration of the first embodiment of the present invention.

In FIG. 10, 1021 is the correction data generation unit 10
A correction data storage section 1021 stores phase shift correction data 5TBLK sent from 10, and a recording phase storage section 1021 generates recording phase data RCBLK that determines the initial phase of the reference timing generation section 1015 based on the stored correction data. This is a data generation section.

The operation of splice recording will be explained using FIG. 11(a) (bl).

Splice recording is a function of recording a new track following a previously recorded track.

At this time, if the spacing between the new and old tracks and the track phase in the head trace direction are not continuous, the trunking servo will be disconnected at the joint between the old and new tracks, so it is necessary to tell the spacing and phase of the tracks.

FIG. 11 shows a recording pattern during spliced recording. Figure 11(a) shows a case where the old track (before rack n) is out of phase, and the phase is ignored and spliced recording is performed using the center phase of the recording system. Since the phase of the tracks (after track n+1) changes rapidly at point A, the track phase becomes discontinuous.

Figure 11 (bl) does not directly start recording from the center phase when starting spliced recording, but gradually changes the track phase toward the center phase, so large phase discontinuities do not occur. do not.

The operation at this time will be explained.

The recording and reproducing apparatus of the present invention is in the reproducing mode for up to n tracks according to instructions from the system control unit 116,
During n-track reproduction, the correction data storage unit 1020 stores phase shift data 5TBLK (n).

For the next track, the system control unit 116 issues a recording mode instruction and recording starts, but the recording phase data generation unit 1021 generates the following recording phase data RCBLK(n) for the subsequent tracks. do.

RCBLK (n+1) -3TBLK(n) (m
-4/m) -(5) (i = 1.2...m) Therefore, when i = m, RCBLK (n + m) = 0, so at the mth track after recording starts, the recording phase is Become a center. In this case, the recording phase always converges to a predetermined value, so no matter how many times recording is repeated, phase errors do not accumulate.

Also, if the accuracy of the recording phase data PCBLD (n) is sufficiently high, RCBLK (n+4) -5TBLK (n)
(6) (i = 1.2...m).

Note that the recording phase data generation section 1021 can be easily realized using a microprocessor or the like.

Effects of the Invention As described above, the recording/reproducing apparatus of the present invention includes a recording phase detection means for detecting the recording phase of the first recording track, and a recording phase detecting means for detecting the recording phase of the first recording track. By providing a splicing recording control means that controls the phase, the phase of the reproduced signal can be detected and the phase of the recording address can be matched to the reproduced signal, so after recording, splicing recording, etc. that match the phase of the reproduced signal can be performed. It can be done.

In addition, by using a recording address that matches the phase of the reproduced signal, it is possible to create a window that follows the phase of the reproduced signal, so a window can be established at the timing when block synchronization signal 5YNC is expected to arrive, and at other timings. It is possible to prevent erroneous detection of 5YNC that occurs.

Furthermore, when data is recorded in several areas like R-DAT, for example, sub-data
The area has a sub area window and the main data area has a main area window.
This can prevent false positives from occurring due to the intake of unnecessary data. In addition, since these windows follow the phase of the playback signal, there is less chance of masking necessary data, and all necessary data can be captured and unnecessary data can be discarded, increasing the reliability of playback processing. improves.

[Brief explanation of the drawing]

FIG. 1 shows the first embodiment of the present invention. A block diagram showing the configuration of a recording/reproducing apparatus in the second embodiment, FIGS. 2(a) to 2(d)
3 is a timing chart showing the operation of the servo block, FIG. 3 is a block diagram showing the configuration of the modulation/demodulation section of the recording/reproducing apparatus according to the first embodiment of the present invention, and FIG. 4 fa) (b
) is a block diagram showing the block format of R-DAT, FIG. 5 is a block diagram showing the track format of R-DAT, and FIGS. 6(a) to (11) show the block address detection process. The timing chart in FIG. 7 (al~ge) is a timing chart showing the relationship between the reproduced block address and the reference address, and the timing chart in FIG. 8 (81~()
g) is a timing diagram showing the operation of the recording timing generator.
9 (al to (g)) are timing charts showing the timing of after-recording of the sub data area, and FIG. Block diagram showing the configuration, 1st
FIGS. 1(a) and 1(b) are explanatory diagrams showing recording patterns during spliced recording. 100a, 100b...Head, 101.
...Cylinder, 108...Modulation/demodulation section, 1
15... Servo block, 307...
・Block address check section, 308...
・Continuous flag counter, 309...Address latch, 310...Correction data generation unit, 31
5...Reference timing generation section, 318...
...Block Address Ranch, 1020...
- Correction data storage section, 1021... recording phase data generation section.

Claims (3)

[Claims] (1) A recording phase detection means for detecting the recording phase of the first recording track, and a splicing recording control means for controlling the recording phase of the second recording track based on the recording phase of the first recording track. A recording/reproducing device characterized by: (2) The recording phase detecting means detects a reproduction block address from a reproduction signal divided into blocks.
an address detection section; a reference timing generation section that generates a reference address independent of the playback signal; The recording/reproducing apparatus according to claim 1, further comprising phase shift detection means for detecting a phase shift and transmitting phase shift correction data. (3) The splicing recording control means includes a correction data storage unit that stores the phase shift correction data, and a recording unit that generates recording phase data that controls the recording phase of the second recording track based on the stored correction data. Claim 1, characterized in that it comprises a phase data generation section and a recording timing generation section whose phase is determined by the recording phase data.
) The record generating device described in section 2.