JPH01123459A - Input protecting circuit - Google Patents

Abstract

PURPOSE:To realize input protection of high breakdown voltage, by absorbing surge voltage with load-resistance-coupled P-type and N-type MOS transistors arranged in the vicinity of an input pad, and receiving an input signal with a protecting resistance of a drain region. CONSTITUTION:The threshold voltage of a P-type transistor 104 is designated as VTP. When the electric potential of a signal VIN, input to a signal input pad 103 from the outside is higher than a power supply voltage VDD, and a relation VIN=VDD+¦VTP¦ is satisfied, the P-type transistor turns to ON state, and functions as a clamp circuit in the manner in which potential of the side connected to a metal wiring 3 becomes (VDD+¦VTP¦). After an applied surge voltage is received by protecting transistors 104, 105, an input signal is received by a protecting resistance of a drain region surrounded by the gate part of the protecting transistor 105. Thereby eliminating physical structure as a cause of PN junction destruction between a channel stopper region and a protecting region of impurity diffusion, and realizing an input protecting circuit of high quality.

Description

[Detailed description of the invention] Industrial applications The present invention relates to an input protection circuit.

BACKGROUND OF THE INVENTION In recent years, technological advances regarding MO8 integrated circuits have been remarkable. As microfabrication technology reaches the submicron level and there is a growing demand for faster data processing speeds and lower power consumption for the entire device, current consumption in MO3 integrated circuits only occurs during switching operations of internal transistors. Complementary MO8, so-called C
Integrated circuits with MO8 configuration are becoming mainstream in the future.

However, as microfabrication progresses, the thickness of the silicon dioxide (Si(h) film that forms the isolation region for isolating the active regions of transistors, etc.) becomes thinner than conventional ones. In order to prevent the threshold voltage from decreasing in the isolation region, an impurity called a channel stopper is diffused into the lower part of the isolation layer before the isolation layer is formed. These changes in process conditions are causing a decline in the surge withstand voltage of conventional input protection circuits.

The conventional input protection circuit, as shown in Figure 2,
oo) There is a pad 201, a ground (GND) pad 202, and a signal input pad 203.
An N-type diffusion region 204, which functions as a protection resistor and an N-type protection diode, is connected to a P-type protection diode 205 and an N-type protection diode by a metal wiring 13.
type protection diode 206 in combination with input protection means.

Problems to be Solved by the Invention In the protection circuit having this configuration, a particular problem arises when a positive surge voltage is applied between the input signal terminal and the ground terminal. If a negative surge voltage is applied between the input signal terminal and the ground terminal, connect an N-type protection diode 20.
4 operates in the forward direction and can absorb surge charges from the pad without going through a resistor. However, in the case of positive polarity, the diffusion region 204 acts as a protection resistor, and the surge charge is absorbed by the P-type protection diode 205. At this time, the diffusion region 204 acts as a protection resistor.
Since a surge voltage is directly applied to the input pad side of the input pad, PN junction breakdown is likely to occur under reverse bias. According to the results of surge application experiments, this destruction occurs particularly in a short path from the ohmic contact between the metal wiring 12 and the diffusion region 204 to the channel stopper region having a high impurity concentration. This phenomenon occurs because the applied surge electric field is concentrated on this portion due to the concentration difference between the impurity concentration of the substrate or well and the impurity concentration of the channel stopper region.

Means for Solving the Problems The present invention solves the problem that electric field concentration occurs between the highly concentrated channel stopper region and the surface layer of the diffusion region forming the protective resistor when a surge voltage is applied, and the junction is damaged. In order to prevent destruction, it has a P-type protection transistor whose gate electrode and source electrode are commonly connected, and an N-type protection transistor whose gate electrode and source electrode are commonly connected, and one of the protection transistors has a P-type protection transistor whose gate electrode and source electrode are commonly connected. A protection resistor is provided by a narrow drain region in the gate electrode portion of the transistor.

According to this invention, surge voltage is absorbed by the load resistance-coupled P-type and N-type MOS transistors arranged near the input pad, and input signals are received by the protective resistor in the drain region, so that junction breakdown does not occur. First, it is possible to perform a high voltage input protection function.

Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

- The embodiment of the invention shown in FIG. Ground pad (GND) 102. It has a signal input pad 103, and further includes a P-type protection transistor 104 connected from the input pad 103 to the drain part via the metal wiring 3, and a P-type protection transistor 104 connected to the input pad 103 and the drain part via the metal wiring 3. N-type protection transistor 10
5, and a protective resistor 106 connected to the drain region of the N-type protective transistor 105 between the metal wiring 3 at one end and the metal wiring 4 at the other end so as to act as a series resistor. Ru. Note that the drain region of the N-type protection transistor 105 is preferably surrounded by a gate electrode portion, that is, a channel region.

Next, the operation of the embodiment of the present invention configured as described above will be explained using FIG.

First, when the potential of the signal VIN externally input to the signal input pad 103 is higher than the power supply voltage VOO, and the threshold voltage of the P-type transistor 104 is VTP, VIN=VDD+ l VTP l ・
...If (1) is satisfied, P-type transistor 1
04 is turned on, and the P-type transistor 10
It functions as a clamp circuit so that the potential on the side connected to the metal wiring 3 of No. 4 becomes (Voo+ l VTP l ). Next, in the N-type protection transistor, the potential of the signal VIN input to the signal input pad 103 is lower than the ground potential V GND, and the threshold voltage of the N-type transistor 105 is opposite to the case of the P-type transistor described above. When is VIN, VINi; VGND VTN ・
...” If (2) is satisfied, the N-type transistor 10
5 is turned on, and the N-type transistor 105
It functions as a clamp circuit so that the potential on the side connected to the metal wiring 3 becomes (VGND I VTN l ). Next, the protection resistor 106 is configured to temporarily reduce the potential of the metal wiring 3 to V in a transient state in which the protection transistors 104 and 105 function as a clamp circuit.
oo+ l VTP Higher than l or VGND
This is inserted to prevent damage to the gate oxide film due to the potential being applied directly to the gates of transistors 107 and 108 in the input stage when the potential becomes lower than I VTN l, and prevents current from passing. The accompanying potential drop protects the gates of input stage transistors 107 and 108.

Effects of the Invention The difference between the present invention and the conventional example is that in the conventional example shown in FIG.
However, since the surge voltage is directly applied to the input pad side of the diffusion region 204 that acts as a protection resistor, the metal wiring 12 from the input pad and the diffusion region 204 However, the present invention has the shortest distance from the contact part that makes an ohmic connection to the channel stopper region with a high impurity concentration, which tends to cause PN junction breakdown under reverse bias. First, the protection transistors 104 and 105 receive the surge voltage, and then the protection transistor 105 receives the surge voltage through the protection resistor formed by the drain region surrounded by the gate. A high-quality input protection circuit can be realized by eliminating a physical structure that causes PN junction breakdown between protection resistance regions due to diffusion.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example of an input protection circuit. 1.2.3, 4.10.11, 12.13 Old... Metal wiring, 101... Power pad, 102 Old...
Ground pad, 103... Input pad, 104.
Old...P-type protection transistor, 105...Old...N-type protection transistor, 106...Protection resistor using the drain region of an N-type protection transistor, 107.108.
Old... Input stage transistor, 201... Power supply pad, 202... Ground pad, 203...
...Input pad, 204...Protection resistor and N-type protection diode, 205...P-type protection diode, 206...N-type protection diode, 207.2
08... Input stage transistor. Name of agent: Patent attorney Toshio Nakao and one other person Figure 1 Figure 2

Claims (1)

[Claims] A P-type protection transistor having a gate electrode and a source electrode commonly connected, and an N-type protection transistor having a gate electrode and a source electrode commonly connected, and a protection resistance formed by the drain region of one of the protection transistors. An input protection circuit characterized by: