JPH01118951A - Serial interface circuit - Google Patents

Abstract

PURPOSE:To realize the transmission/reception of the 2-bit data with a 1-cycle clock pulse and to attain the transfer of different data at one time up to two sets of devices between control systems by securing the input or output of serial data alternately at every bit between 1st and 2nd shift registers. CONSTITUTION:A serial interface circuit consists of a 1st shift register 5 which supplies the serial input data received from an input terminal 1 at every bit synchronously with the leading edge of a clock signal, an inverter 4 which inverts the clock signal, and a 2nd shift register 6 which supplies the serial input data at every bit synchronously with the leading edge of the clock signal inverted by the inverter 4. Both registers 5 and 6 shift out the stored parallel data at every bit synchronously with the leading and the trailing edges of the clock signal respectively. Thus it is possible to transmit/receive the 2-bit data with a 1-cycle clock pulse and also to transfer data simultaneously between two systems.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a serial interface circuit that serially inputs and outputs data, and more particularly to a serial interface circuit that facilitates increasing the transfer rate of serial data.

2. Description of the Related Art A conventional serial interface circuit employs a method of transmitting and receiving data bit by bit in synchronization with a clock.

FIG. 6 is a diagram showing an example of the configuration of a conventional serial interface circuit. It is assumed that this serial interface circuit handles 8-bit/word data.

Serial input data is input to the serial input terminal 13, and is transferred bit by bit to the shift register 16, for example, the most significant bit (hereinafter referred to as MSB) in synchronization with a clock (hereinafter referred to as τn) input to the clock input terminal 14. recorded).

The operation when serial data is input to this shift register 16 is shown in FIGS.
a) to (company). That is, first, as shown in FIG. 7(X), when CI of Ttff is input to the clock input terminal 14, the shift register 16 is synchronized with this as shown in FIG. 7(a). Input data DO is stored in MS B16-1. Next, as shown in FIG. 7(X), when the next I C2 is input to the clock input terminal 14, the MSB of the shift register 16 is input as shown in FIG. 7(b).
The data DO of 16-1 is moved to the next stage shift register 16-2 in the lower direction, and at the same time, 1 bit of the next input data D1 is stored in the MSB 16-1.

Thereafter, as shown in FIGS. 7(C) to 7(C), input data is sequentially introduced into the shift register 16 at the rising edge of each 5r clock. Therefore, by inputting the lower π pulse eight times to the clock input terminal 14, 8 bits of serial input data can be introduced into the shift register 16.

On the other hand, the contents of the shift register 16 (16-1 to 16-8
), the contents of, for example, the least significant bit (hereinafter referred to as LSB) of the shift register 16 are shifted out to the serial output terminal 15 in synchronization with SCK, as in the case of input. The remaining stored serial output data is moved to the next stage shift register on the lower side.

FIGS. 8(X), (G), and (a) to (FIG. 8) are diagrams showing the operation of outputting serial data from this shift register 16.

As shown in FIG. 8(X), when C1 at -5τ= is input to the clock input terminal 14, the LSB16 of the shift register 16 is synchronized with this as shown in FIG. 8(a).
-8, the serial output data DO is shifted out and output from the serial output terminal 15. At the same time, the remaining serial output data stored in the shift register 16 is moved to the next shift register on the lower side. Hereinafter, as shown in FIGS. 8 and 8, output data is sequentially shifted out from the shift register 16 in synchronization with the falling edge of ττπ. Therefore, the pulse on -tea is 8
By inputting the data twice, the shift register 16 outputs 8 bits of serial output data.

The contents of the serial data input/output to this serial interface circuit are determined by any data processing device (display device, arithmetic device, printing device, etc.) that incorporates this circuit.
Each is processed as appropriate.

Problems to be Solved by the Invention In the conventional serial interface circuit as described above, one bit of data is transmitted and received for one cycle of clock pulses. Therefore, when transferring a large amount of data, clock pulses corresponding to the number of data bits are required, and an operation period corresponding to the clock pulse period is also required. This has the disadvantage that it takes a long time.

In addition, when configuring a control system using three or more devices having at least a serial interface circuit,
Becomes the data sender and receiver when data is transferred 1
Devices other than the paired device cannot perform data transfers. Therefore, other devices have to wait for the completion of the transfer, which also has the drawback of inefficient data transfer time between systems.

An object of the present invention is to solve the above-mentioned drawbacks of the prior art, and to enable transmission and reception of 2 bits of data with one cycle of clock pulses, and to enable simultaneous transfer of different data to two sets of devices between control systems. The object of the present invention is to provide a novel serial interface circuit.

Means for Solving the Problems According to the present invention, in a serial interface circuit that inputs or outputs serial data in synchronization with a clock signal and stores the serial data as parallel data, it is possible to synchronize with the rising edge of the clock signal. a first shift register that sequentially inputs or outputs serial data bit by bit in synchronization with the falling edge of the clock signal; and a second shift register that sequentially inputs or outputs serial data bit by bit in synchronization with the falling edge of the clock signal. A serial interface circuit is provided, wherein the first and second shift registers are configured to alternately input or output serial data bit by bit.

Operation The serial interface circuit of the present invention includes a first shift register that inputs serial input data from an input terminal bit by bit in synchronization with the rising edge of a clock signal, an inverter that inverts the clock signal, and an inverter that inverts the clock signal. , a second shift register that introduces serial input data bit by bit in synchronization with the rising edge of a clock signal, and the first shift register and the second shift register each input the stored parallel data. Data is shifted out bit by bit in synchronization with the falling and rising edges of the clock signal.

Furthermore, it includes a selection means for selecting the output data from the first shift register and the output data from the second shift register while synchronizing with the high level or low level of the clock signal, and outputs the serial output data from the selection means. It consists of output through a terminal.

The present invention will be described in more detail below with reference to the drawings, but what is disclosed below is only one embodiment of the present invention and does not limit the technical scope of the present invention in any way.

Embodiment FIG. 1 is a block diagram showing an embodiment of a serial interface circuit constructed according to the present invention. still,
This embodiment is configured as a circuit that inputs 8-bit/word serial input data and outputs parallel data as 8-bit serial data.

Serial input terminal 1 is connected to the first shift register 50M5
B5-1 and MSB6-1 of the second shift register 6.

Serial clock terminal 2 has clock signal -5T
is input. Here, mτ7 is a shift clock signal for the shift register 5, and furthermore, after passing through the inverter 4, the signal π becomes an inverted signal scK, which is input to the shift register 6 as a shift clock.

Output of LSB5-4 of shift register 5 and inverter 4
The output of is input to the AND circuit 7, and the shift register 6
The output τπ of LSB 6-4 is input to the AND circuit 8. Furthermore, the output of the AND circuit 7 and the output of the AND circuit 8 are input to an OR circuit 9, and the output of the OR circuit 9 is connected to the serial output terminal 3.

FIGS. 2(X) to (Z) and (a) to (5) show that 1. Shift registers 5 and 6
FIG. 2 is a diagram illustrating an operation when storing serial data in a computer.

The first falling edge of the clock signal X is shown in Figure 2 (y
), it is inverted by the inverter 4 and becomes the first rising edge C1 of the clock signal SCK. Therefore, at this time, the shift register 5 does not operate, and the shift register 6 receives the input input from the input terminal 1 in synchronization with the rising edge C1 of the clock signal SCK, as shown in FIG. 2(a). One bit of serial data DO is stored in the shift register 6-1.

Next, as shown in FIG. 2 (X), in synchronization with the first rising edge of the lock signal - π, the input serial data input from the input terminal 1 as shown in FIG. The next bit D1 is shift register 50M5B5-1
is stored in

Furthermore, the next rising edge C2 of SCK shown in FIG. 2(y)
As shown in FIG. 2(C), the input data DO stored in the MSB 5-1 of the shift register 5 is shifted by 1 bit to the lower side and stored in the shift register 5-2, and the serial input data DO is Data D2 is stored in MSB6-1 of shift register 6.

Hereinafter, as shown in FIG. 2(d) to color), the input data is stored in the shift registers 5 and 6 at 17 and at the rising edge of SCK.

In this manner, this serial interface circuit including shift registers 5 and 6 can store 8 bits of 8-bit serial input data during the input period of the x pulse after four completions.

Note that by reading the contents of the shift registers 5 and 6 in parallel, 8-bit serial data can be converted to 8-bit parallel data.

FIGS. 3(X) to (2) and (a) to 3(a) are diagrams for explaining the operation of the circuit shown in FIG. 1 when outputting stored parallel data.

As described above, in the serial interface circuit according to the present embodiment, 8-bit data is stored every other bit in the shift registers 5 and 6, respectively.

The first falling C1 of tTππ shown in FIG. 3(p) is
At the first rising edge of SCK, data is inputted to the shift register 6 via the inverter 4 as "D" from LSB5-4 of the shift register, as shown in FIG. 3(a).
O is output, and this output data DO is input to AND7.

Furthermore, by the first rising edge C1 of T under the clock signal, data D1 is output from LSB5-4 of the shift register 5, as shown in FIG. 3(b), and this output data DI is input to AND8, and , At this time, the 3-bit data stored in the shift register 5 is:
Shift 1 bit to the lower side.

Furthermore, due to the rising edge C1 of SCK shown in FIG. 3(6), data D2 is outputted from LSB6-4 of the shift register 6 as shown in FIG. 3(C), and is simultaneously stored in the shift register 6. The remaining 2 bits of parallel data are shifted 1 bit to the lower order side.

Similarly, output data is output one bit at a time from the shift register 5 and the shift register 6 at each rising edge of πX and SCK shown in FIGS. 3(P) and (Q).

Each LSB5 of these shift registers 5 and 6 = 1.6
The output data D output from -1 is the clock signal -5
It is controlled by an AND circuit 7 and an AND circuit 8 to which τAK is input. That is, as shown in Table 1,
Only when π or SCK is at high level (VDD level), the contents of shift registers 5 and 6 are output from AND7 and AND8, and when π or SCK is at low level (GND level), the contents of shift registers 5 and 6 are output
The outputs of AND7 and AND8 are at low level regardless of the data output from.

As shown in Table 1, in this circuit, the output of the shift register 5.6 is alternately selected and outputted by the AND circuit 7.8 and the OR circuit 9, and the pulse of x is output at τ. By inputting the signal four times, 8-bit data is output from the shift register 5.6. In this way, the data output from the OR circuit 9 is output from the serial output terminal 3 as serial output data.

Note that this serial output data output from the serial output terminal 3 is transferred to another device equipped with the serial interface circuit of the present invention and introduced as serial input data. In addition, when outputting serial data from the serial output terminal 3, the serial data is output from the serial terminal before being output from the serial terminal so that the shift register on the receiving side can reliably latch the serial data transferred at a predetermined clock signal timing. It is also preferable to output the signal after being delayed by a delay circuit.

FIG. 4 shows three devices M1, M2, and
FIG. 2 is a block diagram schematically showing the configuration of a control system (consisting of a display system, a printing system, an arithmetic system, etc.) configured by M3.

In this system, the serial output terminal Sol of device M1
and serial input terminals i2 and SI3 of devices M2 and M3 are connected via wiring 11. Also,
Clock input terminal 5CKI of each device M1, M2, M3,
5CK2.5CK3 are connected via wiring 10, and these clock input terminals 5CKI, 5CK2.5CK
The serial interface circuit of each device is configured to operate by inputting X as a system clock signal from the outside to 3.

FIGS. 5(a) to 5(d) are diagrams for explaining the operation of the apparatus shown in FIG. 4 during data transfer.

The signal t1 shown in FIG. 5(a) corresponds to the clock signal -5T7 required for one data transfer. In response to this tarlock signal, the serial interface circuit in device M1 stores parallel data A (AO~A3) and B (BO~B) of 4 bits each in its pair of shift registers.
3) can be stored and output simultaneously.

When data is transferred from device M1 to devices M2 and M3, serial data A is stored in one of the shift registers provided in devices M2 and M3, and serial data B is stored in the other shift register provided in devices M2 and M3, respectively. Ill be. Here, if data A stored in one shift register is valid data for device M2, and data B is valid data for device M3, then device M2 is one of the pair of shift registers. Only the contents of the shift register storing data A are read as parallel data, while device M3 reads only data B stored in the other shift register as parallel data. In this way, it becomes possible to perform two different types of data transfer simultaneously.

Although the present embodiment has been described as an 8-bit serial interface circuit, it goes without saying that the present invention is not limited to this, and may adopt a 4-bit, 16-bit, or 32-bit configuration.

Effects of the Invention As is clear from the above explanation, according to the serial interface circuit of the present invention, one period of clock pulse can
It becomes possible to send and receive bit data, and high-speed data processing is realized.

Furthermore, data can be transferred simultaneously between two sets of systems, and, for example, data transfer time between control systems can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a diagram schematically showing the configuration of an embodiment of a serial interface circuit according to the present invention, and FIGS. 3], (q), (X) to (Z), and (a) to (sha) are the same as those in FIG. 1. FIG. FIG. 4 is a block diagram schematically showing the configuration of a control system using a device equipped with the serial interface circuit shown in FIG. 1. FIG. Yes, a copy of the specification; Figures 5(a) to (d) are based on the control system xfh shown in Figure 4.
FIG. 6 is a diagram schematically explaining the configuration of a conventional serial interface circuit, and FIGS. 7(X), (y) and (a) (3), (y) and (a) are diagrams for explaining the operation of the serial interface circuit shown in FIG. 6 when inputting serial data.
) to (company) are diagrams illustrating the operation of the serial interface circuit shown in FIG. 6 when outputting serial data. [Main reference numbers] 1.13... Serial data input terminal, 2
．． 14... Serial clock input terminal,
3.15... Serial data output terminal, 4
・・・・・・・・・・・・Inverter, 5.6.16・
・・・ Shift register, 7.8・・・・・・・・・AN
D circuit, 9...OR circuit Patent applicant: NEC IG Microcomputer System Co., Ltd.

Claims (1)

[Claims] In a serial interface circuit that inputs or outputs serial data in synchronization with a clock signal and stores the serial data as parallel data, the serial data is input or output bit by bit in synchronization with the rising edge of the clock signal. A first shift register that sequentially inputs or outputs serial data, and a second shift register that sequentially inputs or outputs serial data bit by bit in synchronization with the falling edge of the clock signal, the first and second shift registers A serial interface circuit characterized in that a register is configured to alternately input or output serial data bit by bit.