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JPH01117386A - Compound semiconductor thin film manufacturing method - Google Patents

Compound semiconductor thin film manufacturing method

Info

Publication number
JPH01117386A
JPH01117386A JP27552887A JP27552887A JPH01117386A JP H01117386 A JPH01117386 A JP H01117386A JP 27552887 A JP27552887 A JP 27552887A JP 27552887 A JP27552887 A JP 27552887A JP H01117386 A JPH01117386 A JP H01117386A
Authority
JP
Japan
Prior art keywords
thin film
substrate
layer
zn5e
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27552887A
Other languages
Japanese (ja)
Inventor
Takashi Takamura
高村 孝士
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP27552887A priority Critical patent/JPH01117386A/en
Publication of JPH01117386A publication Critical patent/JPH01117386A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/2205Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers
    • H01S5/2211Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure comprising special burying or current confinement layers based on II-VI materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/20Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/223Buried stripe structure
    • H01S5/2231Buried stripe structure with inner confining structure only between the active layer and the upper electrode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01SDEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00Semiconductor lasers
    • H01S5/30Structure or shape of the active region; Materials used for the active region
    • H01S5/32Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures
    • H01S5/323Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
    • H01S5/32308Structure or shape of the active region; Materials used for the active region comprising PN junctions, e.g. hetero- or double- heterostructures in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser emitting light at a wavelength less than 900 nm

Landscapes

  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Semiconductor Lasers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、■−■族化合物半導体超格子薄膜の選択的な
形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for selectively forming a superlattice thin film of a ■-■ group compound semiconductor.

〔従来の技術〕[Conventional technology]

セレン化亜鉛(ZnSe)、硫化亜鉛(ZnS)等、お
よびこれらの混晶より成るII −VI族化合物半導体
は、広い禁制帯幅、高比抵抗、低屈折率といった他の材
料系にはない特徴を有しており、これらの特徴を生かし
て、例えばZn5e薄膜はAlGaAs系半導体レーザ
素子の電流狭窄および光閉じ込め層として利用されてい
る。第4図は岩野らにより応物学会講演予稿集(昭和6
2年春季、28p−ZH−8)に発表された、Zn5e
薄膜層で埋め込まれたAlGaAs半導体レーザ素子の
構造断面図を示している。リプ401を埋め込むように
Zn5e薄膜層402が形成されている。
Group II-VI compound semiconductors made of zinc selenide (ZnSe), zinc sulfide (ZnS), etc., and their mixed crystals have characteristics that other material systems do not have, such as a wide bandgap, high specific resistance, and low refractive index. Taking advantage of these characteristics, for example, Zn5e thin films are used as current confinement and optical confinement layers in AlGaAs semiconductor laser devices. Figure 4 is a collection of lecture proceedings by the Society of Applied Physics (1939) by Iwano et al.
Zn5e, announced on Spring 2018, 28p-ZH-8)
1 shows a cross-sectional view of the structure of an AlGaAs semiconductor laser device embedded with a thin film layer. A Zn5e thin film layer 402 is formed to bury the lip 401.

またリプ上面403は電極を形成するために、Zn5e
薄膜層を形成せず、ストライプ状に露出している。この
構造のように、半導体基板上に選択的にZn5e薄膜層
を形成したい場合、従来技術では、まず全面にZn5e
薄膜層を堆積した後、フォトエツチング方法でレジスト
等でマスクを施し、その後取り除きたい部分のZn5e
薄膜膜層をエツチング除去していた。
In addition, the upper surface 403 of the lip is coated with Zn5e to form an electrode.
It does not form a thin film layer and is exposed in stripes. When it is desired to selectively form a Zn5e thin film layer on a semiconductor substrate as in this structure, in the conventional technology, the Zn5e thin film layer is first deposited on the entire surface.
After depositing the thin film layer, mask it with a resist or the like using a photo-etching method, and then remove the Zn5e in the area that you want to remove.
The thin film layer was removed by etching.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、前述の従来技術の場合、第一にZn5eとAl
CaAs系とでは大きな格子定数の差と、大きな熱膨張
係数の差があるため、半導体レーザ活性層にストレスが
かかり、AlGaAs系により゛製作された半導体レー
ザに比べると寿命が短かくなるという問題点があった。
However, in the case of the above-mentioned prior art, firstly Zn5e and Al
Since there is a large difference in lattice constant and thermal expansion coefficient between the CaAs system and the semiconductor laser active layer, stress is applied to the semiconductor laser active layer, resulting in a shorter lifespan compared to semiconductor lasers manufactured using the AlGaAs system. was there.

また、第二に活性層部と電極ストライプとの間でセルフ
ァラインにすることは困難で、位置ずれが起こる可能性
があり素子の構造及び特性の再現性が不十分であるとい
った問題点があった。また第二にZn5e薄膜層のエン
チングが非常に難しく、良好なエツチングを行うには工
程が複雑になり生産性が悪くなることや、エツチング後
の表面に凹凸が多く発生し基板との界面特性が低下する
といった問題点があった。
Second, it is difficult to form a self-alignment line between the active layer and the electrode stripes, which may cause misalignment, leading to problems such as insufficient reproducibility of the structure and characteristics of the device. Ta. Secondly, etching the Zn5e thin film layer is very difficult, and the process is complicated to achieve good etching, which reduces productivity. Also, the surface after etching has many irregularities, which deteriorates the interface characteristics with the substrate. There were problems such as a decline in

そこで本発明は、これらの問題点を解決するため、格子
定数の差や熱膨張係数の差に起因するストレスを緩和し
、セルファインが可能で再現性が良く、表面の凹凸のな
い良好なn −VIl超超格子薄膜選択的な形成方法を
提供するところにある。
Therefore, in order to solve these problems, the present invention alleviates the stress caused by the difference in lattice constants and thermal expansion coefficients, enables cell fine processing, has good reproducibility, and has a good n-type structure with no surface irregularities. - A method for selectively forming a VII supersuperlattice thin film is provided.

〔問題点を解決するための手段〕[Means for solving problems]

上記問題点を解決するため、本発明の半導体薄膜の成長
方法は、半導体基板表面上の一部にマスクを製造する手
段と、前記半導体基板表面上に■−■族化合物半導体超
格子薄膜を製造する手段を含むことを特徴とする。
In order to solve the above problems, the method for growing a semiconductor thin film of the present invention includes means for manufacturing a mask on a part of the surface of a semiconductor substrate, and manufacturing a thin film of a ■-■ group compound semiconductor superlattice on the surface of the semiconductor substrate. It is characterized in that it includes means for.

〔実施例〕〔Example〕

本発明を実施例に基づきさらに詳述する。 The present invention will be further explained in detail based on Examples.

(実施例−1) 本発明の第一の実施例として、ダブルへテロ接合上部に
形成されたリブをZn5ei膜層で埋め込み電流狭窄お
よび光閉じ込め用としたZn5e埋め込みAIGaA、
s半導体レーザ素子の製作工程の一部を説明する。第1
図(a)〜(c)は第一の実施例を説明するもので、素
子の製造工程途中の基板の断面概略図である。第1図(
a)はZn5e  Zn5o、+zSeo、as歪超格
子薄膜層を形成する直前の基板断面概略図である。(1
00)面方位のn形GaAs基板101上に1. 5μ
m厚のn形A 1 o、s G a o、s A Sク
ラッド層102.0.1em厚のノンドープA I o
、 +sG a o、 ssA s活性層103.1.
5μm厚のP形A1o、5Gao、sAsクラッド層1
04.0.5μm厚のP形GaAsコンタクト層105
を順次積層したDH構造を有する基板を準備する。次に
そのDH基板表面にCVD法により3000人の5in
2を埋積し、フォトエツチング法で幅5μmのストライ
イブ状の5in2マスク106を形成する。その後、5
inzをマスクにしてP形りラッド層の途中まで基板の
エツチングを行いリブ107を形成する。典型的なリブ
の形状は上部の幅が5μm、下部が3.5μm、高さが
1.6μmである。このリブを埋め込むために次にZn
’5e−ZnSo。
(Example-1) As a first example of the present invention, a Zn5e-embedded AIGaA was used in which the rib formed on the upper part of the double heterojunction was buried with a Zn5ei film layer for current confinement and optical confinement.
A part of the manufacturing process of the S semiconductor laser device will be explained. 1st
Figures (a) to (c) illustrate a first embodiment, and are schematic cross-sectional views of a substrate in the middle of an element manufacturing process. Figure 1 (
a) is a schematic cross-sectional view of a substrate immediately before forming a Zn5e Zn5o, +zSeo, as strained superlattice thin film layer; (1
1.00) on an n-type GaAs substrate 101 with a plane orientation of 1. 5μ
m-thick n-type A 1 o, s G a o, s A S cladding layer 102.0.1 em-thick non-doped A I o
, +sG ao, ssA s active layer 103.1.
5μm thick P type A1o, 5Gao, sAs cladding layer 1
04.0.5 μm thick P-type GaAs contact layer 105
A substrate having a DH structure in which the following are sequentially laminated is prepared. Next, 3,000 5-in.
2 is buried, and a stripe-shaped 5in2 mask 106 with a width of 5 μm is formed by photoetching. After that, 5
Using inz as a mask, the substrate is etched to the middle of the P-shaped rad layer to form ribs 107. A typical rib shape is 5 μm wide at the top, 3.5 μm at the bottom, and 1.6 μm high. Next, to embed this rib, Zn
'5e-ZnSo.

1□SeO,1l11歪超格子薄膜のエピタキシャル成
長を行う。リブ上にZ n S e  Z n S11
.12S eo、ea歪超格子薄膜が堆積しないように
、5in2マスク106をそのまま残しておく。Zn5
e−ZnSO,l2SeO,l18歪超格子はCaAs
あるいはAI。。
A 1□SeO, 1l11 strained superlattice thin film is epitaxially grown. Z n S e Z n S11 on the rib
.. The 5in2 mask 106 is left as is to prevent deposition of the 12S eo, ea strained superlattice thin film. Zn5
e-ZnSO, l2SeO, l18 strained superlattice is CaAs
Or AI. .

、Ga、、5As上に良好なエピタキシャル成長をする
ため、エツチングで露出したP形りラッド表面及びリブ
側面にエピタキシャル成長される。Zn S e  Z
 n s’o、I!s eo、118歪超格子のエピタ
キシャル成長は、原料にジメチル亜鉛(DMZn)とジ
エチルサルファ(DES)とジメチルセレン(DMSe
)、キャリアガスに純水素(H2)を用いたM OCV
 D (Metal−Organic−Chemica
l−Vapor−D’eposition)法を用いた
, Ga, , 5As, epitaxial growth is performed on the P-shaped rad surface and the rib side surface exposed by etching. Zn S e Z
n s'o, I! The epitaxial growth of the seo, 118 strained superlattice uses dimethylzinc (DMZn), diethylsulfur (DES), and dimethylselenium (DMSe) as raw materials.
), MOCV using pure hydrogen (H2) as carrier gas
D (Metal-Organic-Chemica
1-Vapor-D'eposition) method was used.

成長条件は基板温度が550℃、反応管圧力が35To
 r r、0MZn流量3.  OX 10−’mol
e/sin  D E S流M1. 6X10−5mo
le/min  DMSe流量1 、 2 X l O
−’mole/min  金塊I1.O3LMであり、
DESのオンオフにより歪超格子とする。
The growth conditions are a substrate temperature of 550°C and a reaction tube pressure of 35To.
r r, 0MZn flow rate 3. OX 10-'mol
e/sin D E S style M1. 6X10-5mo
le/min DMSe flow rate 1, 2 X l O
-'mole/min Gold bullion I1. O3LM,
A strained superlattice is created by turning on and off the DES.

成長手順は、第1図(a)に示す基板をMOCVD装置
に挿入し、水素雰囲気中で550 ’Cに加熱し15分
間サーマルエツチングを行ったのち、前述の条件の下で
Z n S e  Z n So、+zS eo、ae
歪超格子薄膜のエピタキシャル成長を行う。ここではD
ESのオンオフは20秒ごとに行い、1周期6.5om
(ZnSe3nm−ZnSo、+zSeo、as3、 
5om)の超格子格造とした。このとき成長速度は0.
6μm/hourである。
The growth procedure was as follows: insert the substrate shown in FIG. 1(a) into an MOCVD apparatus, heat it to 550'C in a hydrogen atmosphere, perform thermal etching for 15 minutes, and then perform Z n S e Z under the aforementioned conditions. n So, +zS eo, ae
Perform epitaxial growth of strained superlattice thin films. Here D
ES is turned on and off every 20 seconds, one cycle is 6.5 ohm.
(ZnSe3nm-ZnSo, +zSeo, as3,
5 ohm) superlattice structure. At this time, the growth rate is 0.
It is 6 μm/hour.

3時間成長を行った後の基板の断面概略図を第1図(b
)に示す。Zn5e−ZnSo、+zSeo。
A schematic cross-sectional view of the substrate after 3 hours of growth is shown in Figure 1 (b).
). Zn5e-ZnSo, +zSeo.

■歪超格子薄膜層108はリブを埋め込んでDH基板上
はぼ平坦にエピタキシャル成長している。
(2) The strained superlattice thin film layer 108 is epitaxially grown almost flat on the DH substrate with ribs buried therein.

一方、Sing?スク106上にはZn5e−ZnSo
、+□Seo、ao歪超格子薄膜の付着が認められず、
Z e S e  Z n So、+zS eo、sa
歪超格子薄膜はSiO□マスク部分を除いた基板上に選
択的に形成された。さらにDH基板のエツチングに用い
たSi0gマスクをそのまま利用しているため、セルフ
ァラインでもある。第1図(C)はSiO2マスクをエ
ツチング除去したのち、P形電極109およびn形電極
110を形成し、へき開して得られたZn5e埋め込み
AlGaAs半導体レーザ素子の断面概略図である。Z
n5e−ZnSo、+zseo、as歪超格子薄膜層1
08は高抵抗(P>10”Ωcm)であるため、P形電
極から注入される。電流はリブに集中して流れ、完全に
電流狭窄層となっている。この半導体レーザ素子は室温
連続発振のしきい値電流が16mA、非点収差1μmと
いう良好な特性を示した。
On the other hand, Sing? Zn5e-ZnSo on the screen 106
, +□Seo, no adhesion of ao strained superlattice thin film was observed,
Z e S e Z n So, +zS eo, sa
A strained superlattice thin film was selectively formed on the substrate excluding the SiO□ mask portion. Furthermore, since the Si0g mask used for etching the DH substrate is used as is, it is also a self-line. FIG. 1C is a schematic cross-sectional view of a Zn5e-embedded AlGaAs semiconductor laser device obtained by etching away the SiO2 mask, forming a P-type electrode 109 and an N-type electrode 110, and cleaving the device. Z
n5e-ZnSo, +zseo, as strained superlattice thin film layer 1
Since 08 has a high resistance (P >10" Ωcm), it is injected from the P-type electrode. The current flows concentrated in the ribs, forming a complete current confinement layer. This semiconductor laser device is capable of continuous oscillation at room temperature. It exhibited good characteristics with a threshold current of 16 mA and an astigmatism of 1 μm.

また、超格子構造により、活性層にかかるストレスが緩
和されるため良好な寿命特性を持ち、光出力20mW、
ケース温度70’Cの条件下において5,000時間の
信頼性試験を行っても駆動型゛流の増加は初期値に比べ
3%以内であった。
In addition, due to the superlattice structure, stress on the active layer is alleviated, resulting in good lifetime characteristics, optical output of 20 mW,
Even when a reliability test was conducted for 5,000 hours at a case temperature of 70'C, the increase in drive current was within 3% compared to the initial value.

(実施例−2) 本発明の第二の実施例として、埋め込み(BH)型半導
体レーザ素子の埋め込み層にZn5e−ZnSo、。1
lset1.92歪超格子薄膜層を用いる場合の形成方
法を説明する。第2図(a)〜(C)は第二の実施例を
説明するもので、BH型半導体レーザ素子の製造工程途
中の基板の断面概略図である。
(Example 2) As a second example of the present invention, Zn5e-ZnSo was used in the buried layer of a buried (BH) type semiconductor laser device. 1
A method of forming an lset1.92 strained superlattice thin film layer will be described. FIGS. 2(a) to 2(C) explain a second embodiment, and are schematic cross-sectional views of a substrate during the manufacturing process of a BH type semiconductor laser device.

製造工程の流れは実施例−1で説明したものと同じであ
る。第2図(a)は埋め込み層を形成する直前の基板の
断面概略図である。n形GaAs基板201上にAlG
aAsより成るストライプ状のDH構造202とS、i
0□マスク203を実施例−1と同様の工程で形成する
。第2図(b)は埋め込み層を形成した後の基板の断面
概略図である。Z n S e  Z n So、os
S eo、qt歪歪超格子力込み層204は厚さ3.2
μmであるが、DH構造の側面を良好に埋め込んでいる
。一方、SiO□マスク203上には付着物はな(、選
択性良く埋め込み層が形成されている。第2図(c)は
P形電極205、n形電極206を形成した後、へき関
して得られたBH型半導体レーザ素子の断面概略図であ
る。このBH型半導体レーザはZn5e−ZnSo、。
The flow of the manufacturing process is the same as that described in Example-1. FIG. 2(a) is a schematic cross-sectional view of the substrate immediately before forming the buried layer. AlG on the n-type GaAs substrate 201
A striped DH structure 202 made of aAs and S,i
A 0□ mask 203 is formed in the same process as in Example-1. FIG. 2(b) is a schematic cross-sectional view of the substrate after forming the buried layer. Z n S e Z n So, os
S eo, qt strain superlattice forcing layer 204 has a thickness of 3.2
μm, but the side surfaces of the DH structure are well buried. On the other hand, there is no deposit on the SiO□ mask 203 (a buried layer is formed with good selectivity). 1 is a schematic cross-sectional view of the obtained BH type semiconductor laser device.This BH type semiconductor laser is made of Zn5e-ZnSo.

S eo、qz歪超格子の良好な結晶性や抵抗率の高さ
(<10IlΩcm)及びGaAsとの大きな屈折率差
(GaAs23.6、Zn5e−ZnSo、osSeo
、qz歪超格子二2.5)により良好な特性を示し、し
きい値電流10mA、非点収差は光出力1mWからl’
QmWまでで1μm以下という理想的な特性が得られた
The good crystallinity and high resistivity of the Seo, qz strained superlattice (<10IlΩcm) and the large refractive index difference with GaAs (GaAs23.6, Zn5e-ZnSo, osSeo
, qz strain superlattice 2.5) shows good characteristics, threshold current is 10 mA, and astigmatism is l' from optical output 1 mW.
Ideal characteristics of 1 μm or less were obtained up to QmW.

なお、以上の実施例ではZn5e  Zn5o、oes
eo、qz歪超格子の側を゛とり挙げたが、本発明の適
用はこの範囲にとどまらない。すなわち、本発明はZn
、Cd、Hgなどの第■族と、S、Se、Te、0など
の第■族との組み合わせによる単結晶及び混晶の薄膜の
形成に適用できる。MOCVDの原料としてメチル系有
機金属を用いたが、エチル系およびその他の有機金属、
水素化物、塩化物およびこれらの混合物等を原料に用い
ても良い。
In addition, in the above examples, Zn5e, Zn5o, oes
Although the eo, qz strained superlattice side has been taken up, the application of the present invention is not limited to this range. That is, the present invention uses Zn
It can be applied to the formation of single crystal and mixed crystal thin films using a combination of group Ⅰ, such as , Cd, Hg, etc., and group ①, such as S, Se, Te, 0, etc. Although methyl-based organometallics were used as raw materials for MOCVD, ethyl-based and other organometallics,
A hydride, a chloride, a mixture thereof, etc. may be used as the raw material.

また、薄膜の成長手段としてMOCVD法をとり上げた
が、本発明は、この他、例えばMBE法、MO−MBE
法、気相輸送法等を利用しても可能である。半導体基板
として、GaAs基板、InP基板の他にSi基板、G
e基板、GaP基板等や、これらの基板上に成長された
異種半導体層を有する半導体基板を用いることができる
。マスクの材質としては、5iOzの他に窒化けい素、
アルミナ等の絶縁帯、タングステン、モリブデン等の金
属等も使用可能である。
In addition, although the MOCVD method has been mentioned as a method for growing a thin film, the present invention is also applicable to other methods such as MBE method, MO-MBE method, etc.
It is also possible to use a method such as a gas phase transport method or a gas phase transport method. In addition to GaAs substrates and InP substrates, Si substrates and G
It is possible to use an e-substrate, a GaP substrate, etc., or a semiconductor substrate having a different type of semiconductor layer grown on these substrates. In addition to 5iOz, the mask materials include silicon nitride,
Insulating bands such as alumina, metals such as tungsten, molybdenum, etc. can also be used.

〔発明の効果] 本発明のII −VI族化合物半導体薄膜製造方法には
、次に述べるような種々の効果を有する。
[Effects of the Invention] The method for producing a II-VI group compound semiconductor thin film of the present invention has various effects as described below.

(1)マスクが予め施すことにより、セルファラインで
薄膜が製造できるため、従来の製造方法に比べてデバイ
ス製造時の後工程が極めて筒略化される。
(1) By applying a mask in advance, a thin film can be manufactured using a self-alignment line, so the post-process during device manufacturing can be extremely simplified compared to conventional manufacturing methods.

(2)超格子を用いることで熱膨張や係数の差や格子不
整に起因する応力が緩和されるため、実施例−1のよう
に半導体レーザの電流狭窄層に用いると、活性層への応
力が著しく小さくなり、半導体レーザの初期特性及び信
顛性が向上する。特に信顛性の向上は顕著であり、MT
TFでは50%以上の向上が見られた。
(2) Using a superlattice relieves stress caused by thermal expansion, coefficient differences, and lattice misalignment, so if it is used in the current confinement layer of a semiconductor laser as in Example 1, stress on the active layer will be reduced. becomes significantly smaller, improving the initial characteristics and reliability of the semiconductor laser. In particular, the improvement in reliability is remarkable, and MT
In TF, an improvement of more than 50% was observed.

また、実施例−2のように半導体レーザの埋め込み層に
用いると、通常のII −VI族化合物半導体で埋め込
んだ場合に比べ、格子欠陥が超格子の弾性により吸収さ
れるため非常に欠陥が減少し光学的特性の良好な埋め込
み層が得られる。
In addition, when used in the buried layer of a semiconductor laser as in Example 2, lattice defects are absorbed by the elasticity of the superlattice, resulting in significantly fewer defects than when buried with a normal II-VI group compound semiconductor. A buried layer with good optical properties can be obtained.

(3)平坦な表面が得られるため、電極形成が容易で、
段差に起因する電極金属の断線が生じない。
(3) Since a flat surface can be obtained, electrode formation is easy;
There is no disconnection of the electrode metal due to the difference in level.

また、実施例−1及び2のように半導体レーザに用いた
場合には、レーザチップのグイボンドが確実になり、半
導体レーザに通電する持主じる熱を効率よく放熱でき、
この面からも信鎖性が向上する」 (4)II−VIl超超格子均一にエツチングする工程
に比べ、選択成長に用いるマスクのエツチング工程はる
かに容易であるため、エツチングプロセスにおいて良好
な再現性が得られ、歩留りが向上する。
In addition, when used in a semiconductor laser as in Examples 1 and 2, the laser chip is firmly bonded, and the heat generated by the owner when the semiconductor laser is energized can be efficiently dissipated.
(4) Compared to the process of uniformly etching the II-VII superlattice, the process of etching the mask used for selective growth is much easier, resulting in good reproducibility in the etching process. is obtained, and the yield is improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)〜(c)は本発明の第一の実施例を説明す
るもので、第1図(a)はZn5e−Znso、oss
eo、qz歪超格子薄膜層を形成する直前の基板の断面
概略図、第1図(b)は成長後の断面概略図、第1図(
C)はZn5e埋め込みAlGaAs半導体レーザ素子
の断面概略図である。 lOl・・n型GaAs基板 102・・n形りラッド層 103・・活性層 104・・P形りラッド層 105・・P型コンタクト層 106・・Sin、マスク 107・・リブ 10B・−ZnSe  Zn5o、osSeo、*z歪
超格子薄膜 109・・P形電極 110・・n形電極 第2図(a)〜(C)は本発明の第二の実施例を説明す
るもので、第2図(a)は埋め込み層を形成する直前の
基板の断面概略図、第2図(b)は形成後の断面概略図
、第2図(C)は得られたBH型半導体レーザ素子の断
面概略図である。 201・−nY3GaAs基板 202・・DH構造 203・・Stowマスク 204・・Zn5e  Zn5o、osSeo、qt歪
超格子埋め込み層 205・・P型電極 206・・n形電極 以上 出願人 セイコーエプソン株式会社 代理人 弁理士 最 上  務(、他1名)−71’ (久) (bン
FIGS. 1(a) to (c) explain the first embodiment of the present invention, and FIG. 1(a) shows Zn5e-Znso, oss
Figure 1(b) is a schematic cross-sectional view of the substrate immediately before forming the eo, qz strained superlattice thin film layer, and Figure 1(b) is a schematic cross-sectional view of the substrate after growth.
C) is a schematic cross-sectional view of a Zn5e-embedded AlGaAs semiconductor laser device. lOl...N-type GaAs substrate 102...N-type rad layer 103...Active layer 104...P-type rad layer 105...P-type contact layer 106...Sin, mask 107...rib 10B...-ZnSe Zn5o , osSeo, *z strained superlattice thin film 109...P-type electrode 110...n-type electrode FIGS. 2(a) to (C) explain the second embodiment of the present invention, and FIG. A) is a schematic cross-sectional view of the substrate immediately before forming the buried layer, FIG. 2(b) is a schematic cross-sectional view after formation, and FIG. 2(C) is a schematic cross-sectional view of the obtained BH type semiconductor laser device. be. 201・-nY3GaAs substrate 202・・DH structure 203・・Stow mask 204・・Zn5e Zn5o, osSeo, qt strained superlattice buried layer 205・・P type electrode 206・・n type electrode and above Applicant Seiko Epson Corporation Agent Patent Attorney Tsutomu Mogami (and 1 other person) -71' (ku) (bn

Claims (1)

【特許請求の範囲】[Claims]  半導体基板表面上の一部にマスクを製造する手段と、
前記マスク以外の前記半導体基板表面上にII−VI族化合
物半導体超格子薄膜を製造する手段を含むことを特徴と
する化合物半導体薄膜製造方法。
means for manufacturing a mask on a portion of the surface of the semiconductor substrate;
A method for manufacturing a compound semiconductor thin film, comprising means for manufacturing a II-VI group compound semiconductor superlattice thin film on the surface of the semiconductor substrate other than the mask.
JP27552887A 1987-10-30 1987-10-30 Compound semiconductor thin film manufacturing method Pending JPH01117386A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27552887A JPH01117386A (en) 1987-10-30 1987-10-30 Compound semiconductor thin film manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27552887A JPH01117386A (en) 1987-10-30 1987-10-30 Compound semiconductor thin film manufacturing method

Publications (1)

Publication Number Publication Date
JPH01117386A true JPH01117386A (en) 1989-05-10

Family

ID=17556710

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27552887A Pending JPH01117386A (en) 1987-10-30 1987-10-30 Compound semiconductor thin film manufacturing method

Country Status (1)

Country Link
JP (1) JPH01117386A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000021169A1 (en) * 1998-10-07 2000-04-13 Sharp Kabushiki Kaisha Semiconductor laser

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000021169A1 (en) * 1998-10-07 2000-04-13 Sharp Kabushiki Kaisha Semiconductor laser
US6618416B1 (en) 1998-10-07 2003-09-09 Sharp Kabushiki Kaisha Semiconductor laser

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