JPH01116693A - Dot matrix display device - Google Patents

Abstract

PURPOSE: To improve the generality of a dot matrix display device by counting the number of display lines of an input signal by the vertical and horizontal synchronizing signals of the input signal and changing address data stored in a ROM in accordance with the counted result. CONSTITUTION: A scanning side number-of-lines discriminating circuit 100 is added to circuits in a conventional dot matrix display device. Data for outputting a signal only to a scanning side shift register 15 without outputting a signal to a modulating circuit/writing circuit 16 and quickly executing transfer about 100 times when specific address data are inputted from a local counter 30 to a P-ROM 80 are previously written in the P-ROM 80. Thereby driving timing for inhibiting display is obtained by changing the address specification of the P-ROM 80 and normal display can be obtained. Consequently a signal can be inputted from the external of, the display device without restricting the number of display lines of the device and the generality of the dot matrix display device can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a dot matrix display device such as a thin film EL display or a plasma display.

<Prior Art> A double insulation type thin film EL display device, which is one type of dot matrix display device, is configured as follows, for example.

As shown in FIG. 2, band-shaped transparent electrodes 2, 2, -, such as 1n201, are provided on a glass substrate 1 in parallel with each other, and dielectric materials 3, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3, 3, such a dielectric material, such as Y2O3, etc., such as Y2O3, etc. E LJi of ZnS doped with activator such as Mn 4. A dielectric material 5 such as YZOt is deposited in this order by a vapor deposition method, a sputtering method, etc.
The film is formed to a thickness of 0.00 to 10,000 to form a three-layer structure, and furthermore, ``transparent electrodes 2, 2-- are formed on the dielectric material N5.
It is provided with a strip-shaped back electrode 6.6- extending in a direction perpendicular to , and is a capacitive element when viewed from an equivalent circuit perspective.

Therefore, by applying a predetermined alternating voltage to the desired transparent electrode 2 and the back electrode 6, the minute area sandwiched between the intersections of the picture electrodes emits light to display characters, symbols, patterns, etc. It constitutes one picture element.

The double-insulated thin-film EL display panel with the above configuration has the following advantages in that it can emit high-intensity light, have a longer lifespan, and is more stable than conventional distributed EL display panels. Are better.

In order to maintain the long-term reliability, readability, stability, etc. of the EL display device without impairing these characteristics,
A drive logic device suitable for the number of scan side and data side electrodes of each EL display panel is required. However, designing drive logic devices individually for display panels having different numbers of electrodes is disadvantageous in terms of cost or time constraints required for development when converting drive logic devices into ICs. In this regard, the present applicant has already demonstrated that multiple types of ELs can be used with one drive logic device without changing the hardware.
It can be applied to display devices, and by integrating the circuitry into a single IC, excluding the P-ROM, etc., which requires changes to the electrode configuration of the display panel, it has the minimum circuit configuration and is versatile. A drive logic device for thin film EL display devices is proposed.

FIG. 3 shows the configuration of this drive logic device. In the figure,
11 is the aforementioned thin film EL display panel, 12 is a scanning side driver group, 13 is a scanning side shift register and latch circuit, 14 is a data side driver group, 15 is a data side shift register and latch circuit, 16 is a modulation circuit and a write drive Each of these 12 to 16 elements constitutes a so-called display drive circuit section.

The part surrounded by the broken line is the drive logic circuit. 20 is a column counter, 30 is a row counter, 35 is a row number setting switch, 40 is an oscillation circuit, 50 is a synchronization signal interface circuit, 60 is a data signal interface circuit,
70 is a latch circuit, and 80 is a P-ROM.

The column counter 20 is a circuit that counts the cycle of one row. The period for one row is determined by the frame frequency and the number of scanning side electrodes, but usually, in order to keep the frame frequency constant, it is determined by the number of scanning side electrodes.

Therefore, in order to change the period so that it can be applied to any EL display panel with a different number of scanning side electrodes, either the oscillation frequency is kept constant and the count number of the column counter 20 is changed, or the count number is kept constant and the oscillation circuit It is necessary to either change the oscillation frequency of 40.

The count number of the row counter 30 must be adapted to the number of electrodes on the scanning side in order to perform line sequential driving.

The outputs of the column counter 20 and row counter 30 are input to the P-ROM 80 as address data. Therefore, the timing required for one row is generated by the column counter 20, and the timing required for one field is generated by sequentially reading the data of the P-ROM 80 by the row counter 30.

The error/f circuit 70 not only latches the output data of the P-ROM 80 to remove noise, but also functions to stop the output due to fluctuations in the power supply.

The synchronization signal interface circuit 50 is a circuit that secures internal drive timing and synchronizes with an external synchronization signal. Details are described in Japanese Patent Application Laid-Open No. 57-42092.

The data signal interface circuit 60 is an interface that allows the data side shift register/latch circuit 15 to be directly controlled by external inputs such as a clock, data, and data valid period signal (which also serves as signal H in FIG. 3). It is a circuit.

The details are also described in Japanese Unexamined Patent Publication No. 57-42092.

The row counter 30 does not have a fixed count number, but has a margin in the counter, and by combining it with the row number setting switch 35, the count number can be set arbitrarily, and it is applicable to many types of EL display panels.

Further, in the P-ROM 80, when the count period of the column counter 20 and the count number of the row counter 30 are changed, the P-ROM data can be changed accordingly without changing the hardware.

The integration of such logic circuits into ICs has the effect of reducing circuit costs and improving productivity during mass production of EL display devices, and also
The entire device can be made smaller.

<Problems to be Solved by the Invention> In the prior art, for an EL% channel with a certain number of electrodes on the scanning side, the line number setting switch 35 and the P-ROM 80 are
For example, the data side 640 is fixed.
If you want to display only 640 lines x 400 lines using a panel with 480 electrodes on the scanning side, change the line number setting switch 35, change the P-ROM data, and even change the scanning side driver group. It was also necessary to replace it with one that matched the number of lines. Alternatively, it was necessary to process the signal externally so as to display only 640 lines x 400 lines.

In this way, if you want to use only some of the scanning lines of an EL display device with a large display capacity, you will need to either make a hardware change that is equivalent to replacing the entire display device, or
Alternatively, the only option was to manipulate the signals externally and change the software to accommodate them. Therefore, there are also problems in terms of cost and use of the device.

<Means for Solving the Problems> The present invention provides a dot matrix display device that performs display drive according to data in a ROM in which drive timing data for dot matrix display is written. A ROM in which the drive timing for not displaying is written as data, a counter that counts the number of display lines of the input signal according to the vertical and horizontal synchronization signals of the input signal, and a data processing means that changes the address data of the ROM according to the count result. Equipped with.

According to the present invention, in a dot matrix display device capable of displaying 480 scanning lines, even if input signals for only 400 scanning lines are given, 100 lines are counted and the remaining 80 lines are counted. By changing the address designation of the P-ROM, the drive timing is changed so that no display is performed, and a normal display can be obtained. Therefore, signals can be input outside the display device without being limited by the number of display lines of the device, and the versatility of the dot matrix display device is increased.

<Embodiment> FIG. 1 shows the configuration of a dot matrix display device of this embodiment. The circuit is basically the same as the circuit of the conventional dot matrix display device shown in FIG. 3, except that a scanning side line number discriminating circuit 100 is added. The scanning side line number determination circuit 100 provides control signals A and B to the low counter 30 and the latch circuit 70 in accordance with the input signals H and V. In addition, when specific address data is input from the row counter 30, the P-ROM 80 does not output a signal to the modulation circuit and write circuit 16, but outputs a signal only to the shift register 15 on the scanning side, and For example, write data that will be transferred about 100 times. The number of transfers depends on the difference between the actual number of displayable lines and the number of signal lines.

The operation of the scanning side line number determination circuit 100 will be described below.

First, one field after the signal ■ is input.

During this period, the output A is input to the latch circuit 70, and the output of the latch circuit 70 is stopped. During this period, the scanning side line number determining circuit 100 counts the signal H for one field period, determines the number of scanning lines of the input signal, and outputs the same output B as the line number setting switch 35 for the next field period. is input to the low counter 30. When the count number of the row counter 30 is B earlier than the set value of the row number setting switch 35,
When the input value is reached, the specific address is stored in the P-ROM 80.
As described above, only the transfer of the shift register 15 on the scanning side is performed, and thereafter, similar driving is performed up to the set value of the row number setting switch 35, and nothing is displayed during this period. Therefore, for example, if 400 lines are input with the number of lines set to 480, nothing will be displayed for 80 lines, and the display device can essentially be used as a display device for 400 lines.

Although the drive logic circuit for a thin film EL display device has been described in the above embodiment, it goes without saying that the present invention can be applied to a similar structure to a matrix type display device. Further, in the above embodiment, only the number of lines on the scanning side was determined, but if necessary, it is possible to perform the determination on the data side using a similar configuration.

<Effects of the Invention> As described above, according to the present invention, even in a dot matrix display device with a large display dot structure, a screen with a small dot structure can be displayed without deteriorating the display quality. It is possible to increase the versatility of the display device, and there is an advantage that the software for computers and the like related to the screen configuration can be used as is without modification.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the circuit configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the structure of a thin film EL display panel, and FIG. 3 is a diagram showing the circuit configuration of a conventional example. 11...EL panel 12...Scanning side driver group 13...Shift register and launch circuit 14...Data side driver group 15...Shift register and latch circuit 16...Modulation circuit and write circuit 20 ...Column counter 30...Low counter 40...Oscillation circuit 50...Synchronization signal interface circuit 60...Data signal interface circuit 70...Latch circuit 80...P-ROM 90... Drive logic circuit patent applicant Sharp Co., Ltd. Agent Patent attorney Nishi 1) New Figure 2 1112 Figure 3

Claims (1)

[Claims] A ROM in which the drive timing for not displaying the scanning line of the dot matrix display is written as data, a counting means for counting the number of display lines of the input signal according to the vertical and horizontal synchronization signals of the input signal, and a counter according to the counting result of the counting means. A dot matrix display device comprising: data processing means for changing addressing data of a ROM.