JPH01112743A - Ic packaging circuit board - Google Patents
Ic packaging circuit boardInfo
- Publication number
- JPH01112743A JPH01112743A JP62271137A JP27113787A JPH01112743A JP H01112743 A JPH01112743 A JP H01112743A JP 62271137 A JP62271137 A JP 62271137A JP 27113787 A JP27113787 A JP 27113787A JP H01112743 A JPH01112743 A JP H01112743A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- circuit board
- mounting
- electrode
- positioning protrusions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004806 packaging method and process Methods 0.000 title abstract 3
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 3
- 239000004020 conductor Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000012790 confirmation Methods 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 21
- 239000010410 layer Substances 0.000 description 15
- 238000000206 photolithography Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000002594 fluoroscopy Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/303—Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 〔技術分野〕 この発明は、ＩＣ実装用回路基板に関する。[Detailed description of the invention] 〔Technical field〕 The present invention relates to a circuit board for IC mounting.
ＩＣをＩＣ実装用回路基板に実装するには、たとえば、
第２図にみるように、ＡｕやＡＡの細線１を用いてＩＣ
２の電極３とＩＣ実装用回路基板４の電路５とを電気的
に接続するというワイヤボンディングが利用されている
。しかし、ワイヤボンディングでは、電極数の増加に伴
ってボンディングに要する時間が増大するので、高密度
実装や高集積化に対応することが困難になってきている
そこで、突起電極を用いて、ＩＣの電極とＩＣ実装用回
路基板の電路とを一括して電気的に接続するという、ギ
ヤングボンディング法が提案されている。この方法には
、ＩＣの方に突起電極を設ける方法と、ＩＣ実装用回路
基板の方に突起電極を設ける方法とがある。前者の方法
の１つにフリップチップ法というのがある。これは、第
３図（ａ）にみるように、ＩＣ２に突起電極（バンブ）
６を設け、これらの突起電極６を一括してＩＣ実装用回
路基板４の各電路５に熱圧着するという方法である。し
かし、この方法では、ＩＣの製造工程において、突起電
極を形成するという工程を付加する必要がある。この工
程では、第３図（ｂ）にみるように、突起電極６の主な
材料であるＡｕやはんだ等がＩＣ２内へ拡散するのを防
ぐバリアメタル眉７や、ＩＣ−突起電極間の接合力を高
める接着層８を形成する必要があり、複雑で高価なもの
になる。図中、９はパッシベーション層、１０はＩＣの
／ｌ電極である。To mount an IC on an IC mounting circuit board, for example,
As shown in Figure 2, an IC is
Wire bonding is used to electrically connect the electrodes 3 of 2 and the electric paths 5 of the IC mounting circuit board 4. However, with wire bonding, the time required for bonding increases as the number of electrodes increases, making it difficult to support high-density mounting and high integration. A gigantic bonding method has been proposed in which the electrodes and the electric paths of the circuit board for IC mounting are electrically connected together. This method includes a method in which protruding electrodes are provided on the IC, and a method in which protruding electrodes are provided on the IC mounting circuit board. One of the former methods is the flip-chip method. As shown in Figure 3(a), this means that there is a protruding electrode (bump) on IC2.
6 are provided, and these protruding electrodes 6 are collectively bonded to each electric circuit 5 of the IC mounting circuit board 4 by thermocompression. However, in this method, it is necessary to add a step of forming a protruding electrode to the IC manufacturing process. In this step, as shown in FIG. 3(b), a barrier metal layer 7 is formed to prevent Au, which is the main material of the protruding electrode 6, solder, etc., from diffusing into the IC 2, and a bond between the IC and the protruding electrode is formed. It is necessary to form an adhesive layer 8 to increase the force, which is complicated and expensive. In the figure, 9 is a passivation layer, and 10 is a /l electrode of the IC.
これに対し、第４図にみるように、ＩＣ実装用回路基板
４の方にペデスタルと称される突起電極１２を形成して
おき、ＩＣ２をボンディングするという方法（「ペデス
タル法」ということもある）も提案されている。この方
法は、ＩＣを新たに加工する必要がなく、しかも、ＩＣ
側に突起電極を設ける方法に比べて、安価に突起電極を
形成できるという利点がある。しかし、ＩＣ実装用回路
基板側の突起電極とＩＣの電極との位置合わせに高い精
度が要求される上、ＩＣ実装用回路基板とＩＣとを接合
すると、接続部がＩＣと基板との間に隠れてしまうため
、突起電極とＩＣの電極との位置合わせや接合状態を確
認できないという問題点がある。On the other hand, as shown in FIG. 4, there is a method (sometimes called the "pedestal method") in which a protruding electrode 12 called a pedestal is formed on the IC mounting circuit board 4 and the IC 2 is bonded. ) has also been proposed. This method does not require any new processing of the IC, and
This method has the advantage that the protruding electrode can be formed at a lower cost than the method of providing the protruding electrode on the side. However, high precision is required for alignment between the protruding electrodes on the circuit board for IC mounting and the electrodes of the IC, and when the circuit board for IC mounting and the IC are bonded, the connection part is between the IC and the board. Since it is hidden, there is a problem in that it is impossible to check the alignment and bonding state between the protruding electrode and the IC electrode.
この発明は、以上のことに鑑みて、ＩＣを実装した後に
、ＩＣと基板上の突起電極との相対位置を確認すること
ができるＩＣ実装用回路基板を提供することを目的とす
る。In view of the above, an object of the present invention is to provide a circuit board for mounting an IC on which the relative position of the IC and the protruding electrodes on the board can be confirmed after mounting the IC.
この発明は、主起目的を達成するため、絶縁層表面に形
成された電路上に突起電極が設けられていて、同突起電
極とＩＣの電極とがボンディングされるようになってい
るＩＣ実装用回路基板において、前記絶縁層表面の前記
ＩＣの外形よりも外側の部分には、前記突起電極の形成
と同時に形成された位置決め用突起が設けられているこ
とを特徴とするＩＣ実装用回路基板を要旨とする。In order to achieve the main purpose, this invention is for IC mounting, in which a protruding electrode is provided on a conductor formed on the surface of an insulating layer, and the protruding electrode is bonded to an electrode of an IC. A circuit board for IC mounting, characterized in that a positioning protrusion formed at the same time as the formation of the protruding electrode is provided on a portion of the surface of the insulating layer outside the outer shape of the IC. This is the summary.
以下に、この発明を、その実施例を表す図面を参照しな
がら詳しく説明する。Hereinafter, the present invention will be explained in detail with reference to the drawings showing embodiments thereof.
第１図（ａ）および（ｂ）は、この発明にかかるＩＣ実
装用回路基板の１実施例を表す。これらの図にみるよう
に、このＩＣ実装用回路基板１４は、絶縁層１６の表面
上に所望の電路５が形成されている。各電路５のＩＣ（
半導体素子）２の電極３とのボンディング部分には、突
起電極（「バンプ」ともいう）１２が設けられている。FIGS. 1(a) and 1(b) show one embodiment of an IC mounting circuit board according to the present invention. As seen in these figures, in this IC mounting circuit board 14, a desired electric path 5 is formed on the surface of an insulating layer 16. IC of each electric circuit 5 (
A protruding electrode (also referred to as a "bump") 12 is provided at the bonding portion of the semiconductor element 2 with the electrode 3.
各電路５の前記ボンディング部分は、四方から四角い空
所を形成するように臨んでいる。その１組の対角位置に
臨んでいる２つの電路５ａ、５ａは、それぞれ、側方へ
枝分かれしていてその先端に位置決め用突起１７．１７
が設けられている。これら位置決め用突起１７．１７は
、ＩＣが実装された時に、その外形よりも外側となると
ころに位置している。The bonding portion of each electric circuit 5 faces from all sides so as to form a square void. The two electric circuits 5a, 5a facing the pair of diagonal positions are branched laterally, and each has a positioning projection 17, 17 at its tip.
is provided. These positioning protrusions 17.17 are located outside the outer shape of the IC when it is mounted.
ＩＣ実装用回路基板にボンディング用の突起電極を形成
するには、たとえば、下記のようにして行うが、これに
限定されない。絶縁層の上に所望のパターンで電路とな
る導体層を形成する。前記パターンは、たとえば、第１
図（ａ）にみるように、ボンディング用の電路と位置決
め用突起を形成するための電路からなる。この上にホト
レジストを塗布して前記導体層を覆い、ホトリソグラフ
ィー法により、導体層上の必要な位置にホトレジストの
孔をあける。このとき、位置決め用突起を設けるための
孔もあける。そして、前記電路を電極として、それらの
孔の中を電気メツキ等によりＡｕ等の突起電極用材料で
埋めて、前記導体層の上に突起電極と位置決め用突起を
形成する。各突起電極の相対位置は、ホトリソグラフィ
ー工程のマスク精度（マスクのパターン精度）と等しく
、通常、０．１μｍ以下のずれである。また、各突起電
極と位置決め用突起との相対位置も同様の精度である。The protruding electrodes for bonding can be formed on the circuit board for IC mounting in the following manner, but the present invention is not limited thereto. A conductive layer serving as an electric path is formed in a desired pattern on the insulating layer. The pattern may be, for example, a first
As shown in Figure (a), it consists of an electric path for bonding and an electric path for forming positioning protrusions. A photoresist is applied thereon to cover the conductor layer, and holes are made in the photoresist at required positions on the conductor layer by photolithography. At this time, holes for providing positioning protrusions are also made. Then, using the electrical path as an electrode, the holes are filled with a protruding electrode material such as Au by electroplating or the like to form protruding electrodes and positioning protrusions on the conductor layer. The relative position of each protruding electrode is equal to the mask precision (mask pattern precision) of the photolithography process, and is usually deviated by 0.1 μm or less. Further, the relative positions of each protruding electrode and the positioning protrusion have similar accuracy.
これらの精度は、ＩＣを実装するときの位置合わせ精度
に比べて問題にならないくらい高いレベルである。他方
、電路に対する突起電極の位置楕゛度は、マスク位置合
わせ精度に依存するため、１μｍ以上のオーダーのずれ
が生じる。These accuracies are at a level so high that they do not pose a problem compared to the alignment accuracy when mounting the IC. On the other hand, since the positional ellipse of the protruding electrode with respect to the electric path depends on the mask alignment accuracy, a deviation on the order of 1 μm or more occurs.
したがって、ＩＣのＩＣ実装用回路基板への位置合わせ
をＩＣの外形と基板上の電路とで行うと、ＩＣの電極と
ｒｃ実装用回路基板の突起電極とがずれてしまい、電気
的な接続が行えないことがある。Therefore, if the IC is aligned with the circuit board for IC mounting based on the outer shape of the IC and the electric circuit on the board, the electrodes of the IC and the protruding electrodes of the circuit board for RC mounting will be misaligned, and the electrical connection will be disrupted. There are some things I can't do.
そこで、前述のごとく、実装しようとするＩＣの外形よ
りも少し外側に、位置決め用突起（これは電気的接続に
関与しないので、「ダミーバンプ」である）を設けてお
゛き、この突起とＩＣの外形との間隔を測定すれば、Ｉ
Ｃの電極と突起電極との位置精度が確認できる。Therefore, as mentioned above, a positioning protrusion (this is a "dummy bump" as it is not involved in electrical connection) is provided a little outside the outline of the IC to be mounted, and this protrusion and IC If you measure the distance from the outer shape of
The positional accuracy of the electrode C and the protrusion electrode can be confirmed.
前記絶縁層としては、たとえば、アルミナ基板等のセラ
ミック基板、ガラスエポキシ基板等の樹脂を用いた基板
などがあり、特に限定はない。導体層の材料も特に限定
はなく、たとえば、金属銅゛などが用いられる。導体層
の形成方法も特に限定はなく、たとえば、メツキ・真空
蒸着・スパッタリング等により薄膜を形成して所望のパ
ターンを残してエツチングするという方法で形成するこ
とができる。ＩＣの電極は、特に限定はないが、たとえ
ば、Ａ１電極などが使用される。Examples of the insulating layer include a ceramic substrate such as an alumina substrate, a substrate made of resin such as a glass epoxy substrate, and the like, and is not particularly limited. The material of the conductor layer is also not particularly limited, and for example, metal copper or the like may be used. The method of forming the conductor layer is not particularly limited either, and for example, it can be formed by forming a thin film by plating, vacuum evaporation, sputtering, etc., and then etching it leaving a desired pattern. Although the electrode of the IC is not particularly limited, for example, an A1 electrode is used.
この発明において、突起電極の形成と位置決め用突起の
形成とを同時に行うのは、位置決め用突起と突起電極と
の位置精度を突起電極同士の位置精度と同程度にするた
めである。上記実施例では、ホトレジストのホトリソグ
ラフィー工程で、位置決め用突起と突起電極となる部分
のホトレジストに孔をあけることにより、位置決め用突
起と突起電極との位置精度を得ている。しかし、この位
置精度を得るためには、ホトレジストの必要な部分にホ
トリソグラフィーにより孔をあけるという方法を利用す
る必要はない。また、ホトリソグラフィー工程の後、電
気メツキによらず、化学メツキ・真空蒸着・スパッタリ
ング等によって突起電極と位置決め用突起を形成しても
よく、突起電極と位置決め用突起とを別の手段で形成し
てもよい。要するに、位置決め用突起と各突起電極との
位置精度が各突起電極相互間の位置精度と同程度となる
のであれば、上記以外のやり方で行ってもよいのである
。In this invention, the reason why the protruding electrodes and the positioning protrusions are formed at the same time is to make the positional accuracy between the positioning protrusions and the protruding electrodes comparable to the positional accuracy between the protruding electrodes. In the above embodiment, the positioning accuracy of the positioning protrusions and the protruding electrodes is obtained by drilling holes in the photoresist at the portions that will become the positioning protrusions and protruding electrodes in the photolithography process of the photoresist. However, in order to obtain this positional accuracy, it is not necessary to use a method of making holes by photolithography in the required portions of the photoresist. Further, after the photolithography process, the protruding electrodes and positioning protrusions may be formed by chemical plating, vacuum evaporation, sputtering, etc., instead of electroplating, or the protruding electrodes and positioning protrusions may be formed by another method. You can. In short, as long as the positional accuracy between the positioning protrusion and each protruding electrode is comparable to the positional accuracy between the protruding electrodes, methods other than those described above may be used.
この発明にかかるＩＣ実装用回路基板は、突起電極の形
成と同時に形成された位置決め用突起を有するので、Ｉ
Ｃを実装するときに、その位置決め用突起を利用して位
置合わせ状態を確認することができる。しかも、その位
置合わせ精度が高い。ＩＣ実装後の位置合わせ状態の確
認は、超音波・赤外線顕微鏡・Ｘ線透視装置等の高価な
設備を用いる必要がなく、しかも、非破壊で行うことが
できる。これにより、ＩＣ実装工程のスピード向上、設
備投資のコストダウンを図ることができ、全体として実
装コストの低減を図ることができる。また、位置決め用
突起と突起電極の形成を同時に行えば、工程が少なくて
すみ、精度も同程度にすることができる。The IC mounting circuit board according to the present invention has positioning protrusions formed at the same time as the protrusion electrodes, so that
When mounting C, the alignment state can be confirmed using the positioning protrusion. Furthermore, the alignment accuracy is high. Confirmation of the alignment state after IC mounting does not require the use of expensive equipment such as ultrasonic waves, infrared microscopes, or X-ray fluoroscopes, and can be performed non-destructively. As a result, it is possible to improve the speed of the IC mounting process, reduce the cost of equipment investment, and reduce the overall mounting cost. Furthermore, if the positioning protrusions and the protruding electrodes are formed at the same time, the number of steps can be reduced and the accuracy can be maintained at the same level.
なお、この発明にかかるＩＣ実装用回路基板は、上記実
施例に限定されない。たとえば、位置決め用突起は、実
装しようとするＩＣの対角位置に２つ設けていたが、３
つ以上でもよ（，１つでもよい。精度をより高めるとい
う点からは、位置決め用突起は２つ以上設けることが好
ましい。また、その設ける位置も、ＩＣとの間隔の計測
が容易な場所であれば、特に限定はなく、電路の上に形
成される必要もない。位置決め用突起の形状も、円形に
限らず、四角形などの多角形やＬ字形などであってもよ
い。位置決め用突起の材料も導体である必要はない。Note that the IC mounting circuit board according to the present invention is not limited to the above embodiments. For example, two positioning protrusions were provided at diagonal positions of the IC to be mounted, but three
The number of positioning protrusions may be two or more (or one is also acceptable. From the point of view of increasing accuracy, it is preferable to provide two or more positioning protrusions. Also, the positioning protrusions should be placed in a place where it is easy to measure the distance between them and the IC. If there is, there is no particular limitation and there is no need to form it on the electric circuit.The shape of the positioning protrusion is not limited to a circle, but may also be a polygon such as a square or an L-shape. The material also does not need to be a conductor.
この発明にかかるＩＣ実装用回路基板は、以上のように
、絶縁層表面のＩＣの外形よりも外側の部分には、突起
電極の形成と同時に形成された位置決め用突起が設けら
れているので、ＩＣを精度良くボンディングすることが
できる。ボンディング後は、超音波、赤外線顕微鏡ある
いはＸ線透視装置などといった高価な設備を用いずに、
しかも、破壊を行わずに、突起電極とＩＣの電極の位置
精度が確認できる。このため、工程のスピード向上、設
備投資のコストダウンを図ることができ、全体的に実装
コストの低減を図ることができる。As described above, in the IC mounting circuit board according to the present invention, the positioning protrusion is provided on the surface of the insulating layer outside the IC outline, and the positioning protrusion is formed at the same time as the protrusion electrode is formed. ICs can be bonded with high precision. After bonding, there is no need to use expensive equipment such as ultrasound, infrared microscopes, or X-ray fluoroscopy equipment.
Moreover, the positional accuracy of the protruding electrodes and the IC electrodes can be confirmed without destroying them. Therefore, it is possible to improve the speed of the process, reduce the cost of equipment investment, and reduce the overall mounting cost.
第１図（ａ）はこの発明にかかるＩＣ実装用回路基板に
ＩＣを搭載した状態を表す一部分の平面図、第１図（ｂ
）はその搭載直前の断面図、第２図・第３図（ａ）・第
４図はそれぞれ従来のボンディングのやり方を表す一部
分の側面図、第３図（ｂｌはＩＣ側に形成する突起電極
の１例を表す断面図である。
２・・・ＩＣ３・・・ＩＣの電極 ５，５ａ・・・電路
１２・・・突起電極 １４・・・ＩＣ実装用回路基板
１６・・・絶縁層 １７・・・位置決め用突起代理人
弁理士 松 本 武 彦
第１ 図
（ａ）
第２図
第３図
（ａ）（ｂ）
第４図FIG. 1(a) is a partial plan view showing a state in which an IC is mounted on an IC mounting circuit board according to the present invention, and FIG.
) is a sectional view immediately before mounting, Figures 2, 3 (a), and 4 are partial side views showing the conventional bonding method, and Figure 3 (bl is a protrusion electrode formed on the IC side). 2... IC3... IC electrode 5, 5a... Electrical path 12... Protruding electrode 14... IC mounting circuit board
16... Insulating layer 17... Protrusion agent for positioning
Patent Attorney Takehiko Matsumoto Figure 1 (a) Figure 2 Figure 3 (a) (b) Figure 4
Claims (1)
られていて、同突起電極とＩＣの電極とがボンディング
されるようになっているＩＣ実装用回路基板において、
前記絶縁層表面の前記ＩＣの外形よりも外側の部分には
、前記突起電極の形成と同時に形成された位置決め用突
起が設けられていることを特徴とするＩＣ実装用回路基
板。(1) In a circuit board for IC mounting, in which a protruding electrode is provided on the electric conductor formed on the surface of the insulating layer, and the protruding electrode and the electrode of the IC are bonded.
A circuit board for mounting an IC, characterized in that a positioning protrusion formed at the same time as the formation of the protruding electrode is provided on a portion of the surface of the insulating layer outside the outer shape of the IC.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62271137A JPH01112743A (en) | 1987-10-27 | 1987-10-27 | Ic packaging circuit board |
| DE3817600A DE3817600C2 (en) | 1987-05-26 | 1988-05-24 | Method of manufacturing a semiconductor device with a ceramic substrate and an integrated circuit |
| FR8806997A FR2617335B1 (en) | 1987-05-26 | 1988-05-26 | CERAMIC CONNECTION SUBSTRATE PROVIDED WITH CONNECTION PROTUBERANCES TO THE INTEGRATED CIRCUIT PELLET |
| US07/504,028 US5126818A (en) | 1987-05-26 | 1990-04-02 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62271137A JPH01112743A (en) | 1987-10-27 | 1987-10-27 | Ic packaging circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01112743A true JPH01112743A (en) | 1989-05-01 |
| JPH0474863B2 JPH0474863B2 (en) | 1992-11-27 |
Family
ID=17495831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62271137A Granted JPH01112743A (en) | 1987-05-26 | 1987-10-27 | Ic packaging circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01112743A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7250329B2 (en) | 2004-05-31 | 2007-07-31 | Shinko Electric Industries Co., Ltd. | Method of fabricating a built-in chip type substrate |
-
1987
- 1987-10-27 JP JP62271137A patent/JPH01112743A/en active Granted
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7250329B2 (en) | 2004-05-31 | 2007-07-31 | Shinko Electric Industries Co., Ltd. | Method of fabricating a built-in chip type substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0474863B2 (en) | 1992-11-27 |
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