JPH01110277A - Tester comparing circuit - Google Patents

Abstract

PURPOSE:To perform the test relating to an access time under the worst condition, by setting the magnitude and direction of the load current of the load to a circuit to be measured on the basis of the expected value data corresponding to a test pattern. CONSTITUTION:An output data comparing and judge circuit 3 is connected to the output terminal of a circuit 1 to be measured and a load current control circuit 2 constituted of a transistor, a resistor and constant voltage change-over circuits 4, 5 and generating an inflow constant current J1 or an induced constant current J2 on the basis of a load control signal T is further connected thereto. Then, by changing over the load control signal T in arbitrary timing in accordance with the expected value data corresponding to a test pattern, the test relating to the access time of data or the test of a try state output state is performed under a condition nearer to actual use.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a testing method for digital circuits, and particularly to a tester comparison circuit suitable for use in detecting abnormalities in output circuits and testing driving ability.

[Conventional technology]

2. Description of the Related Art As a prior art related to a device for testing digital circuits, there is known a technique described in, for example, the T3340 Tester Programming Manual published by Advanced Test Co., Ltd. This type of conventional technology has
Equipped with a load circuit that can set constant current values in each direction for sinking and sinking, it tests digital circuits by setting the direction and magnitude of the load current according to the operation when the output circuit operates. be.

[Problem that the invention seeks to solve]

The above-mentioned conventional technology is passive in that the output circuit of the digital circuit under test operates and a voltage is output, and then the direction of the constant current is determined according to the level. For example, there has been a problem in that it is not possible to perform sufficient tests on access time, differences in output signals with respect to expected values, etc.

An object of the present invention is to set a constant current generated based on expected value data in the output circuit before the output operation of the circuit under test starts, thereby setting the worst condition for the output circuit and improving the driving ability. An object of the present invention is to provide a tester comparison circuit for digital circuit testing, which makes it possible to improve test accuracy, defect detection, and other test capabilities.

[Means for solving problems]

According to the present invention, the object is to create data necessary for determining the direction of the current to be passed to the output terminal of the circuit under test from the expected value data generated by the pattern generator, and thereby to This is achieved by including a load current control circuit that switches between a constant current source for inflowing and a constant current source for sinking at specified timing, and a comparison judgment circuit that makes a judgment with respect to the output level.

[For production]

The load current control circuit operates to flow a current in the direction determined from the expected value or in the opposite direction to the output terminal of the circuit under test, and the comparison judgment circuit operates in the conventional manner for the output level determined by this. Make a comparative judgment. Thereby, it is possible to perform tests suitable for actual use of the circuit, such as testing the driving ability of the digital circuit and testing the access time.

〔Example〕

Hereinafter, one embodiment of the tester comparison circuit according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, and FIGS. 2(a) and 2(b) are timing charts illustrating testing of an output circuit having a tri-state state. In FIG. 1, 1 is a circuit to be measured, 2 is a load current control circuit, 3 is an output data comparison/judgment circuit, 4 is a constant voltage switching circuit A, and 5 is a constant voltage switching circuit B.

The tester comparison circuit according to the present invention, as shown in FIG.
Load current control circuit 2 and data comparison/judgment circuit 3
It is composed of The load current control circuit 2 is
Consisting of a transistor, a resistor, a constant voltage switching circuit A4, and a constant current switching circuit B5, when the load current control signal T is at a high level, a constant current J is injected, and when the signal T is at a low level, a constant current J is drawn out. , is connected to the output terminal of the circuit under test 1 so as to generate . At this time, the terminal voltage is VHI im % vLl
limited by im. Output data comparison judgment circuit 3
The output signal level of the circuit under test 1, which is determined by the load current control circuit 2 and the output signal of the circuit under test 1 based on the input signal that is the test pattern, is compared with the reference voltage level, and the same comparison judgment as in the conventional method is performed. I do. FIG. 1 shows a load current control circuit 2 and an output data comparison/judgment circuit 3.
It becomes possible to test one indicator data at the same time.

Hereinafter, with reference to FIG. 2, the operation when testing an output circuit having a tri-state state using the circuit shown in FIG. 1 will be explained.

In FIG. 2(a), for example, a high signal is read from the memory during the test cycle 1+, and the high signal is read from the memory during the test cycle t. A time chart is shown when performing a test to read the W signal. Figure 2(a)
The waveform A is the expected value data waveform of the measured circuit 1,
A high signal should be read out during period t,
Period t! This indicates that a Low signal should be read out. When performing this test, the load current control circuit 2 controls the load current with an inverted waveform of the expected value data waveform A, as shown by waveform B in FIG. 2(a).

Therefore, during period t, the voltage level of the output terminal of the circuit under test 1 is at the L level determined by the control current of waveform B when there is no readout output of the High signal, but when the Htgh signal is read out. At this time, it becomes H level. Further, in the period t, the signal goes to the H level when there is no reading output of the Low signal, and goes to the L level when the Low signal is read out, contrary to the above. As a result, if High and Low signals are normally read out from the circuit under test 1 during test periods 1+ and 1-, the output level of the output terminal of the circuit under test 1 will be the same as wave C in FIG. 2(a). It will change like this. The output data comparison and judgment screen N3 tests the driving ability of the circuit under test 1 by judging the voltage level of this waveform C, and also by checking the output timing of the output data by the H5gh signal and the Low signal. , it is possible to conduct tests regarding access time.

Incidentally, in the case of the circuit of the prior art, the voltage at the output terminal of the circuit under test 1 is, as shown in the waveform of FIG. The voltage is at an intermediate level determined by the load, and the output data comparison judgment circuit 3
It was necessary to judge three types of voltage levels.

FIG. 2(b) shows a test when the output circuit of the circuit under test 1 having a tri-state state is outputting an intermediate level signal, that is, when testing is performed when the output circuit is open. It shows a time chart. In this case, the load current control circuit changes the signal level of the output terminal of the circuit under test 1 to H level during the test cycle 11, as shown as waveform B in FIG. The load current is controlled so that it is at L level during the period. At this time, the output terminal of the circuit under test 1 should be open, so the expected value for the test result is as shown in waveform A in FIG. 2(b) above. If the output circuit of the circuit under test 1 is correctly open, the test result will be the same as waveform B, as shown as waveform C in FIG. 2(b). It becomes the same as waveform B. By determining the level of this waveform C, the output data comparison and determination circuit 3 can test the normality of the output circuit of the circuit under test 1 when outputting an intermediate level.

Incidentally, in the case of the conventional circuit, the voltage at the output terminal of the circuit under test 1 is at a constant intermediate level determined by the load, as shown in the waveform in FIG. , the test was performed by detecting this intermediate level voltage.

In one embodiment of the present invention described above, test cycle 1*=1
Although the load current control circuit 2 is described as supplying the load current to the output terminal of the circuit under test 1 without changing the magnitude and direction of the load current during the period of the present invention, the present invention The magnitude and direction of the load current may be switched during the cycle 1+-11.

For example, when the output data of the circuit under test 1 changes within one test cycle, the load current control circuit 2 can switch the load current according to the change in the output data, and the present invention This makes it possible to dynamically test the circuit under test.

According to the embodiment of the present invention described above, in a test regarding the drive ability of the output circuit of the circuit under test and the access time of read data, it is possible to set the worst conditions and perform the test under those conditions. Further, it is possible to test the tri-state output state under conditions closer to actual use.

〔Effect of the invention〕

As explained above, according to the present invention, the load current value and current direction can be switched to the output section of the circuit under test at any timing according to the expected value of each test cycle, which was previously impossible. The test conditions can be set according to the test content.

From this, the present invention can perform strict testing of the driving ability of the output part of the circuit under test, testing in accordance with the actual usage situation when measuring the tri-state state, etc. This has the effect of improving detection ability.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a circuit showing an embodiment of the present invention, and FIGS. 2(a) and 2(b) are timing charts illustrating testing of an output circuit having a tri-state state.

Claims (1)

[Scope of Claims] 1. In a digital circuit testing device comprising a load for a circuit under test to which a test pattern is applied and a data comparison/judgment section, as a load, according to expected value data of an output corresponding to the test pattern, A tester comparison circuit characterized by comprising a load current control circuit that sets the magnitude and direction of the load current flowing through the output section of the circuit under test. 2. The tester comparison circuit according to claim 1, wherein the load current control circuit is capable of switching the magnitude and direction of the load current at any timing during each test cycle.